The National Institute of Engineering, Mysuru
Manandavadi Road, Mysuru – 570 008, Karnataka, INDIA
(An Autonomous Institute under Visvesvaraya Technological
University, Belagavi)
Department of Electronics and Communication
Engineering
The National Institute of Engineering
(An Autonomous Institute under Visvesvaraya Technological
University, Belagavi)
Submitted by
Ningaraddy-4NI21EC069
Nuthan M N-4NI21EC073
Santosh-4NI21EC094
Sathwik-4NI21EC095
Siddesh N S-4NI21EC104
Under The Guidance of
Dr. Shashidhara H R sir
Associate Professor
Department of Electronics and Communication engineering
The National Institute of Engineering
(An Autonomous Institute under Visvesvaraya Technological
University, Belagavi)
Table of conTenT
SL.NO CONTENT Page. No
1 Declaration 1
2 Acknowledgement 2
3 Abstract 3
4 Introduction 4-5
5 Design And Working 6-7
Of DRAM
6 Verilog Code and Test 8-11
Bench
7 Detailed explanation 12-14
Of code
8 Output Waveforms 14-15
9 Conclusion and References 16
DeclaraTion
We hereby declare that this project work entitled "Analysis and
Design Of 32-bit DRAM Memory" is for an original and
Bonafede work carried out by us at NIE Mysuru, in partial
fulfilment of B.E. in Electronics and Communication
Engineering. We also declare that, to the best of our knowledge
and belief, the work reported here does not form part of any
thesis or dissertation of the basis of which a degree or award
was conferred on an earlier occasion by any student.
Ningaraddy Nuthan M N Santosh R Patgar Sathwik P M Siddesh N S
4NI21EC069 4Ni21EC073 4NI21EC094 4NI21EC095 4NI21EC104
Dept. of ECE Dept. of ECE Dept. of ECE Dept. of ECE Dept. of ECE
Mysuru-570008 Mysuru-570008 Mysuru-570008 Mysuru-570008 Mysuru-570008
absTracT
➢ The design and development of 32-bit Dynamic Random
Access Memory (DRAM) systems are critical components
in modern computing architectures. This abstract provides
an overview of the essential considerations and
methodologies involved in the creation of such DRAM
systems.
➢ The primary objective of 32-bit DRAM design is to ensure
efficient and reliable data storage and retrieval within a 32-
bit data bus architecture. To achieve this, several key
aspects are addressed during the design process
inTroDucTion
Dynamic random-access memory (DRAM) is a type of
semiconductor memory that is typically used for the data or program
code needed by a computer processor to function. DRAM is a common
type of random-access memory (RAM) that is used in personal
computers (PCs), workstations and servers. Random access allows the
PC processor to access any part of the memory directly rather than
having to proceed sequentially from a starting place. RAM is located
close to a computer's processor and enables faster access to data than
storage media such as hard disk drives and solid-state drives.
How Does DraM work
Memory is made of bits of data or program code that are arranged in a
two-dimensional grid. DRAM will store bits of data in what's called a
storage, or memory cell, consisting of a capacitor and a transistor. The
storage cells are typically organized in a rectangular configuration.
When a charge is sent through a column, the transistor at the column is
activated. A DRAM storage cell is dynamic, meaning that it needs to
be refreshed or given a new electronic charge every few milliseconds
to compensate for charge leaks from the capacitor.
The memory cells will work with other circuits that can be used to
identify rows and columns, track the refresh process, instruct a cell
whether or not to accept a charge and read or restore data from a cell.
DRAM is one option of semiconductor memory that a system designer
can use when building a computer. Alternative memory choices include
static RAM (SRAM), electrically erasable programmable read-only
memory (EEPROM), NOR flash and NAND flash. Many systems use
more than one type of memory.
Types of DraMs:
➢ Synchronous DRAM (SDRAM) syncs memory speeds with CPU
clock speeds, letting the memory controller know the CPU clock
cycle. This allows the CPU to perform more instructions at a time.
➢ Rambus DRAM (RDRAM) was more widely used in the early
2000s for graphics cards.
➢ Double Data Rate SDRAM (DDR SDRAM) almost doubles the
bandwidth in data rate of SDRAM by using double pinning. This
process allows for data to transfer on rising and falling edges of a
clock signal. It has been available in different iterations over time,
including DDR2 SDRAM, DDR3 SDRAM and DDR4 SDRAM.
➢ Fast Page Mode DRAM (FPM DRAM) gives higher performance
than other DRAM types through focusing on fast page access.
➢ Extended data out DRAM (EDO DRAM) improves the time to
read from memory on microprocessors, such as the Intel Pentium.
DesiGn of DraM anD iTs
workinG
This DIMM contains 1 GB of memory, but notice the “2Rx8” printed
on the sticker. The 2R means that this module is of rank 2, while the
x8 (pronounced “by eight”) denotes the output width of the data
coming from each DRAM chip. A rank is a separately addressable set
of DRAMs. In this case, one rank is a set of four DRAM chips. Since
there are eight total (front/back), we have 2 ranks.
The rank of a DRAM module is the highest level of organization
within a DIMM. Below that, each chip is organized into a number of
banks and memory arrays containing rows and columns. Figure 3
shows a DRAM chip with four banks.
As mentioned earlier, the rank of a DRAM is a set of separately
addressable DRAM chips. Each DRAM chip is further organized into
a number of banks that contain a set of memory arrays. The number of
memory arrays per bank is equal to the size of the output width.
Therefore, in a x4 DRAM chip, the internal banks would each have
four memory arrays. Figure 4 shows an example of a single x4 bank.
The Gray section is the memory array designed as a grid of rows and
columns. A set of decoders are used to access the rows and columns,
selecting a single intersection within the memory array. It is at this
intersection that a small capacitor stores a charge representing the data
being accessed.
Sense amplifiers perform precharge operations on capacitors and
generate logic-level outputs for a number of data buffers that store the
data until it can be retrieved by a memory controller or CPU.
VeriloG coDe anD TesT
bencH
module dram_32x32 (
input wire clk, // Clock input
input wire rst, // Reset input
input wire we, // Write enable
input wire [4:0] addr, // Address (Assuming 32 words)
input wire [31:0] din, // Input data for write
output reg [31:0] dout // Output data for read
);
// Step 1: Define memory array
reg [31:0] memory [31:0]; // 32x32-bit memory array
// Step 2: Write operation
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset memory on reset signal
memory <= 32'h00000000;
end else if (we) begin
// Write data to memory
memory[addr] <= din;
end
end
// Step 3: Read operation
always @(posedge clk or posedge rst) begin
if (rst) begin
dout <= 32'h00000000; // Reset output on reset signal
end else begin
// Read data from memory
dout <= memory[addr];
end
end
endmodule
TEST BENCH
module dram_32x32_tb;
// Inputs
reg clk;
reg rst;
reg we;
reg [4:0] addr;
reg [31:0] din;
// Outputs
wire [31:0] dout;
// Instantiate the dram_32x32 module
dram_32x32 uut (
.clk(clk),
.rst(rst),
.we(we),
.addr(addr),
.din(din),
.dout(dout)
);
// Clock generation
always begin
#5 clk = ~clk;
end
// Initial block
initial begin
// Initialize inputs
clk = 0;
rst = 1;
we = 0;
addr = 0;
din = 32'h00000000;
// Apply reset
#10 rst = 0;
// Test write operation
#5 we = 1;
#5 addr = 2;
#5 din = 32'hAABBCCDD;
// Test read operation
#5 we = 0;
#5 addr = 2;
// Add more test cases as needed
// End simulation
#10 $finish;
end
endmodule
This test bench includes a clock generation block, initializes inputs,
applies a reset, performs a write operation, and then a read operation.
You can add more test cases as needed for thorough testing of your
module. Adjust the delay values and inputs according to your specific
requirements.
DeTaileD explanaTion
of coDe
module dram_32x32 (
input wire clk, // Clock input
input wire rst, // Reset input
input wire we, // Write enable
input wire [4:0] addr, // Address (Assuming 32 words)
input wire [31:0] din, // Input data for write
output reg [31:0] dout // Output data for read
);
- clk: Clock input for synchronous operations.
- rst: Reset input to reset the memory.
- we: Write enable signal. When asserted, it indicates a write
operation.
- addr: Address bus for accessing memory locations. Assuming 32
words, so it uses 5 bits.
- din: Input data for write operations, assuming 32-bit data.
- dout: Output data for read operations, also assuming 32-bit data.
Define memory array
reg [31:0] memory [31:0];
This line declares a 32x32-bit memory array named memory. It's an
array of registers (reg), where each register is 32 bits wide. The
memory array provides storage for the data to be read and written.
Write operation
always @(posedge clk or posedge rst) begin
if (rst) begin
// Reset memory on reset signal
memory <= 32'h00000000;
end else if (we) begin
// Write data to memory
memory[addr] <= din;
end
end
This block describes the write operation. It is sensitive to the positive
edge of the clock (posedge clk) or the positive edge of the reset signal
(posedge rst). If the reset signal is asserted (rst), the memory is reset
to all zeros. If the write enable signal (we) is asserted and there is no
reset, the input data din is written to the memory location specified by
the address addr.
Read operation
always @(posedge clk or posedge rst) begin
if (rst) begin
dout <= 32'h00000000; // Reset output on reset signal
end else begin
// Read data from memory
dout <= memory[addr];
end
end
This block describes the read operation. Similar to the write
operation, it is sensitive to the positive edge of the clock or the
positive edge of the reset signal. If the reset signal is asserted, the
output dout is reset to all zeros. Otherwise, the data at the memory
location specified by the address addr is assigned to the output.
ouTpuT
1. Synthesis
2. Schematic
3. Physical Design
4. Clock Tree
conclusion anD references
we examined the basic principle of operation behind dynamic random
access memory, or DRAM. DRAM is extremely common in personal
computers and is a basic component that any computer needs to work
properly. DRAM works by using the presence or absence of charge on
a capacitor to store data.
Since a single DRAM cell is composed of only two components—a
transistor and a capacitor—DRAM can be made in high densities, and
it is inexpensive compared to other types of memory. We also looked
at a DIMM containing multiple DRAM chips and how those DRAM
chips are organized into arrays of memory cells.
References
https://www.techtarget.com/searchstorage/definition/DRAM
https://www.allaboutcircuits.com/technical-articles/introduction-to-
dram-dynamic-random-access-memory/
