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BUnee Institute of Technology, Tumakuru - 572 103
Course: BE TEST -Il ODD: 2023-24
Branch: (Common (EXO, BOT RST EXE) Sem: iil
SUB: Digital Electronics Circuits and Verilog
Time: 1% Hours ‘Max. Marks: 50
‘Marks | BL | COs | POs
4 | a) | Implement JK flip-flop using Nand gate lo Write the truth table, draw[ 8 [ 2 | 3 | 2.
timing diagram and derive its characteristic equation.
|] b) | Implement 3- bit PISO shift register using positive edge triggered D Flip lopand] 6 | 2 | 3 | 2
describe the operation for data 101
) | Develop a Verilog code for Toggle flip flop using behavioral modeling. 5 2] 3 2
2) a) | Design an Universal Shift Register for 4 bit operation of following) 8 3] 2
sequence
condition | operation
[00 | MEMORY
01 | Right Shift
10 | Left Shift
[PPO
b) | Analyze the given synchronous sequential machine and draw the state] 10 / 3 | 4 | 2
diagram.
J [ay | Design a mod-6 asynchronous up counter sequential circuit using T Hip-lop and | 8 Smale
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@ SradagengaInetue of Technology, BH Road, Tumkur - 872103, Kemataka Pay
