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Exp 1

1. The document describes an experiment to study logic gates and verify their truth tables. 2. It requires AND, OR, NOT, NAND, and NOR gates to build circuits and complete their truth tables. 3. The tasks are to write the truth table for a 3-input NAND gate and complete the truth table for a circuit diagram.

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Rubaiyat Jaky
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28 views2 pages

Exp 1

1. The document describes an experiment to study logic gates and verify their truth tables. 2. It requires AND, OR, NOT, NAND, and NOR gates to build circuits and complete their truth tables. 3. The tasks are to write the truth table for a 3-input NAND gate and complete the truth table for a circuit diagram.

Uploaded by

Rubaiyat Jaky
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Dept.

of EEE, CUET
EEE 366 - Digital Electronics Sessional

Experiment No.: 01
Experiment Name: Study of logic gates and verification of their truth tables

OBJECTIVES:
1. To study the basic logic functions AND, OR, INVERTER (NOT), NAND and NOR.
2. To study the representation of these functions by truth tables, logic diagrams and
Boolean algebra.

REQUIRED ICs:
1. 2 input AND gate (7408)
2. 2 input OR gate (7432)
3. NOT gate (7404)
4. 2 input NAND gate (7400)
5. 3 input NAND gate (7410)
6. 2 input NOR gate (7402)

EXPERIMENTAL PROCEDURE:
Make all circuit arrangements as given below and complete the truth tables. For each part of
the experiment apply the indicated voltage. Use LED to see the output change for different
input combinations.

OR Gate:

Truth table: OR gate


Pin 1 Pin 2 Pin 3
0 0
0 +5
+5 0
+5 +5

AND Gate:

Truth table: AND gate


Pin 1 Pin 2 Pin 3
0 0
0 +5
+5 0
+5 +5

Prepared by Muhammad Asad Rahman Page 1 of 41


Supervised by Dr. Quazi Delwar Hossain
Dept. of EEE, CUET
EEE 366 - Digital Electronics Sessional

NOT Gate:
Truth table: NOT gate
Pin 1 Pin 2
0
0
+5
+5

NOR Gate:

Truth table: NOR gate


Pin 2 Pin 3 Pin 1
0 0
0 +5
+5 0
+5 +5

NAND Gate:

Truth table: NAND gate


Pin 1 Pin 2 Pin 3
0 0
0 +5
+5 0
+5 +5

TASK:
1. Write the truth table for 3 input NAND gate.
2. Complete the truth table for the diagram of Fig. 1.

Prepared by Muhammad Asad Rahman Page 2 of 41


Supervised by Dr. Quazi Delwar Hossain

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