LOGIC II
Counters & Register
Lecture 2
Dr. Marwa Gamal Abd El-Azeem
Introduction to Chapter 7
•FFs and logic gates are combined to
form various counters and registers.
•Part 1 covers counter principles,
various counter circuits, and IC
counters.
•Part 2 covers several types of IC
registers and shift register counter
troubleshooting.
Introduction: Counters
Counters are circuits that cycle through a specified
number of states.
Two types of counters:
synchronous (parallel) counters
asynchronous (ripple) counters
Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.
Synchronous counters apply the same clock to all
flip-flops.
Asynchronous (Ripple) Counters
•Each FF output drives
the CLK input of the
next FF.
•This type of counter
arrangement is called
an asynchronous
counter
Asynchronous (Ripple) Counters
• Clock is applied only to FF A. J and K are high in all
FFs to toggle on every clock pulse.
•FF B must wait for FF A to change states before it
can toggle; FF C must wait for FF B, and so on.
• FF outputs D, C, B, and A are a 4 bit binary number
with D as the MSB and A as the LSB
• After the negative transition of the 15th clock pulse
the counter recycles to 0000
• This is an asynchronous counter because state is
not changed in exact synchronism with the clock.
EXAMPLE 1
How many clock pulses have occurred to read
0011 if the counter starts from 0000 state?
Solutions
19 clock pulses; the first 16 pulses bring the counter
back to 0000, and the last 3 bring it to 0011.
Also, 35 pulses (two complete cycles and then
three more),
or 51 pulses, and so on.
Four-Bit Asynchronous (Ripple) Counter
This counter has 16 distinctly different states (0000
through 1111). Thus, it is a MOD-16 ripple counter.
MOD number is equal to the number of states that the
counter goes through before recycling. Adding FFs will
increase the MOD number.
MOD number = 2N
N >>>is the number of FFs
Frequency division
Each FF will have an output frequency of ½ the
input.
The output frequency of the last FF of any
counter will be the clock frequency divided by the
MOD of the counter.
suppose that the clock signal in Figure 7-1 is 16
kHz. The waveform at output A is an 8-kHz
square wave, at output B it is 4 kHz, at output C it
is 2 kHz, and at output D it is1 kHz.
Propagation Delay in Ripple
Counters
The waveforms for a three-bit ripple counter
input pulse occurs every 1000 ns and each FF
has a propagation delay of 50 ns.
Clock 1:
Freq. = 1 MHz
Period = 1000 nsec.
Propagation Delay in Ripple
Counters
input pulse occurs every 100 ns and each FF
has a propagation delay of 50 ns.
Clock 2:
Freq. = 10 MHz
Period = 100 nsec.
Propagation Delay in Ripple
Counters
Ripple counters are simple, but the
cumulative propagation delay can cause
problems at high frequencies.
• For proper operation the following apply:
* Tclock ≥ N x tpd
* Fmax = 1 / (Nx tpd)
Synchronous (Parallel) Counters
• All FFs are triggered by
CLK simultaneously
• All of the FFs will change
states simultaneously;
•Each FF has J and K inputs connected so
they are HIGH only when the outputs of all
lower-order FFs are HIGH.
•The total propagation delay will be the same
for any number of FFs.
•Synchronous counters can operate at much
higher frequencies than asynchronous
counters.
Synchronous (Parallel) Counters
This total delay is the same no matter how many
FFs are in the counter, and it will generally be
much lower than with an asynchronous counter
with the same number of FFs.
total delay = FF tpd + AND gate tpd
Disadvantage :::
The circuitry of the synchronous counter is more
complex than that of the asynchronous counter.
Example
(a) Determine fmax for the counter of Figure 7-5(a) if tpd
for each FF is 50 ns and tpd for each AND gate is 20
ns. Compare this value with fmax for a MOD-16 ripple
counter.
(b) Determine fmax for the MOD-32 parallel counter.
Solution
a) Tclock ≥ 50+20=70 ns
Fmax =1/70 ns= 14.3 MHz (parallel counter)
Fmax = 1/(4*50) = 5 MHZ (ripple counter )
(b) ?????????????????
Counters with MOD Number < 2N
•Connect a NAND gate to the asynchronous CLEAR
inputs of all FFs.
• Determine which FFs are HIGH at the desired count and
connect the outputs of these FFs to the NAND gate inputs.
Counters with MOD Number < 2N
MOD-6 Counter
Displaying Counter States
one of the simplest methods using individual indicator
LEDs for each FF output. Each FF output is connected to
an INVERTER whose output provides the current path for
the LED.
For example, when output A is HIGH, the INVERTER
output goes LOW and the LED turns ON.
Counters with MOD Number < 2N
Decade counters / BCD counters
– A decade counter is any counter with 10
distinct states, regardless of the sequence. Any
MOD-10 counter is a decade counter.
– A BCD counter is a decade counter that counts
from binary 0000 to 1001.
• Decade counters are widely used for counting
events and displaying results in decimal form.
MOD-14 counter resets when Counts
from 0 to13
Clear asserted (activated) when1110 is
reached
MOD-10
(BCD + decade)
counter. Resets when count 1010 is
reached. Counts from 0 to 9
MOD-60 Counter
Resets when count 60 is reached
SYNCHRONOUS DOWN AND
UP/DOWN COUNTERS
UP
Counter
Down
Counter
SYNCHRONOUS UP/DOWN
COUNTERS
The counter counts up when the control input
Up/Down = 1
The counter counts down when
the control input Up/Down = 0.
Presettable COUNTERS
A presettable counter can be set to any
desired starting point either asynchronously or
synchronously.
The preset operation is also called parallel
loading the counter.
Presettable COUNTERS
1 1 0 1 1
1
0 1 0
1 0 1
1 0 1
0 1 0
0 1 1 1 1
Presettable COUNTERS
1 0 0 0 1
0
1 1 1
1 0 1
1 1 1
0 1 0
1 0 0 0 0
