AOZ1092D

EZBuck™ 3A Simple Buck Regulator

General Description Features

The AOZ1092D is a high efficiency, simple to use, 3A ● 4.5V to 16V operating input voltage range
buck regulator. The AOZ1092D works from a 4.5V to 16V ● 50mΩ internal PFET switch for high efficiency:
input voltage range, and provides up to 3A of up to 95%
continuous output current with an output voltage ● Schottky diode is included
adjustable down to 0.8V. ● Internal soft start
● Output voltage adjustable to 0.8V
The AOZ1092D comes in 4x5 DFN-8 packages and is
● 3A continuous output current
rated over a -40°C to +85°C ambient temperature range.
● Fixed 500kHz PWM operation
● Cycle-by-cycle current limit
● Short-circuit protection
● Output over voltage protection
● Thermal shutdown
● Small size 4x5 DFN-8 packages

Applications
● Point of load DC/DC conversion
● PCIe graphics cards
● Set top boxes
● DVD drives and HDD
● LCD panels
● Cable modems
● Telecom/networking/datacom equipment

Typical Application
VIN

C1
22µF
Ceramic

VIN
L1
4.7µH VOUT
EN 3.3V
U1 LX
AOZ1092D R1
COMP C2, C3
FB 22µF
Ceramic
RC
C5 R2
AGND GND
CC

Figure 1. 3.3V/3A Non-Synchronous Buck Regulator

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 AOZ1092D

Ordering Information
Part Number Ambient Temperature Range Package Environmental
AOZ1092DI -40°C to +85°C DFN-8 4x5 RoHS

All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration

VIN 1 8 LX
LX
PGND 2 7 LX

AGND 3 6 EN
GND
FB 4 5 COMP

4x5 DFN
(Top View)

Pin Description
Pin Number Pin Name Pin Function
1 VIN Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
2 PGND Power ground. Electrically needs to be connected to AGND.
3 AGND Reference connection for controller section. Also used as thermal connection for controller section.
Electrically needs to be connected to PGND.
4 FB The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
5 COMP External loop compensation pin.
6 EN The enable pin is active HIGH. Connect EN pin to VIN if not used. Do not leave the EN pin floating.
7, 8 LX PWM output connection to inductor. Thermal connection for output stage.

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 AOZ1092D

Block Diagram
VIN

EN UVLO 5V LDO Internal OTP

& POR Regulator +5V

+
ISen
–
Reference Softstart
& Bias Q1
ILimit

+
+ PWM Level
0.8V PWM Shifter
EAmp – Control
FB – Comp +
Logic
+ FET LX
Driver
D1
COMP

Frequency 500kHz/63kHz
Foldback Oscillator
Comparator
+
0.2V –

Over Voltage
Protection
+ Comparator
0.96V
–

AGND PGND

Absolute Maximum Ratings Recommend Operating Ratings

Exceeding the Absolute Maximum Ratings may damage the The device is not guaranteed to operate beyond the Maximum
device. Operating Ratings.
Parameter Rating Parameter Rating
Supply Voltage (VIN) 18V Supply Voltage (VIN) 4.5V to 16V
LX to AGND -0.7V to VIN+0.3V Output Voltage Range 0.8V to VIN
EN to AGND -0.3V to VIN+0.3V Ambient Temperature (TA) -40°C to +85°C
FB to AGND -0.3V to 6V
Package Thermal Resistance 53°C/W
COMP to AGND -0.3V to 6V DFN 4x5 (ΘJA)
PGND to AGND -0.3V to 0.3V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C

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 AOZ1092D

Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)

Symbol Parameter Conditions Min. Typ. Max. Units

VIN Supply Voltage 4.5 16 V
VUVLO Input Under-Voltage Lockout Threshold VIN Rising 4.00
V
VIN Falling 3.70
IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V 2 3 mA
IOFF Shutdown Supply Current VEN = 0V 1 10 µA
VFB Feedback Voltage 0.782 0.8 0.818 V
Load Regulation 0.5 %
Line Regulation 0.5 %
IFB Feedback Voltage Input Current 200 nA
ENABLE
VEN EN Input Threshold Off Threshold 0.6
V
On Threshold 2.0
VHYS EN Input Hysteresis 100 mV
MODULATOR
fO Frequency 400 500 600 kHz
DMAX Maximum Duty Cycle 100 %
DMIN Minimum Duty Cycle 6 %
GVEA Error Amplifier Voltage Gain 500 V/ V
GEA Error Amplifier Transconductance 200 µA / V
PROTECTION
ILIM Current Limit 4 5 A
VPR Output Over-Voltage Protection Threshold Off Threshold 960
mV
On Threshold 840
TJ Over-Temperature Shutdown Limit 150 °C
tSS Soft Start Interval 2.2 ms
OUTPUT STAGE
High-Side Switch On-Resistance VIN = 12V 40 50
mΩ
VIN = 5V 65 85
Note:
3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.

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 AOZ1092D

Typical Performance Characteristics

Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.

Light Load (DCM) Operation Full Load (CCM) Operation

Vin ripple Vin ripple

50mV/div 0.1V/div

Vo ripple Vo ripple
50mV/div 50mV/div

IL IL
2A/div 2A/div

VLX VLX
10V/div 10V/div

1μs/div 1μs/div

Startup to Full Load Full Load to Turn Off

Vin
5V/div Vin
5V/div

Vo
Vo
2V/div
1V/div

lin lin
1A/div 1A/div

400μs/div 1ms/div

50% to 100% Load Transient No Load to Turn Off

Vin
5V/div
Vo Ripple
0.1V/div
Vo
1V/div

lo
lin
2A/div
1A/div

100μs/div 1s/div

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 AOZ1092D

Typical Performance Characteristics (Continued)

Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.

Short Circuit Protection Short Circuit Recovery

Vo
Vo
2V/div
2V/div

IL IL
2A/div 2A/div

100μs/div 1ms/div

Efficiency

Efficiency (VIN = 12V) vs. Load Current

100

8.0V OUTPUT
95
5.0V OUTPUT
Efficieny (%)

90
3.3V OUTPUT
85

80

75
0 0.5 1.0 1.5 2.0 2.5 3.0
Load Current (A)

Thermal Derating Curves

Thermal derating curves for 4x5 DFN-8 package part under typical line and output voltage condition based on
EVAL board. Circuit of Figure 1. 25°C ambient temperature and natural convection (air speed <50LFM) unless
otherwise specified.
Derating Curve at 5V/6V Input Derating Curve at 12 Input
3.5 3.5

5.0V OUTPUT 8.0V OUTPUT

3.0 3.0
Output Current (IO)

Output Current (IO)

1.8V 1.8V OUTPUT

OUTPUT
2.5 2.5
3.3V
3.3V
OUTPUT 5.0V
OUTPUT
OUTPUT
2.0 2.0

1.5 1.5

1.0 1.0
25 35 45 55 65 75 85 25 35 45 55 65 75 85
Ambient Temperature (TA) Ambient Temperature (TA)

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 AOZ1092D

Detailed Description
The AOZ1092D is a current-mode step down regulator seen in a circuit which is using an NMOS switch. It allows
with integrated high side PMOS switch and low side 100% turn-on of the upper switch to achieve linear regu-
Schottky diode. It operates from a 4.5V to 16V input lation mode of operation. The minimum voltage drop from
voltage range and supplies up to 3A of load current. The VIN to VO is the load current times DC resistance of
duty cycle can be adjusted from 6% to 100% allowing a MOSFET plus DC resistance of buck inductor. It can be
wide range of output voltage. Features include enable calculated by equation below:
control, Power-On Reset, input under voltage lockout,
fixed internal soft-start and thermal shut down. V O_MAX = V IN – I O × ( R DS ( ON ) + R inductor )

The AOZ1092D is available in 4x5 DFN-8 package. where;

VO_MAX is the maximum output voltage,
Enable and Soft Start VIN is the input voltage from 4.5V to 16V,
The AOZ1092D has internal soft start feature to limit IO is the output current from 0A to 3A,
in-rush current and ensure the output voltage ramps up RDS(ON) is the on resistance of internal MOSFET, the value is
smoothly to regulation voltage. A soft start process between 40mΩ and 70mΩ depending on input voltage and
begins when the input voltage rises to 4.0V and voltage junction temperature, and
on EN pin is HIGH. In soft start process, the output Rinductor is the inductor DC resistance.
voltage is ramped to regulation voltage in typically 2.2ms.
The 2.2ms soft start time is set internally. Switching Frequency
The EN pin of the AOZ1092D is active high. Connect the The AOZ1092D switching frequency is fixed and set by
EN pin to VIN if enable function is not used. Pull it to an internal oscillator. The practical switching frequency
ground will disable the AOZ1092D. Do not leave it open. could range from 400kHz to 600kHz due to device
The voltage on EN pin must be above 2.0 V to enable the variation.
AOZ1092D. When voltage on EN pin falls below 0.6V,
the AOZ1092D is disabled. Output Voltage Programming
Output voltage can be set by feeding back the output to
Steady-State Operation
the FB pin with a resistor divider network. In the
Under steady-state conditions, the converter operates application circuit shown in Figure 1. The resistor divider
in fixed frequency and Continuous-Conduction Mode network includes R1 and R2. Usually, a design is started
(CCM). by picking a fixed R2 value and calculating the required
R1 with equation below.
The AOZ1092D integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying ⎛ R 1⎞
the voltage drop across the drain to source of the high V O = 0.8 × ⎜ 1 + -------⎟
⎝ R 2⎠
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the Some standard value of R1, R2 and most commonly used
internal transconductance error amplifier. The error output voltage values are listed in Table 1.
voltage, which shows on the COMP pin, is compared VO (V) R1 (kΩ) R2 (kΩ)
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at PWM 0.8 1.0 open
comparator input. If the current signal is less than the 1.2 4.99 10
error voltage, the internal high-side switch is on. The 1.5 10 11.5
inductor current flows from the input through the inductor 1.8 12.7 10.2
to the output. When the current signal exceeds the error 2.5 21.5 10
voltage, the high-side switch is off. The inductor current is 3.3 31.1 10
freewheeling through the internal Schottky diode to 5.0 52.3 10
output.
The combination of R1 and R2 should be large enough to
The AOZ1092D uses a P-Channel MOSFET as the high
avoid drawing excessive current from the output, which
side switch. It saves the bootstrap capacitor normally
will cause power loss.

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 AOZ1092D

Since the switch duty cycle can be as high as 100%, the Thermal Protection
maximum output voltage can be set as high as the input An internal temperature sensor monitors the junction
voltage minus the voltage drop on upper PMOS and temperature. It shuts down the internal control circuit and
inductor. high side PMOS if the junction temperature exceeds
150ºC.
Protection Features
The AOZ1092D has multiple protection features to Application Information
prevent system circuit damage under abnormal The basic AOZ1092D application circuit is shown in
conditions. Figure 1. Component selection is explained below.
Over Current Protection (OCP) Input Capacitor
The sensed inductor current signal is also used for over The input capacitor must be connected to the VIN pin and
current protection. Since AOZ1092D employs peak PGND pin of the AOZ1092D to maintain steady input
current mode control, the COMP pin voltage is voltage and filter out the pulsing input current. The
proportional to the peak inductor current. The COMP pin voltage rating of input capacitor must be greater than
voltage is limited to be between 0.4V and 2.5V internally. maximum input voltage plus ripple voltage.
The peak inductor current is automatically limited cycle
by cycle. The input ripple voltage can be approximated by
equation below:
The cycle by cycle current limit threshold is set between
IO ⎛ VO ⎞ VO
4A and 5A. When the load current reaches the current ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × ---------
limit threshold, the cycle by cycle current limit circuit turns f × C IN ⎝ V IN⎠ V IN
off the high side switch immediately to terminate the
current duty cycle. The inductor current stop rising. The Since the input current is discontinuous in a buck
cycle by cycle current limit protection directly limits converter, the current stress on the input capacitor is
inductor peak current. The average inductor current is another concern when selecting the capacitor. For a buck
also limited due to the limitation on peak inductor current. circuit, the RMS value of input capacitor current can be
When cycle by cycle current limit circuit is triggered, the calculated by:
output voltage drops as the duty cycle decreasing.
VO ⎛ VO ⎞
The AOZ1092D has internal short circuit protection to I CIN_RMS = I O × --------
- ⎜ 1 – --------
-⎟
protect itself from catastrophic failure under output short V IN ⎝ V IN⎠
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever FB pin voltage is below if let m equal the conversion ratio:
0.2V, the short circuit protection circuit is triggered. As a
result, the converter is shut down and hiccups at a VO
--------
- = m
frequency equals to 1/8 of normal switching frequency. V IN
The converter will start up via a soft start once the short
circuit condition disappears. In short circuit protection The relationship between the input capacitor RMS
mode, the inductor average current is greatly reduced current and voltage conversion ratio is calculated and
because of the low hiccup frequency. shown in Figure 2 below. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
Power-On Reset (POR) worst current stress on CIN is 0.5 x IO.
A power-on reset circuit monitors the input voltage.
0.5
When the input voltage exceeds 4V, the converter starts
operation. When input voltage falls below 3.7V, the 0.4
converter will be shut down.
ICIN_RMS(m) 0.3
Output Over Voltage Protection (OVP) IO
0.2
The AOZ1092D monitors the feedback voltage: when the
feedback voltage is higher than 960mV, it immediate 0.1
turns-off the PMOS to protect the output voltage
overshoot at fault condition. When feedback voltage is 0
0 0.5 1
lower than 840mV, the PMOS is allowed to turn on in the m
next cycle.
Figure 2. ICIN vs. Voltage Conversion Ratio

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 AOZ1092D

For reliable operation and best performance, the input Table 2.

capacitors must have current rating higher than ICIN_RMS
VOUT L1 Manufacturer
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR 5.0V Shielded, 6.8µH Coilcraft
and high ripple current rating. Depending on the MSS1278-682MLD
application circuits, other low ESR tantalum capacitor or Shielded, 6.8µH
aluminum electrolytic capacitor may also be used. When MSS1260-682MLD
selecting ceramic capacitors, X5R or X7R type dielectric
3.3V Un-shielded, 4.7µH Coilcraft
ceramic capacitors are preferred for their better
DO3316P-472MLD
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures are Shielded, 4.7µH
DO1260-472NXD
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement. Shielded, 3.3µH ELYTONE
ET553-3R3
Inductor 1.8V Shielded, 2.2µH ELYTONE
The inductor is used to supply constant current to output ET553-2R2
when it is driven by a switching voltage. For given input Un-shielded, 3.3µH Coilcraft
and output voltage, inductance and switching frequency DO3316P-222MLD
together decide the inductor ripple current, which is: Shielded, 2.2µH
VO ⎛ MSS1260-222NXD
VO ⎞
ΔI L = ----------- × ⎜ 1 – --------
-⎟
f×L ⎝ V IN⎠ Output Capacitor
The output capacitor is selected based on the DC output
The peak inductor current is: voltage rating, output ripple voltage specification and
ripple current rating.
ΔI L
I Lpeak = I O + -------- The selected output capacitor must have a higher rated
2
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
High inductance gives low inductor ripple current but
considered for long term reliability.
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also Output ripple voltage specification is another important
reduces RMS current through inductor and switches, factor for selecting the output capacitor. In a buck con-
which results in less conduction loss. verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
When selecting the inductor, make sure it is able to
value and ESR. It can be calculated by the equation
handle the peak current without saturation even at the
below:
highest operating temperature.
1
ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
The inductor takes the highest current in a buck circuit. ⎝ 8×f×C ⎠
The conduction loss on inductor needs to be checked for O
thermal and efficiency requirements. where,
CO is output capacitor value, and
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded ESRCO is the equivalent series resistance of the output
inductors are small and radiate less EMI noise. But they capacitor.
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size. When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
Table 2 lists some inductors for typical output voltage frequency dominates. Output ripple is mainly caused by
design. capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
ΔV O = ΔI L × ⎛ -------------------------⎞
⎝8 × f × C ⎠
O

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 AOZ1092D

If the impedance of ESR at switching frequency The compensation design is actually to shape the
dominates, the output ripple voltage is mainly decided by converter close loop transfer function to get desired gain
capacitor ESR and inductor ripple current. The output and phase. Several different types of compensation
ripple voltage calculation can be further simplified to: network can be used for the AOZ1092D. For most cases,
a series capacitor and resistor network connected to the
ΔV O = ΔI L × ESR CO COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type In the AOZ1092D, FB pin and COMP pin are the invert-
of ceramic, or other low ESR tantalum capacitor or ing input and the output of internal transconductance
aluminum electrolytic capacitor may also be used as error amplifier. A series R and C compensation network
output capacitors. connected to COMP provides one pole and one zero.
The pole is:
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is G EA
decided by the peak to peak inductor ripple current. It can f p2 = -------------------------------------------
2π × C C × G VEA
be calculated by:
ΔI L where;
I CO_RMS = ---------- GEA is the error amplifier transconductance, which is 200 x 10-6
12 A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When CC is cthe compensation capacitor.
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be The zero given by the external compensation network,
overstressed. capacitor CC and resistor RC, is located at:

Loop Compensation 1
f Z2 = -----------------------------------
The AOZ1092D employs peak current mode control for 2π × C C × R C
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output To design the compensation circuit, a target crossover
L&C filter. It greatly simplifies the compensation loop frequency fC for close loop must be selected. The system
design. crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
With peak current mode control, the buck power stage bandwidth. Generally a higher bandwidth means faster
can be simplified to be a one-pole and one-zero system response to load transient. However, the bandwidth
in frequency domain. The pole is dominant pole and can should not be too high because of system stability
be calculated by: concern. When designing the compensation loop,
converter stability under all line and load condition must
1
f p1 = ----------------------------------- be considered.
2π × C O × R L
Usually, it is recommended to set the bandwidth to be
The zero is a ESR zero due to output capacitor and its less than 1/10 of switching frequency. The AOZ1092D
ESR. It is can be calculated by: operates at a fixed switching frequency range from
400kHz to 600kHz. It is recommended to choose a
1 crossover frequency less than 50kHz.
f Z1 = ------------------------------------------------
2π × C O × ESR CO f C = 50kHz

where; The strategy for choosing RC and CC is to set the

CO is the output filter capacitor, cross over frequency with RC and set the compensator
RL is load resistor value, and zero with CC. Using selected crossover frequency, fC,
to calculate RC:
ESRCO is the equivalent series resistance of output capacitor.
VO 2π × C O
R C = f C × ---------- × ------------------------------
V G ×G
FB EA CS

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 AOZ1092D

where; The actual junction temperature can be calculated with

where fC is desired crossover frequency, power dissipation in the AOZ1092D and thermal
VFB is 0.8V, impedance from junction to ambient.
GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, and T junction = ( P total_loss – P inductor_loss ) × Θ JA + T
GCS is the current sense circuit transconductance, which is 6.86 A/V amb

The maximum junction temperature of AOZ1092D is

The compensation capacitor CC and resistor RC together 150ºC, which limits the maximum load current capability.
make a zero. This zero is put somewhere close to the Please see the thermal de-rating curves for maximum
dominate pole fp1 but lower than 1/5 of selected cross- load current of the AOZ1092D under different ambient
over frequency. CC can is selected by: temperature.
1.5
C C = ----------------------------------- The thermal performance of the AOZ1092D is strongly
2π × R C × f p1 affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
The above equation can be simplified to: operate under the recommended environmental
CO × RL conditions.
C C = ---------------------
R3 Several layout tips are listed below for the best electric
and thermal performance. Figure 3 on the next page
An easy-to-use application software which helps to illustrates a PCB layout example as reference.
design and simulate the compensation loop can be found
at www.aosmd.com. 1. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized copper area to
Thermal Management and Layout the PGND pin and the VIN pin to help thermal
Consideration dissipation.
In the AOZ1092D buck regulator circuit, high pulsing 2. Input capacitor should be connected to the VIN pin
current flows through two circuit loops. The first loop and the PGND pin as close as possible.
starts from the input capacitors, to the VIN pin, to the 3. A ground plane is preferred. If a ground plane is not
LX pins, to the filter inductor, to the output capacitor and used, separate PGND from AGND and connect them
load, and then return to the input capacitor through only at one point to avoid the PGND pin noise
ground. Current flows in the first loop when the high side coupling to the AGND pin.
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the anode of Schottky 4. Make the current trace from LX pins to L to Co to the
diode, to the cathode of Schottky diode. Current flows in PGND as short as possible.
the second loop when the low side diode is on. 5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground 6. The two LX pins are connected to internal PFET
plane is strongly recommended to connect input drain. They are low resistance thermal conduction
capacitor, output capacitor, and PGND pin of the path and most noisy switching node. Connected a
AOZ1092D. copper plane to LX pin to help thermal dissipation.
This copper plane should not be too larger otherwise
In the AOZ1092D buck regulator circuit, the major power switching noise may be coupled to other part of
dissipating components are the AOZ1092D and output circuit.
inductor. The total power dissipation of converter circuit 7. Keep sensitive signal trace far away form the LX
can be measured by input power minus output power. pins.
P total_loss = V IN × I IN – V O × I O

The power dissipation of inductor can be approximately

calculated by output current and DCR of the inductor.

P inductor_loss = IO2 × R inductor × 1.1

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 AOZ1092D

Thermal PAD: LX

Vin Vo

L
Vin LX

Cin
PG LX
Cout
AG EN

FB CP

GND

Thermal PAD: AGND Via to ground plane

Figure 3. AOZ1092D PCB Layout

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 AOZ1092D

Package Dimensions, DFN 4x5

D A Pin #1 IDA
e
D/2 B 1
L
E/2
R
E E3
aaa C

E2

Index Area
(D/2 x E/2)

aaa C D2 D3 L1

ccc C A3
Seating C
Plane
A

ddd C A1
b
bbb CAB

Dimensions in millimeters Dimensions in inches

Symbols Min. Nom. Max. Symbols Min. Nom. Max.
A 0.80 0.90 1.00 A 0.031 0.035 0.039
Recommended Land Pattern A1 0.00 0.02 0.05 A1 0.000 0.001 0.002
2.125 1.775 A3 0.20 REF A3 0.008 REF
b 0.35 0.40 0.45 b 0.014 0.016 0.018
0.6
D 5.00 BSC D 0.197 BSC
D2 1.975 2.125 2.225 D2 0.078 0.084 0.088
2.7 D3 1.625 1.775 1.875 D3 0.064 0.070 0.074
2.2
E 4.00 BSC E 0.157 BSC
E2 2.500 2.650 2.750 E2 0.098 0.104 0.108
E3 2.050 2.200 2.300 E3 0.081 0.087 0.091
e 0.95 BSC e 0.037 BSC
0.8
0.5 0.95 L 0.600 0.700 0.800 L 0.024 0.028 0.031
Unit: mm L1 0.400 0.500 0.600 L1 0.016 0.020 0.024
R 0.30 REF R 0.012 REF
aaa – 0.15 – aaa – 0.006 –
bbb – 0.10 – bbb – 0.004 –
ccc – 0.10 – ccc – 0.004 –
ddd – 0.08 – ddd – 0.003 –

Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.

Rev. 1.3 February 2009 www.aosmd.com Page 13 of 16

 AOZ1092D

Tape Dimensions, DFN 4x5

Tape

R0
.40

0.
T

20
D1

E1

E2 D0
E
B0
Feeding
Direction

K0 P0 A0
Unit: mm

Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T
DFN 5x4 5.30 4.30 1.20 1.50 1.50 12.00 1.75 5.50 8.00 4.00 2.00 0.30
(12 mm) ±0.10 ±0.10 ±0.10 Min. +0.10 / –0 ±0.30 ±0.10 ±0.10 ±0.10 ±0.20 ±0.10 ±0.05
Typ.

Leader/Trailer and Orientation

Trailer Tape Components Tape Leader Tape

(300mm Min.) Orientation in Pocket (500mm Min.)

Rev. 1.3 February 2009 www.aosmd.com Page 14 of 16

 AOZ1092D

Reel Dimensions, DFN 4x5

59
R1
II I

R1 6.0±1
M 21
R1 I
27
Zoom In
R1

R6
P

R5
B

5
W1
III
Zoom In
3-1.8
0.05

II
Zoom In

A
/8"

3-
ø2
"
3-ø1

/4

.9
ø1

±0 N=ø100±2
A A
3-

.0
5
0.2
6±
ø9

1.8
6.0

6.45±0.05
1.8

0.00
6.2 8.00 -0.05
R1

ø2 2.20
8.9±0.1
1. ø9 0.00 2.00
20
14 REF
5.0
0
ø17.0 ø13.0
C
R1.10
1.8
R3.10
11.90 12 REF
ø86 46.0±0.1
.0±0 R0.5
.1
10°
44.5±0.1
41.5 REF
43.00 3.3
44.5±0.1
.95

6.50 4.0
R3

6.10 38°

40°
10.0
EF

VIEW: C 2.5
8R

A 0.80
R4

3- 3.00 1.80
ø3 8.0±0.1
"
16

2.00 /1 +0.05
/

6"
ø3

8.000.00
3-

6.50
10.71

6°

Rev. 1.3 February 2009 www.aosmd.com Page 15 of 16

 AOZ1092D

Package Marking

Z1092DI
Part Number Code
FAYWLT

Fab & Assembly Location Assembly Lot Code

Year & Week Code

This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

As used herein:

1. Life support devices or systems are devices or 2. A critical component in any component of a life
systems which, (a) are intended for surgical implant into support, device, or system whose failure to perform can
the body or (b) support or sustain life, and (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in a significant injury of
the user.

Rev. 1.3 February 2009 www.aosmd.com Page 16 of 16