Introduction to Silicon Process and VLSI

Manufacturing Process

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

 Previous Lectures
• Moore’s Law.
• Semiconductors - Devices.
• The MOSFET Transistor.
• CMOS Inverter.

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Agenda
• Manufacturing CMOS ICs:
• Background.
• Materials Used in IC Manufacturing.
• Manufacturing Processes.
• CMOS Fabrication process.

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 IC Design Flow
• IC design flow is the process of developing an IC design to the
point at which the IC can be manufactured in a semiconductor
fabrication plant (i.e., a foundry).

• To manufacture a circuit design, a designer must convert his

circuit design (circuit symbols) into a layout. Then, This layout is
sent to the foundry to be manufactured.

• Layouts can be stored in different file formats. The most common

one is called Graphic Database System Information Interchange
(GDSII).

• A layout includes the physical arrangement and wiring of

components on a semiconductor chip. It involves determining
the exact locations, sizes, and shapes of transistors, resistors,
capacitors, and as well as their interconnections.
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 Electronic Design Automation Tools (EDA) Market Top Players

• Siemens EDA (Mentor

Graphics)
• Synopsys Inc.
• Cadence Design Systems
Inc.
• ANSYS Inc.
• Keysight Technologies Inc.
• Xilinx Inc.

https://eda.sw.siemens.com/en-US/

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 IC Manufacturing
Manufacturing (Fabrication) is the process of constructing an industrial product, Or it
can be defined as a set of methods that are performed to manufacture an electronic
device or product.

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 IC Manufacturing
• IC Manufacturing is like creating a building
• Different layers are put on each others
• Layers are deposited (added) then parts are etched
(removed) and
modified to get the 3-D shapes that eventually build up the
transistors and their connections

What made IC fabrication

very successful is the ability
to process millions of
transistors in parallel.

https://www.asml.com/en/news/stories/2021/semiconduct
or-manufacturing-process-steps
https://www.gep.com/blog/mind/outlook-for-the-global-
semiconductor-silicon-wafer-industry CND121: INTRODUCTION TO SILICON PROCESS & VLSI
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 IC Manufacturing: Clean Rooms
• The fabrication process is performed in highly specialized semiconductor fabrication
plants, also called foundries or "fabs“, with a central part being called “Clean Room
• Main function of clean rooms is control of particle Contamination.
• Requires control of air flow, water and chemical filtrations, human protocol. For
example, Air flows through 0.3 microns filters.

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Semiconductor Fabrication Plant

• A semiconductor fabrication plant is where

integrated circuits (ICs), also known as microchips,
are manufactured.
• Integrated Device Manufacturers (IDMs) who design and
manufacture ICs in-house and may also manufacture designs
from design-only (fabless firms)
• Pure foundries who manufacture designs from fabless
companies and do not design their own ICs.

• Taiwan Semiconductor Manufacturing Company

(TSMC) offer IC design services
• Samsung, design and manufacture ICs for
customers, while also designing, manufacturing and
selling their own ICs. ASML is one of the world's leading
• “Fab” is where semiconductors are born. Fab is manufacturers of chip-making equipment design
short for “fabrication”, which means to produce, and manufacture the lithography machines that
and refers to semiconductor production facilities in are an essential component in chip
the semiconductor industry. manufacturing.

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 Semiconductor Fabrication Plant
In 2022, TSMC led the foundry to start
3nm FinFET (N3) technology high volume
production. TSMC's 3nm process is the
industry's most advanced semiconductor
technology offering best power,
performance, and area (PPA), and is a
full-node advance from its 5nm
generation.

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 Market share in Semiconductor Manufacturing Industry

• As of 2021, only three firms are able to manufacture the most advanced
semiconductors:
TSMC has 28% of the market share in matured nodes
• TSMC (Taiwan)
(40nm and below), making it the world leader in the
• Samsung (South Korea) global semiconductor manufacturing market.
• Intel (United States) UMC, SMIC and Samsung take second, third and fourth
place with market shares of 13%, 11% and 10%,
respectively.
In 2022, Intel's market share of the global
semiconductor market was 9.7 percent.

International Data Corporation (IDC)

Taiwan Semiconductor Manufacturing Company (TSMC)
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 Materials Used in IC Manufacturing
IC manufacturing materials can be categorized into three main groups according to their
electrical conduction properties:
• Conductors:
• Mainly used for electrical Connectivity (e.g., connect the different devices to each other).
• Examples: Copper, Aluminum, Platinum, Silver, and Gold.
• Insulators:
• They are mainly used to isolate conducting and semiconducting materials.
• Semiconductors:
• They are mainly used in substrate and device creation.
• Examples: Silicon and GaAs.

Note: some devices rely on the three materials for

their physical operation.

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 Materials Used in IC Manufacturing

An example showing metal connections inside a chip. An example showing metal connections
inside a chip (cross-section).

Semiconductors are made from a variety of raw materials, including silicon, germanium, gallium arsenide,
and indium phosphide. These materials are processed and purified to create a crystalline structure,
which forms the foundation for building semiconductor devices such as transistors, diodes, and integrated
circuits.

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 Fabrication Steps
• Wafer Manufacture.
• Wafer Processing.
• Oxide Growth and Removal.
• Lithography.
• Etching.
• Deposition and Ion
Implantation.
• Metallization.
• Testing (e.g., EDS)
• Assembly and packaging
https://www.electronicsandyou.com/blog/semiconductor-manufacturing-process-steps-and-
technology-used.html

EDS: Energy Dispersive Spectroscopy

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 Fabrication technologies
• The fabrication steps may involve many IC fabrication technologies, such as
Complementary Metal-Oxide-Semiconductor (CMOS), Silicon-on-Insulator,
Gallium Nitride (GaN), Bipolar CMOS (BiCMOS) , etc.
• Each of them is used for specific applications.
• CMOS is one of the most common fabrication process.

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 CMOS Process
• The CMOS process allows fabrication of NMOS and PMOS transistors side-by-
side on the same Silicon substrate (e.g., inverter)

substrate

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 CMOS Inverter different views

Inverter (circuit design)

https://www.vlsi-expert.com/2014/11/cmos-layout-design.html
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 CMOS Process at a Glance
Define active areas
p+ n+ n+ p+ p+ n+ Etch and fill trenches
n well
p substrate

Implant well regions

• Built (roughly) from the bottom up Deposit and pattern

polysilicon layer
1. metal 2
2. metal 1 Implant source and drain
3. polysilicon regions and substrate contacts

4. source and drain diffusions

Create contact and via windows
5. tubs (aka wells, active Deposit and pattern metal layers
areas)
• One full photolithography sequence per layer (mask)
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 Fabrication Steps – CMOS Inverter
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

• Start with blank p-type wafer

• Build inverter from the bottom up
• First step will be to form the n-well

p substrate

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 Oxidation
• Grow SiO2 on top of Si wafer
• 900 – 1200 C with H2O or O2 in oxidation
furnace

SiO2

p substrate

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 Photoresist
• Spin on photoresist
• Photoresist is a light-sensitive organic
polymer

Photoresist
SiO2

p substrate

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 Lithography
• Expose photoresist through n-well mask
• Strip off photoresist defined by n-well
mask

Photoresist
SiO2

p substrate

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 Etch
• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!

• Only attacks oxide where resist has been

exposed

Photoresist
SiO2

p substrate

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 Strip Photoresist
• Strip off remaining photoresist
• Use mixture of acids called piranah etch

• Necessary so resist doesn’t melt in next

step

SiO2

p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 n-well
• n-well is formed with diffusion or ion
implantation
• Diffusion
• Place wafer in furnace with arsenic (As) gas
• Heat until As atoms diffuse into exposed Si

• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si

SiO2

n well

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 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps
A
GND SiO2
V DD
Y
n+ diffusion

p+ diffusion
p+ n+ n+ p+ p+ n+
polysilicon
n well
p substrate
metal1
well
substrate tap
tap

n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Polysilicon
• Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)

• Chemical Vapor Deposition (CVD) of silicon layer

• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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 Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact
A
GND SiO2
V DD
Y
n+ diffusion

p+ diffusion
p+ n+ n+ p+ p+ n+
polysilicon
n well
p substrate
metal1
well
substrate tap
tap

n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

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 N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+
n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 N-diffusion cont.
Strip off oxide to complete patterning step

A
GND SiO2
V DD
Y
n+ diffusion

p+ diffusion
p+ n+ n+ p+ p+ n+
polysilicon
n well
p substrate
metal1
well
substrate tap
tap

n+ n+ n+
n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS
source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 Detailed Mask Views A

• Six masks Y

GND VDD

• n-well substrate tap

nMOS transistor pMOS transistor
well tap

• Polysilicon
• n+ n well

diffusion
• p+
diffusion Polysilicon

• Contact
• Metal n+ Diffusion

p+ Diffusion
SiO2

n+ diffusion Contact

p+ diffusion

polysilicon
Metal
metal1

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 Overview on IC fabrication

Samsung Videos: https://www.youtube.com/watch?v=Bu52CE55BN0

CND121: INTRODUCTION TO SILICON PROCESS & VLSI
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 Next
• Detailed information on each step

CND121: INTRODUCTION TO SILICON PROCESS & VLSI

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 IC Fabrication: Wafer Manufacturing
Wafer Manufacturing Steps:
1. Silicon is extracted from Silica sand, also known as quartz sand, white sand, or
industrial sand.
2. Sand has high percentages of silicon in the form of silicon dioxide (SiO2).
3. Sand is heated until it melts into a high purity liquid and then gets solidified by
crystallization.
4. The resultant silicon rod is called an ingot.

sand melting ingot

Wafer Deposition and Ion
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 IC Fabrication: Wafer Manufacturing
5. The ingots are sliced into a disc thinly sliced wafers.
6. The surface of sliced wafers is rough and contains defects. Therefore, polishing
machines are used to polish the surface of the wafer. The reason is that defects on the
surface could negatively affect the yield.
7. Eventually, the wafer is cleaned in a combination of chemical paths that remove any
impurities from the surface.

sand melting ingot slicing Wafer

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 IC Fabrication: Oxide Growth
• Oxides (e.g., SiO2)are insulators that are used in either isolating conducting materials from each
other, such as devices and metals) or creating certain devices.
• Growth of SiO2 using oxygen and water vapor is referred to as dry and wet oxidation,
respectively.
• Dry oxidation is used to form thin oxide films.
• Wet oxidation proceeds at a faster rate and is used in forming thicker oxides.
• SiO2 is deposited on materials other than silicon through reaction between gaseous silicon
compounds and oxidizers (Insulation between different layers of metallization)

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 IC Fabrication: photolithography
photolithography is the process of transferring patterns of geometric shapes in a mask to a
thin layer of radiation-sensitive material (called resist) covering the surface of a
semiconductor wafer.

High level Steps:

Designer:
• Drawing “layer” patterns on a layout editor. Then, send a layout (e.g., GDSII) to the
corresponding foundry.
Foundry:
• Masks generation from the layer patterns in the design data base.
• Printing: transfer the mask pattern to the wafer surface.
• Process the wafer to physically pattern each layer of the IC.

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 IC Fabrication: photolithography
Deposit a photoresist:
• the surface to be patterned is spin-coated with a light-
sensitive organic polymer called photoresist
Printing (exposure):
• The mask pattern is developed on the photoresist, with
UV light exposure.
• Depending on the type of photoresist(negative or
positive), the exposed or unexposed parts become
resistant to certain types of solvents.
Development:
• The developed photoresist acts as a mask for patterning
of underlying layers and then is removed.
• The soluble photoresist is chemically removed.

Wafer CND121: INTRODUCTION Deposition and Ion 43

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 IC Fabrication: photolithography

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 IC Fabrication: photolithography
There are two types of a photoresist:
1. Positive resist:
The resist is exposed with UV light where the underlying material is to be removed. In these resists, exposure
to the UV light changes the chemical structure of the resist so that it becomes more soluble in the developer.
2. Negative resist:
The resist is exposed with UV light where the underlying material is to be kept. In these resists, exposure
to the UV light changes the chemical structure of the resist so that it becomes more solid in the developer.

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 IC Fabrication: Etching
Once the desired shape is patterned with photoresist, the etching process allows
unprotected materials to be removed:
• Wet etching: uses chemicals.
• Dry etching: uses ionized gases
(plasma, reactive-ion etching or RIE)

Isotropic etching (i.e., Wet etching)

Anisotropic etching (i.e., Dry etching)

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 IC Fabrication: Diffusion and Ion Implantation
Doping materials are added to change the electrical characteristics of silicon locally
through:
• Diffusion: dopants deposited on silicon move through the lattice by thermal diffusion
(high temperature process), such as Wells.
• Ion implantation: highly energized donor or acceptor atoms impinge on the surface and
travel below it (e.g., source and drain).
• The patterned SiO2 serves as an implantation mask.

• After ion implantation, annealing operation is

required: Heating up the wafer to fix covalent
bonds. Done after every ion implantation or a
similar damaging step.

Diffusion Ion implantation

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 IC Fabrication: Silicon Deposition and Metallization
• Films of silicon can be added on the surface of a wafer
• Epitaxy: growth of a single-crystal semiconductor film on a crystalline substate
• Polysilicon: polycrystalline film with a granular structure obtained through
deposition of silicon on an amorphous material (Chemical vapor deposition-CVD)

• Metallization: deposition of metal layers by evaporation (e.g., interconnections ), uses

physical vapor deposition (PVD)

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