VLSI Tutorials
On-chip Clock Controller
On-chip Clock Controllers (OCC) are also known as Scan Clock Controllers (SCC). OCC is the logic inserted on the SOC
for controlling clocks during silicon testing on ATE (Automatic test Equipment). Since at-speed testing requires two
clock pulses in capture mode with a frequency equal to the functional clock frequency, without OCC we need to
provide these at-speed pulses through I/O pads. But these pads has limitation in terms of maximum frequency they
can support; OCC on other hand uses internal PLL clock for generating clock pulses for test. During stuck-at testing,
the OCC ensures only one clock pulse is generated in the capture phase. Similarly, during at-speed testing, the OCC
ensures two clock pulses are generated in the capture phase, having a frequency equal to frequency of the functional
clock.
Therefore all the test clocks in a scan friendly design is routed through an OCC, which controls the clock operation in
scan mode (both in stuck-at and at-speed testing) and bypasses the functional clock in functional mode. You can
check here, how the clocking architecture is modified with OCCs to support scan.
In this article we will be discussing about a very basic OCC design with the sole purpose of demonstrating how it
work. However industry standard OCCs are much more advanced and robust to clock glitches than the OCC discussed
here.
Figure 1: Schematic of a basic On-chip Clock Controller structure (having a n-bit shift register)
When the circuit is in functional mode (Test Mode = 0), the OCC bypasses the functional clock (Refer Figure 1). But
during the shift phase (Shift Enable = 1), the Scan Clock is propagated at the output of OCC. In capture phase (Shift
Enable = 0), the shift register starts shifting ‘1’ and enables the Clock Gate, to allow single pulse or double pulse,
depending on the type of testing. The OCC generates one clock pulse in stuck-at testing (At-speed Mode = 0) and
two clock pulses in at-speed testing (At-speed Mode = 1).
The behavior of this OCC (having a 5-bit shift register) in at-speed testing is shown in Figure 2. The two capture
pulses came after 5 positive edges of the functional clock (as we are using a 5-bit shift register).
NOTE: Once the Shift Enable is asserted Low, the n-bit shift register decides the delay in terms of the number of positive edges of the
functional clock, after which the functional clock is propagated at the output of the OCC.
Figure 2: Simulation waveform of the OCC structure shown in Figure 1 (having a 5-bit shift register)
Systemverilog code of the OCC:
module occ
#(
parameter SHIFT_REG_BITS = 5
)
(
input logic test_mode,
input logic atspeed_mode,
input logic shift_en,
input logic scan_clk,
input logic func_clk,
output logic occ_out_clk
)
logic cg_en;
logic cg_out_clk;
logic sync_flop;
logic [SHIFT_REG_BITS-1:0]shift_reg;
always @(func_clk or cg_en) begin
if (cg_en == 1)
cg_out_clk = func_clk;
else
cg_out_clk = 0;
end
always_ff @(posedge scan_clk) begin
sync_flop <= ~shift_en;
end
always_ff @(posedge func_clk) begin
shift_reg <= shift_reg << 1;
shift_reg[0] <= sync_flop;
end
assign occ_out_clk = test_mode ? (shift_en ? scan_clk : cg_out_clk) : func_clk;
assign cg_en = atspeed_mode ? (~shift_reg[SHIFT_REG_BITS-1] & shift_reg[SHIFT_REG_BITS-3]) :
(~shift_reg[SHIFT_REG_BITS-1] & shift_reg[SHIFT_REG_BITS-2]);
endmodule
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