Digital Logic Design Labs Fall 2021
Session
Labs
No. Topics
To implement and verify NOT, AND & OR gate
01 1 operations using, 74LS04 IC, 74LS08 IC, 74LS32 IC & LAB TASK1
Module KL-33001 and ELVIS II
To implement and verify NAND & NOR gate operations
2 02 LAB TASK2
using, 74LS00 IC, 74LS02 IC, Module KL-33001 & ELVIS
To implement and verify X-OR & X-NOR gate operations
3 03 LAB TASK3
using 74LS86 IC, ,Module KL-33001 & ELVIS
To implement and verify Half and Full Adder operations
4 04 using,74LS283 IC, Analysis of 74LS283 IC as a 4-bit LAB TASK4
Adder, Module KL-33001 & ELVIS
5-6 FIRST MID TERM PRACTICAL EXAMS
To implement and verify Comparator operations using
7 05 LAB TASK5
74LS85 IC & Module KL-33001 & ELVIS
To implement and verify Multiplexer operations using IC
8 06 LAB TASK6
74151 &Module KL-33001 & ELVIS
To implement and verify Decoder operations using
9 07 LAB TASK7
74LS42 IC& Module KL-33001 & ELVIS
10-11 SECOND MID TERM PRACTICAL EXAMS
To implement and verify active low and active high SR
12 08 Latch operations using Two NOR or Two NAND gates & LAB TASK 8
Module KL-33001 & ELVIS II
To implement and verify Gated D Latch using Two NOR
13 09 LAB TASK 9
and Two AND gates with Module KL-33001 & ELVIS II
To implement and verify J K with Preset and Clear input
14 10 using 7476 IC , Module KL-33001 & ELVIS II and LAB TASK 10
Revision
FINAL EXAMS
Digital Logic Design Labs Fall 2021
Course Learning Outcomes
Course Learning Outcomes (CLO)
1 To apply the techniques/methods for simplification of complex logic
circuits/expressions/truth tables.
2 To implement the combinational and sequential circuits according to their applications.
3 To analyze and verify combinational and sequential logic practically.
CLO-SO Map
SO IDs
CLO GA1 GA1 GA1
GA1 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9
ID 0 1 2
CLO 1 1 0 0 0 0 0 0 0 0 0 0 0
CLO 2 0 0 1 0 0 0 0 0 0 0 0 0
CLO 3 0 0 0 0 1 0 0 0 0 0 0 0
Approvals
Prepared By Muhammad Fayyaz uddin
Approved
By
Last Update
