Experiment 4: Write a VHDL code to describe the functions of 3 bit 4x1 Multiplexor
In VHDL, the process statement contains sequential statements. Processes are only permitted inside an architecture. The
statements within processes execute sequentially, not concurrently. Processes can be written in a variety of ways
------------------------------------------------- --
VHDL code for 4:1 multiplexor
-- Multiplexor is a device to select different inputs to outputs. we use 3 (a2a1a0)bits vector to
describe its I/O ports
Code:
-- Multiplexor is a device to select different
-- inputs to outputs. we use 3 bits vector to
-- describe its I/O ports
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity mx22 is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end mx22;
-------------------------------------------------
architecture behv1 of mx22 is
begin
process(I3,I2,I1,I0)
begin
-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "zzz";
end case;
end process;
end behv1;
Task 1)RTL design:
Task2)Functional wave form with your result
EX2: USING choosing statments TO DESGIN 4X1 MUX(ONE BIT)
1-(Using if -- elseif statements.)
library ieee; one bit 4x1 mux
use ieee.std_logic_1164.all;
entity mx22 is
port (Sel : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic );
end mx22;
architecture behavior1 of mx22 is
begin
process (Sel, A, B, C, D)
begin
if (Sel = "00") then Y<= A;//I0
elsif (Sel = "01") then Y<= B;//I1
elsif (Sel = "10") then Y<= C; //I2
else Y<= D; //I3
end if ;
end process ;
end behavior1;
2-using case statment
library ieee;
use ieee.std_logic_1164.all;
entity mx22 is
port (Sel : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic );
end mx22;
architecture behavior2 of mx22 is
begin
process (Sel, A, B, C, D)
begin
case Sel is
when "00" => Y<=A;//I0
when "01" => Y<=B;//I1
when "10" => Y<=C;//I2
when "11" => Y<=D;//I3
when others => Y<=A;
end case ;
end process ;
end behavior2;
---------------------------------------------------------------------------------------------------------------
3-- Using conditional signal assignment :
library ieee;
use ieee.std_logic_1164.all;
entity mx22 is
port (Sel : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic );
end mx22;
architecture behavior3 of mx22 is
begin
Y <= A when Sel = "00" else
B when Sel = "01" else
C when Sel = "10" else
D when Sel = "11";
end behavior3;
4- Using selected signal assignment :
library ieee;
use ieee.std_logic_1164.all;
entity mx22 is
port (Sel : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic );
end mx22;
architecture behavior4 of mx22 is
begin
with Sel select
Y<= A when "00",
B when "01",
C when "10",
D when "11",
A when others;
end behavior4;
