there in Sem32

IH timers are

b Advanced timers its

Timers Timers
features are rarely used
too

if used then as normal

timers only
To
Timer 6 Tiner Basic timers
cannot do i p capture or
op compare
can only count internal pulses
or capable of counting
external pulses
Cannot generate PWM
16 Bit timers

Timer9 to Timerly so Similar behaviour as

of timer 2 to timer 5
difference being Tim9
to Tim 14 are 16 bit
Timer2 to liner 5 to Tim 3 Timm are
16 bit timers
32 bit timers Tim 2
Tim 5 are 32 bit timers
As there are
large no
of linens
present in Sem 32
The manufacturer has divided then into
chunks
Tmatimitteoinetted
two 32 bits
to the same
Bus

6GR
Tim9 to TIMM's connected to a different
APB Bus
all are 16 bits
geneual purpose timers
Each of these timers are four channel
or two channels

God 71mg to TIMM as 2 channel timer

to Tim 2 to Tims 4 Channel timer
 Major features of timers
or features of time to Tims are discussed

apply to TIM9 to 71m14

apply to TIMI TIM 8

he
only basic timing and counting
features are possible for TIM 6871Mt
so Counting internal pulses Timer
Counted
Counting external pulses
Timer act as both

Input Capture
used
for measuring time measure fog
output compare
used for generating waveforms
Lt Square rect pulse waveforms

used for raising interrupts

t PWM 2oz
Inbuilt inside timer
change duty the
Inbuilt In 57m32
as separate module in LPC2378
cycle to get
results
 Rough dia of a
Single 57m32
Timer

pummetitifitstories
to
eatsignal intAPB
filters are
there for
proper Syne 2 BASE OF THETIMER

of Ilpsignals Prescaler
Autoreloading

REG
COUNTER

3
Ypto
Trio
registers

or any one of the

Yp can be CIA
Source psube
Cascaded
I two I
can

go as up to another time
5 Inputcapture a op compare
operations operations
 Basic part of 52m32 timer

APB CIN
t
can be
changed
APBI APB2 routine
APB 2 is twice CSTM32only

ofAPB 1
APB2man frey or 84MHz
APB 1 man freq armies overflow
AChanges
when nest
event occurs
upcounter FF FF happens when
Downcounter 00004
toundergo timer overflows

Counter register TI MCN

16 bit timer for 71M3 TIMM

32 bit timer for 71M2 TIME
Sizeof Tmx one
veg
16 bit prescaber
can be changed runtime CSM32

thangs when went event occurs

tweenor underflows
time overflows

to Upcounter FFF Fm

Hy
overflows
Downcounter 0000m
Is undouflows
my y guy you
there is an
yp capture
cases or
op compare
be forced to
the software can create an
event also

The changed valve provided to the

is
presenter keptthe in event
shadow
registers untill occurs

when writing into prescriber Counter when

they are running you are writing into
shadow
a neg
A v70 Reload register TIMARR
Everytime an event occurs TIMARA's value
will get reloaded into the counter
 Differences btw the Timers of STM 32 LPC23xx

Cascading of timers in LPC 2378 is

not possible
More no Uk sources in SEM32 s
timer of
2 ent trigger Cir
timer yp capture that act as Un
Cascade Yp can act as a cat
filtered timer channels acting as
a cir
internal Clr also
Multiple prescalens are present in sem32
I prescaler
channel
presence of various filters to make the
est Signal noiseless
up down counting is not present in LPC 2378

Programing the timer for Yp Capture

I
 upcounting

APB
intCIK halve
equiv 1
value 0005m

upcounting soooo 0001 0002 0005

Iver is event it
as
reset tooooo matches with TIMARR

Interrupt raised
Downcountry
also value 0005
AFAIK Gave
equiv't
value 0

Downcountings0005 30004 0000

timer is resit
tentas it matches
to 0005 a with TIMARR
Interrupt
raised

Up downcounting
first counts up say TIMARR 0005
Country 0 I 2 3 4 54 3 218Th
9 Is switches
reaches
ARR I to downcountry
 CLK SELECTION
Capture trigger

TIMERI CH2

Cin
L
IF fixed

selects

selectthe Irate
edge deselect
ext model
sets eat cir mode1
as thecar prescaler

Internal elk can also

beselected

External trigger to ETR trigger

prescaler
available with forfiltering
ent trigger the op

These both are the 4ps to the Cla

 to capture trigger

ETRtrigger

no cascaded
mode

CAPTURE MATCH

CAPTURE

Risingedge Pre Scaler ups are

filtered and
Falling edge filter prescaled
both edges Overflow
O what is timer overflow
Suppose you are measuring a
very low frog
I T
We timer is 16 bits and the next
isof not registered even
rising edge
when all the 65536 transitions of the
counter have elapsed
The timer has overflowed here
In this case an interrupt is generated
by the counter
COMPARE
Set Reset Toggle

It allows a set reset or toggle on a match

is used
The compare operation
for Pwm

Pwm
PW
Is 2
types edgealigned

centrealigned
2 Registers used for Pwm
are
Auto reload
veg
Comp capture veg

How does Pwm is implemented

Suppose edge based PWM
0 ARR veg has value 0 08
Valve in Cap veg 0 04
 EDGE ALIGNED PWM

The counting is like

O 1 2 3 45 6 7 80 I 2 314 5 6 78 0 I 2

resets at this

capture
neg
70N
qtr Mdivider
point
Ton

TOFF
UXCIA time

5 X Cla time
for Cia
value s
Array
OFF
CTRL Crimea

CENTRE ALIGNED PWM

Captureevey Oxon
ARR evey 0 08

counting is like

01 2 34 5 6 78 7 6 54 3 2 10 I 2 3 45
A
dapregnal 1 ARReveyval

Upcounting L Down counting upcounting

switches from copcounting
to Downcounting the centre
 Time period is double to that of edge
aligned

Registers that are new in Sem 32

only those registers are covered that were

not in LPC2378

TIMER Control Register

count once only

ajo
m enable

É
counter

enablesdisables
the samples
p
goingto be
La 0 upcounting
1 Downcountry

www.joaawimai
anyevents Countmode selectbits
of the timer tho asample
o enabled
O s disabled resample bit
I I oo aireveybit
decidecountry
dir
os countupas
wellasdown
Requestselectbit Buteventswill
consideredevents betriggeredonly
O
Underflow dosingupcountry
overflow so countupas
wellasdown
YpCap Buteventswill
ofp match betriggeredonly
Is Software created duringdowncountry
events are alsoconsidered as countupas
wellasdown
events are
triggeredfor
both dir
2 TIMER DMA Interrupt Control Register
event happens you can have
whenever
Interrupt raised or DMA raised
DMA CTRL INTR CTRL

faintanyway
j
all bit open
raised
way to ger gem
makethis bit 1 htt
Intr Ctrl part
nth associatedwith
Capture compare open

DMA operation are associated with timer

in only 57m32
TIMER status register
r whether flag condition is there on not

x T Freiegen
underflow
overflow trigger
TIMER external generator evey
to set OG bit for status neg flag setting
to trigger capture Compare open