Microprocessor ProgrammingandInterfacing

Introduction

Vipin Kizheppatt 10/01/2024

 Course Administration
Schedule

Lecture: Mon, Wed 9:00 - 9:50 AM, Thu 2:00-2:50 PM

Tutorial: Thu 8:00-8:50 PM
Lab: Mon 11:00-12:50 PM, Sat 11:-12:50 PM at CC
Lab

Teaching Team
IC: Vipin Kizheppatt (D212, Ph: +91-
832-2580-383
email: kizheppattv@goa.bits-pilani.ac.in)
Instructors: Amalin Prince A, Manish Gupta, Arun
Raman
 Course Objectives

1. Describe the basic architecture of

microprocessors.
2. Able to write simple to moderately complex
assembly level programs for x86 processors.
3. Able to interface different peripherals (such as
DMA controller, ADC, DAC etc.) with 8086
microprocessor and control them through software.
4.Interface interrupt controller with 8086
microprocessor and write interrupt service routine
for the peripherals.

Text Book: Barry B Brey, The Intel

Microprocessors.Pearson, Eight Ed. 2009
Reference Book: Douglas V Hall, Microprocessor and
Interfacing, TMH, Second Edition
 Evaluation Scheme
Component Duration Weightage (%) Date & Time OB/CB
Midsem Exam 90 Mins 25% 15/03/24 CB
11:00AM-
12:30PM
Quizzes 4 quizzes with 15% Feb 9-12 March CB
10 mins each. 1-4 March 29-
Best 3 will be April 1 April 19-
considered for 22
grading
Evaluated Labs 4 evaluated 15% Feb 9-12 March OB
labs, each one 1-4 March 29-
1.5 hrs. Best 3 April 1 April 19-
will be 22
considered for
grading
Lab Compre 1.5 hrs 10% April 26-April 29 OB
Comprehensive 3 hrs 35% 10/05/24 (AN) OB+CB
Examination

NB: 80% lab attendance is required to appear for lab

 CPU vs MicroProcessor

Motherboard of an early 2000 computer

AGC prototype of Apollo (Image source: Wikipedia)

 Why to
study an
obsolete
processor?
CPU Architecture

ALU

Control Unit

Microprocessor
Architecture
 ALU Design
Full
Adder

Circuit
diagram

4 bit adder by cascading four 1 bit Abstracted

symbol
 ALU Design

Adder/Subtractor Multiplier
4 4
4 4
4 4

Comparator Complement
4
4 4 4
4
 The ALU
4 Add/Sub
4
4
ALU
4 Multiplier 4 data_in
4 4
4 1 data_o
: ut
4
1 4
4 Comparator data_in
4 M 4
2
4 u
x Contr
2
Complement ol
Abstract
4 4
Model
Contr The multiplexer (MUX) chooses
ol the output of a particular circuit
based on the control signal
 The ALU

ALU
data_in 4
1 data_o
ut
4
data_in 4
2
Contr
2
ol
Abstract
Model
ALU requires some data to operate on
It requires some control signals also to
specify the type of operation to perform
 Registers
But for ALU to process data it should be stored
somewhere
Output of ALU needs to be stored somewhere
so that it can process new data
That is where registers are useful
A register is a bunch of flip-flops storing
different bits of same data
D Q D Q D Q D Q
CL CL CL CL
K K K K
E E E E
n n n n

A 4-bit
register
 Registers
DataI 4
n
E
n

DataO 4
ut

Control Unit Reg

1

Reg
2

AL
U

Resul
t

Microprocessor
 Register File
E Reg 0
n

E Reg 1
Write n
Register
Address E
Reg 2

.
n
RegWriteE

.
n
Ad
dre
ss
Dec
ode
.
r
E Reg 31
n
 Register File
Write Register
Data
Reg 0

Reg 1
Write
Register
Address
Reg 2
RegWriteE
.
.
n
Ad
dre
ss
Dec
ode
.
r
Reg 31
 Read Register Address
Register File 1

Write Register
Data
Read
Reg 0 Register
Data 1
MU
Reg 1 X
Write
Register
Address
Reg 2
RegWriteE
.
.
n
Ad
dre
ss
Dec
ode
. Read
Register
Data 2
r
Reg 31 MU
X

Read Register Address

 Register File
RegWriteE
Control Unit
RegFile
n

Read Read
address 1 data
1
Read
address 2 Read
data
Write 2
address
Wri Register File AL
te U
data

Microprocessor
Architecture
Registers store data temporarily
Register file require control signals to specify in which register
data should be stored, which register value should be
propagated to ALU etc.
Stored Program Computer Model
Processor
Memory

In this model a computer has a fixed hardware architecture

but can perform a variety of operations through
program/software
Software is composed of code and data
Software is stored in memory and the processor fetches
instructions from the memory in a sequential manner and
executes them
 Software
Assume you need to add two variables and find the result
c=a+b

dat
a cod
e
 Software
We know ultimately addition will be performed by ALU
a, b and c should be mapped to some registers
Assume a is mapped to register 0 (reg address 0), b to
register 1 and c to register 2 (reg address 2)

RegWriteE
n ALU
Read
address 1
Read data_in 4
data
1 1 data_o
Read
address 2 Read
ut
4
Write
data data_in
2
address 2 4
Wri Register File
te Contr
2
data ol
Abstract
Model
 0 to choose register-0
Software
RegWriteE
n ALU
Read
address 1
Read data_in 4
data
1 1 data_o
Read
address 2 Read
ut
4
Write
data
2
data_in
address 2 4
Wri Register File
te Contr
2
data ol
Abstract
Model

1 to choose register-1 2 to choose register-2

0 to choose addition operation

 Software
RegWriteE
n ALU
Read
address 1
Read data_in 4
data
1 1 data_o
Read
address 2 Read
ut
4
Write
data
2
data_in
address 2 4
Wri Register File
te Contr
2
data ol
Abstract
Model

Control logic
 Software
Assume there are 8 registers in the processor hence 3 bits to
specify the register address
Combined signals from CU might look like this
00 000 001 010

Register 0
Indicate add operation Register 1 Register 2

Writing in binary is cumbersome, so usually prefer

hexadecimal
0x00A or 00AH
 Software
So 00AH can be called as an instruction to add the contents
of register0 and register1 and store in register2 for our
hypothetical processor
As humans, it is quite difficult and error prone to
memorize/write programs using instructions even in
hexadecimal
Hence we use symbolic English like mnemonics to write
programs
Eg: ADD r2,r1,r0
Later will use tools such as an assembler to convert these
mnemonic representation into numbers which the actual
processor understands!!
Since we are using stored program model, we need a
memory model now to interface with processor. Let’s build it
next
Memory Abstract Model

Memory

Address [a1:a0]

Data[3:0]

WE#

RE#
 Sample assembly program and
machine code
Aim  Add 20H and 30H and store the result in
memory location 000AH
Assembly Code Hex Code
MOV A,#20H 3E 20
MOV B,#30H 06 30
ADD A,B 80
MOV [000AH],A 32 0A 00
HLT 76
Program Execution Somehow got the
programme in
the
memory Latch
00111110 0
(3EH)
XX XX XX XX 00100000 1
A
cc
B C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
A0 Bus 00000000
(0AH) 7
D7 –
Data 10000101
D0 Bus
RD (00H) 8
WR
# 01110110
#
XXX (76H) 9
P X X
C X A
CP X
U X
Memor
y
Program Execution Somehow got the
programme in
the
memory Latch
00111110 0
(3EH)
XX XX XX XX 00100000 1
A
cc
B C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0000 Address (32H) 6
A0 H Bus 00000000
Data (0AH) 7
D7 – Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0000 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
XX XX XX XX 00100000 1
A
cc
B C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0000 Address (32H) 6
A0 H Bus 00000000
3E Data (0AH) 7
D7 – H Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0000 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Control logic decodes
instruction, realizes Latch
00111110 0
need to read another (3EH)
XX XX XX XX 00100000 1
A B C D data and store in A. (20H)
Reset cc starts next read cycle 2
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
3E A0 Bus 00000000
H Data (0AH) 7
D7 – Bus 10000101
RD (00H) 8
D0 WR
# 01110110
#
0000 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
XX XX XX XX 00100000 1
A
cc
B C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0001 Address (32H) 6
A0 H Bus 00000000
Data (0AH) 7
D7 – Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0002 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
XX XX XX XX 00100000 1
A
cc
B C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0001 Address (32H) 6
A0 H Bus 00000000
20 Data (0AH) 7
D7 – H Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0002 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Control logic stores Latch
00111110
the data in the A 0
(3EH)
XX XX XX XX register. Increments 00100000 1
A B C D the PC (20H)
Reset cc 2
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
20 A0 Bus 00000000
H Data (0AH) 7
D7 – Bus 10000101
D0 RD (00H) 8
WR
# 01110110
#
0002 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
20 30 XX XX 00100000 1
HAcc BH C D (20H) 2
Reset
# M 00000110
UX Similarly stores 30H in (06H) 3
B register 00110000
ALU 4
XX (30H)
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
A0 Bus 00000000
Data (0AH) 7
D7 – Bus 10000101
D0 RD (00H) 8
WR
# 01110110
#
0004 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
20 30 XX XX 00100000 1
H
A
cc
BH C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0004 Address (32H) 6
A0 H Bus 00000000
Data (0AH) 7
D7 – Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0004 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
20 30 XX XX 00100000 1
H
A
cc
BH C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0004 Address (32H) 6
A0 H Bus 00000000
80 Data (0AH) 7
D7 – H Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0004 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Control logic decodes
instruction, realizes it Latch
00111110 0
needs add the (3EH)
20 30 XX XX 00100000 1
H
A BH C D contents of A and B (20H)
Reset cc and store the result in 2
# M
A 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
80 A0 Bus 00000000
H Data (0AH) 7
D7 – Bus 10000101
RD (00H) 8
D0 WR
# 01110110
#
0005 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
50 30 XX XX 00100000 1
HA BH C D (20H)
Reset cc 2
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
A0 Bus 00000000
Data (0AH) 7
D7 – Bus 10000101
RD (00H) 8
D0 WR
# 01110110
#
0005 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
50 30 XX XX 00100000 1
H
A
cc
BH C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0005 Address (32H) 6
A0 H Bus 00000000
Data (0AH) 7
D7 – Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0005 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
50 30 XX XX 00100000 1
H
A
cc
BH C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 0005 Address (32H) 6
A0 H Bus 00000000
32 Data (0AH) 7
D7 – H Bus 10000101
D0 RD 0 (00H) 8
WR
# 01110110
#
0005 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Control logic decodes
instruction, realizes it Latch
00111110 0
store the content of A (3EH)
50 30 XX XX 00100000 1
H
A BH C D register back to (20H)
Reset cc memory. Address 2
# M
where it has to be 00000110
UX
(06H) 3
stored has to be taken 00110000
ALU from the memory 4
XX (30H)
F
itself!! 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
32 A0 Bus 00000000
H Data (0AH) 7
D7 – Bus 10000101
RD (00H) 8
D0 WR
# 01110110
#
0008 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
This is the address
were result has to be Latch
00111110 0
stored (3EH)
50 30 XX XX 00100000 1
H
A
cc
BH C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
000A A0 Bus 00000000
H Data (0AH) 7
D7 – Bus 10000101
RD (00H) 8
D0 WR
# 01110110
#
0008 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
50 30 XX XX 00100000 1
H
A
cc
BH C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 000A Address (32H) 6
A0 H Bus 00000000
0050 Data (0AH) 7
D7 – H Bus 10000101
D0 RD (00H) 8
WR
# 0
01110110
#
0008 (76H) 9
P H X
C X A
CP X
U X
Memor
y
Program Execution
Latch
00111110 0
(3EH)
50 30 XX XX 00100000 1
H
A
cc
BH C D (20H) 2
Reset
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - 000A Address (32H) 6
A0 H Bus 00000000
0050 Data (0AH) 7
D7 – H Bus 10000101
D0 RD (00H) 8
WR
# 0
01110110
#
0008 (76H) 9
P H X
C X A
CP 5
U 0
Memor
y
Program Execution
When the processor
sees HALT instruction, Latch
00111110 0
it stops execution and (3EH)
50 30 XX XX 00100000 1
H
A BH C D the PC no longer (20H)
Reset cc increments 2
# M 00000110
UX
(06H) 3
00110000 4
ALU (30H)
XX
F 10000000
(80H) 5
00110010
Control logicA15 - Address (32H) 6
76 A0 Bus 00000000
H Data (0AH) 7
D7 – Bus 10000101
RD (00H) 8
D0 WR
# 01110110
#
0008 (76H) 9
P H X
C X A
CP 5
U 0
Memor
y