UNIVERSITY OF EAST LONDON
Assignment Title: Xilinx Design lab using
VHDL
Module Code:
Module Name: Embedded Systems
spervisor: Andrew Chanerley
Submission date:
Aims:
• Design an AND gate interface and check if waveforms are correct
• Design an 8-bit counter interface and implement a hexadecimal display using VHDL
1. AND Gate
Program
The AND function is implemented with two inputs and one output. The following code represents
the function of the AND gate in VHDL, this is entered into the design window:
___________________________________________________________
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY cct2 IS
PORT (
in0 : in STD_LOGIC;
in1 : in STD_LOGIC;
out1 : out STD_LOGIC);
END cct2;
ARCHITECTURE Behavioral OF cct2 IS
BEGIN
out1 <= (in0 and in1);
END Behavioral;
________________________________________________________
2.2 Test Bench: AND Gate
_________________________________________________________________
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_test1 IS
END tb_test1;
ARCHITECTURE behavior OF tb_test1 IS
COMPONENT my_and
PORT(
in0 : IN std_logic;
in1 : IN std_logic;
out1 : OUT std_logic
);
END COMPONENT;
signal in0 : std_logic := '0';
signal in1 : std_logic := '0';
signal out1 : std_logic;
BEGIN
uut: my_and PORT MAP (
in0 => in0,
in1 => in1,
out1 => out1
);
stim_proc: process
BEGIN
wait for 100 ns;
in0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns ;
in1 <= '0' after 0 ns, '1' after 15 ns, '0' after 25 ns ;
wait;
end process;
END;
_________________________________________________________________
Simulation
After the test bench code is complete, the waveform below in opened.
Figure1.1 Waveform of the AND Gate
It can be seen that the output pulse is gives logic 1 when both input are high and a 0 for any other
combination of input which proves the functioning of the AND gate
It can be seen on the waveform that the output occurred after 115 ns but the test bench code had a
wait command of 100ns. The 15ns is a propagation delay used to calculate the output
• Design of the 8 bits counter
• Main Programme
The counter was designed using Xilinx software. First a project was created, the code below was
entered and a check for syntax errors was operated.
Main VHDL Counter Programme
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity leds8 is
GENERIC ( n: POSITIVE := 2**22);
Port ( clkin : in STD_LOGIC;
Clkout : out STD_LOGIC;
Leds : out STD_LOGIC_VECTOR (7 downto 0 7);
End leds8;
Architecture Behavioural of leds8 is
Begin
PROCESS(clkin)
VARIABLE count : INTEGER RANGE 0 TO n;
Variable counter : integer range 0 to 255;
BEGIN
IF(clkin’EVENT AND clkin=’1’) THEN
Count:=count +1;
IF (count=n/2) THEN
Clkout <=’1’;
ELSIF(count=n) THEN
Clkout <=’0’;
Count:=0;
Counter:=counter+1;
Leds <= conc_std_logic_vector(counter,8);
END IF;
END IF;
END PROCESS;
End behavioural;
• Test Bench File
The main counter programme was checked then a new source file was created. The test bench code
was entered, saved and checked for syntax. The test bench code below was given.
Test –bench code
LIBRARY ieee:
USE ieee.std_logic_1164.ALL;
ENTITY tb_leds8 IS
END tb_leds8;
ARCHITECTURE behaviour OF tb_leds8 IS
COMPONENT leds8
PORT( clkin : IN std_logic;
clkout:OUT STD_logic;
leds : OUT std_logic vector(7 downto 0 ));
END COMPONENT;
signal clkin : std_logic :=’0’;
signal clkout : std_logic;
signal leds : std_logic_vector(7 downto 0);
constant clkin_period : time:=125 ns;
BEGIN
Uut: leds8 PORT MAP(
clkin => clkin,
clkout => clkout,
leds => leds
);
Clkijn_process :process
Begin
Clkin <= ‘0’ ;
Wait for clkin_period/2;
Clkin <=’1’:
Wait for clkin_period/2;
End process;
Stim_proc: process
Begin
Wait for 100ns;
END;
• Pins Allocation and Simulation
This code allocates the FPGA pins and set them to the 8 leds or hex-displays and will enable the
board to send the right information to the leds.
#harwire pins
Net “clkin” LOC = P32;
Net “clkin” iostandard =lvcmos33;
Net “clkout” LOC = P90;
Net “clkout” iostandard =lvcmos33;
Net “leds<0>” LOC = P2;
Net “leds<0>” iostandard =lvcmos33;
Net “leds<1>” LOC = P3;
Net “leds<1>” iostandard =lvcmos33;
Net “leds<2>” LOC = P4;
Net “leds<2>” iostandard =lvcmos33;
Net “leds<3>” LOC = P5;
Net “leds<3>” iostandard =lvcmos33;
Net “leds<4>” LOC = P9;
Net “leds<4>” iostandard =lvcmos33;
Net “leds<5>” LOC = P10;
Net “leds<5>” iostandard =lvcmos33;
Net “leds<6>” LOC = P11;
Net “leds<6>” iostandard =lvcmos33;
Net “leds<7>” LOC = P12;
Net “leds<7>” iostandard =lvcmos33;
Behavioural Simulation: After All the steps above are completed, the work is saved and checked for
errors. In case of an error, a dialogue box will show the line in which there is a problem. When this is
done, the simulation button is pressed and this will change the design panel at the bottom left panel.
The errors are checked by pressing the Behavioural Check Syntax button and if there is not any, the
simulation can be operated by clicking on Simulate Behavioural Model. This invokes the simulator
with the waveform of the counter. The duration of the simulation is changed to any time between
3ms and 5ms. The page invoked can be seen below on figure 1.3
Figure 2 Simulation of the 8-bit Counter
After the counter is proven to work, the code is configured and can then be downloaded into the
FPGA. The file downloaded into the FPGA is located in the project folder has the extension .bin.
• Circuit construction
The file is sent into a memory card which is then connected to the FPGA board. The 8 leds are
connected to the board as seen on figure 3.1 and after the board is power on, the count starts and
operates the increment from 00000000 to 11111111.
• Hexadecimal display
Procedure
After the 8-bit counter works correctly, the hexadecimal displays can then be connected to count
from 00 to FF. Figure 3 show the circuit connection and pin allocations of each additional device
need to complete the hexadecimal display. The pins which were connected to the leds are
connected to line driver chip inputs (74LS244). Its output go into two hexadecimal ICs, The circuit is
then powered and should work normally
Figure 3.1 Circuit enabling the 8 leds count and hex-displays
Problems encountered
Due
to the complexity of the circuit and the use of wires, the circuit I build did not count properly. I
looked for the mistake but could not identify it. It could have been a bad bin connection or a loose
wire. A new circuit board including hex-displays and not requiring wires was then distributed. The
code was inserted into the FPGA again and it worked correctly this time. Figure 3.2 shows the
pictures of the new board operating.
Figure 3.2 hex-displays counting
