Computer Architecture

A Quantitative Approach, Fifth Edition

Computer Architecture
Appendix A
Instruction Set Principles
(Pages A1 – A7, A9)

Dr. Abdulmajeed Farea Aljunaid

1
 Instruction Set Principles Appendix A
 Introduction
 Classifying Instruction Set Architectures
 Addressing Modes
 Type and Size of Operands
 Operations in the Instruction Set
 Instructions for Control Flow
 Instruction Format
The RISC-V Architecture
 Conclusion

2
Introduction

3
 Introduction
An instruction set architecture is a specification
of a standardized programmer-visible interface
to hardware.
A set of instructions
 With associated argument fields, assembly syntax, and
machine encoding.
A set of named storage locations
 Registers, memory.

A set of addressing modes

 Ways to name locations

4
 RISC vs. CISC
• The RISC-based computers raised the performance
bar, forcing prior architectures to keep up or
disappear. (VAX changed and Intel adapted )

5
 Classifying Architectures
Classification is based on addressing modes.
 Stack architecture
 Operands implicitly on top of a stack.

 Accumulator architecture
 One operand is implicitly an accumulator

 General-purpose register architecture

 Register-memory architectures
– One operand can be memory.

 Load-store architectures
– All operands are registers (except for load/store)
6
 Four Architecture Classes
Assembly for C:=A+B ESV

Rok Ri

Memorg

7
 Classification based on Operands
 GPR architecture can also be classified based on
the number of operands for ALU instructions
 2-operand and 3-operand
 Further classification can be done based on the type
of operands

8
 Comparison of Architecture Types

Type Instruction Code # of Clock Code Size

Encoding Generation Cycles/Inst.
Register-
register Fixed-length Simple Similar Large

Register- Medium
memory Moderate Different Medium
Variable-length

Memory- Large
memory Complex Large variation Compact
Variable-length

Advantages
Disadvantages
9
 Endians & Alignment
• Byte order is a problem when exchanging data
among computers with different orderings.

oiÉ
m
integer a Byte low address

Kinross
is
41

• All the instruction sets discussed are byte addressed

and provide access for bytes (8 bits), half words (16
bits), and words (32 bits) and there is also double
words (64 bits).
• Depending on the instruction , the computer may
also need to sign-extend the quantity.
10
Endians & Alignment

11
 Addressing Modes
w̅ Mode Example Meaning
Register add r4, r3 R[4]R[4]+R[3] Register Values

Immediate add r4, #3 R[4]R[4]+3 Constants

Displacement add r4, 100(r1) R[4]R[4]+M[100+R[1]]Local Variables

Register indirect add r4, (r1) R[4]R[4]+M[R[1]] Pointer Access

Indexed add r3, (r1+r2) R[3]R[3]+M[R[1]+R[2]] Array Access

Direct/Absolute add r1, (1001) R[1]R[1]+M[1001] Static Data

ÉEmÉ
Memory indirect add r1, @(r3) R[1]R[1]+M[M[R[3]]] *p (Ptr Address)

Autoincrement add r1, (r2)+ R[1]R[1]+M[R[2]]

Array in a Loop
R[2]R[2]+d
Autodecrement add r1, – (r2) R[2]R[2] – d
Postdecrement R[1]R[1]+M[R[2]]
Scaled add r1, 100(r2)[r3] R[1]R[1]+M[100+R[2]+R[3]*d]

( )  memory access [ ]  accessing a Register or Memory location 12

 d e s
Addressing Mode Usage
I

3 SPEC89 programs on VAX

x̅
Fig A.7
• Displacement and immediate addressing dominate addressing mode usage.
• Compiler affects what addressing modes are used. 13
 v Displacement Distribution
Choosing the displacement field sizes is important because they directly
affect the instruction length.

Fig A.8
SPEC CPU2000 on Alpha Sign bit is not counted
14
 Use of Immediate Operand

• About one-quarter of data transfers and ALU

operations have an immediate operand.

SPEC CPU2000 on Alpha

15
 Distribution of Immediate
A similar measurement on the VAX, which supported 32-bit immediate,
showed that about 20%–25% of immediate were longer than 16 bits.
Thus, 16 bits would capture about 80% and 8 bits about 50%.

Sign bit is not counted

SPEC CPU2000 on Alpha 16
 Summary: Memory Addressing
• We would expect a new architecture to support at least the
following addressing modes: displacement, immediate, and
register indirect. Figure A.7 shows that they represent 75%–
99% of the addressing modes used in the measurements.
• We would expect the size of the address for displacement
mode to be at least 12–16 bits, because the caption in
Figure A.8 suggests these sizes would capture 75%–99% of
the displacements.
• We would expect the size of the immediate field to be at
least 8–16 bits.

17
 Type and Size of Operands
• Usually, encoding in the opcode designates the type of an
operand.
• Usually, the type of an operand—integer, single-precision
floating point, character, and so on—effectively gives its
size.

Float
i

18
 Why use Decimal?
Some architectures support a decimal format
Packed decimal or binary-coded decimal (BCD)
Why?
(0.10)10
= (?)2
Answers
 0.10
 0.0001
 0.1010
 0.000110011

Some decimal fractions does not have exact

representation in binary.
19
Instruction Type
oPtration T4

20
Top 10 Instructions for the 80x86

21
 Instructions for Control Flow
Four basic types:
 Conditional branches
w
Jumps (unconditional)

jumb
 Procedure calls
 Procedure returns fin

SPEC CPU2000 on Alpha

22
 Addressing Modes for Control Flow
 PC-relative (PC + displacement)
 Target is known at compile time.
 Position independence (relocatable)

Register indirect jumps (register has address

and Target is not known at compile time)
Procedure returns I
Case / switch statements
Virtual functions or methods
High-order functions or function pointers
Dynamically shared libraries
23
 Branch Distance Distribution

machine
fa.tt i It

SPEC CPU2000 on Alpha

24
 Conditional Branch Options

Resister

is L
me
• Computers with compare and branch (method 2) often
limit the set of compares and use a separate operation
and register for more complex compares.
25
 Procedure Calling Conventions
Two major calling conventions:
Caller saves: stacks
Before the call, procedure caller saves registers that will
be needed later, even if callee did not use them.
Callee saves: c sinus
iww.TW I
Inside the call, called procedure saves registers that it
will overwrite
Can be more efficient if many small procedures

Many architectures use a combination of both

For example, MIPS: Some registers caller-saves,
some callee-saves for optimal performance.
26
Branch Comparison Types

SPEC CPU2000 on Alpha

27
 Encoding An Instruction Set
 Trade-off between Code size and hardware complexity
 Coding addressing modes with each operand as address
specifier or coding them within opcode.

This style is best when there are many addressing modes and operations.
RISC 5

It works best when there are few addressing modes and operations.
Reduced code size in RISCs

28
 Putting It All Together
 RISC-V builds on 30 years of experience with RISC
architectures. Freely licensed open standard.
 Use GPRs with load-store architecture
 Support simple addressing modes Register Register
 Displacement (12-16), immediate (8-16), register indirect
e
 Support basic types
 8-, 16-, 32-, 64-bit integers and 32-, 64-bit floats
 Support most executed operations
 Load, store, add, subtract, move, and shift
 Compare equal/not equal /less, branch (PC-relative) with at
least 8 bits, jump, call, and return
 Instruction encoding based on goal
 Fixed encoding for performance and variable for code size.
 Provide at least 16 GPRs, and preferably 32 GPRs.
29
 The RISC-V Architecture In
 RISC, load-store architecture, three base instruction set.
 Variety of optional extensions to one of the base instruction sets.
 RV64IMAFD (also known as RV64G, for short)

extension

30
 The RISC-V Architecture
 32-bit or 64-bit instructions, hybrid format
 RV64G has 32 64-bit GPRs, R0-R31.
 R0 is just a constant 0. or
 32 64-bit FPRs, F0-F31
 Can hold 32-bit floats also (with other ½ unused).
 Instructions for moving between an FPR and a GPRs.

 Load/store 8-, 16-, 32-, 64-bit integers

 Allsign-extended to fill 64-bit GPR
 Also 32-bit floats/doubles

31
 RISC-V Addressing Modes

Life indirect

instration I I
jump 32
 RISC-V Addressing Modes
 SupportsIodefeatff
four
as (using two) addressing modes for
bespatter

data access.
 Displacement (offset 12 bits for load/store)
 Register indirect(base addressing): Set displacement
offset to zero
 Direct (absolute): set R to zero

 Immediate (12 bits for arithmetic/logical ops)

 RV64G is Byte-addressed memory, 64-bit address
 Little Endian byte numbering.
 Alignment required
755357 33
 Instructions Encoding RISC-V

IFYPE
5th
if
7

Rtype

0
34
 Instruction Format for RV32G
7 5 5 3 5 I
Enlist
b
0 0

REYPE
I TYPE

57p
SURE

type 35
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