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design Verification program

Course Curriculum

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 design Verification Course - Module 1
Digital electronics
➢ Advanced level Digital Mocktests
Live Session
➢ All type of Combinational Ckts Theory & Labs
➢ All type of Sequential Ckts
➢ Registers Hands on
Experience
➢ Counters
➢ FSMs and Its Application examples
➢ Memories Industry
Guidance
➢ Static Timing Analysis
➢ CMOS Logic Design
➢ Glitches & Hazards 24/7 Tool
Access
➢ Interview Preparation
➢ Assignments Placement
Assistance
 design Verification Course - Module 2
RTL Design using verilog hdl
➢ Language Introduction and Applications
Live Session
➢ Data types, Operators Theory & Labs
➢ All Description Styles
➢ Behavioral Modelling Hands on
Experience
➢ Dataflow Modelling
➢ Gate Level Modelling
➢ Switch Level Modelling Industry
Guidance
➢ Making Procedural Statements
➢ Making Continuus Statements
➢ Blocking and Non-Blocking Assignments 24/7 Tool
Access
➢ Introducing the Process of Synthesis
➢ Coding RTL for Synthesis Placement
➢ Modelling of Combinational, Flipflop, Registers, Assistance

Counters
 design Verification Course - Module 2
RTL Design using verilog hdl
➢ Designing Finite State Machines
Live Session
➢ Understanding the Simulation Cycle Theory & Labs
➢ Using Tasks & Functions
➢ Avoiding Simulation Mismatches Hands on
Experience
➢ Directing the Compiler
➢ Using Verification Constructs
➢ Coding Design Behavioral Algorithmically Industry
Guidance
➢ Coding and Synthesizing Examples
➢ Generating a Test Stimulus
➢ Developing a Testbench 24/7 Tool
Access
➢ Using System Tasks and System Functions
➢ Example Verilog Testbench Placement
Assistance
 design Verification Course - Module 3
SystemVerilog (Verification)
➢ SystemVerilog Overview
Live Session
➢ Standard Data types & Literals & Operators Theory & Labs
➢ User-Defined Data types & Structures
➢ Tb Architecture & Connectivity Hands on
Experience
➢ Testbench Components
➢ Static, Dynamic, Associative Arrays
➢ Queues Industry
➢ Tasks & Functions Guidance

➢ Interfaces, Virtual Interface

➢ Verification Features 24/7 Tool
➢ OOPs, Classes Access
➢ Polymorphism and Virtuality
Placement
➢ Inheritance, Encapsulation Assistance
➢ Clocking Blocks
 design Verification Course - Module 3
SystemVerilog (Verification)
➢ Clocking Blocks
Live Session
➢ Random Stimulus Theory & Labs
➢ Class-Based Random Stimulus
➢ Code Coverage Hands on
Performance Expectations
Experience
Of Employees & Superiors
➢ Deep into Functional coverage
➢ Assertion Based Verification(ABV)
➢ SystemVerilog Assertions Industry
➢ Direct Programming Interface(DPI) Guidance
➢ Interprocess Synchronization
➢ Testbench Components Setting Performance
24/7 Tool
Standards
➢ Testbench Examples Access
➢ Testplans, Testcases
Placement
Assistance
 design Verification Course - Module 4
UVM (Verification)
➢ Deep understanding of UVM in SOC | IP
Live Session
➢ Detailed explanation on UVC in SOC | IP Theory & Labs
➢ Introduction to UVM, Features
➢ Testbench Hierarchy, Components Hands on
Performance Expectations
Experience
➢ UVM Sequence Item, Sequence, Sequencer Of Employees & Superiors

➢ Configuration, UVM config_db

➢ UVM Phases
Industry
➢ UVM Driver Guidance
➢ UVM Monitor
➢ UVM Agent Setting Performance
24/7 Tool
➢ UVM Scoreboard Standards
Access
➢ UVM Environment
➢ UVM Test Placement
Assistance
➢ Creating all components in a flow
 design Verification Course - Module 4
UVM (Verification)
➢ Understanding of UVM RAL Model
Live Session
➢ Deep into UVM TLM Theory & Labs
➢ Callback
➢ Events Hands on
Performance Expectations
Experience
➢ UVM Test Of Employees & Superiors

➢ UVM Testbench Examples

➢ UVM Testplan Creation
Industry
➢ DTPs(Detailed Test Plan Exaplanation) Guidance
➢ Testcase scenarios
➢ Importance of Regressions Setting Performance
24/7 Tool
➢ How to Run the Regression Standards
Access
➢ How to check test pass or fail in SOC | IP
Level Placement
Assistance
➢ Idea on debugging testcases, execution flow
 design Verification Course - Module 5
Projects | Protocols
➢ RTL Design for UART Protocol, and detailed architecture implementation of Transmitter &
Receiver
➢ RTL Design and Verification of 4-Port Calculator

➢ I2C Protocol Implementation & Verification using SystemVerilog

➢ AMBA (APB, AHB, AXI) Protocols RTL Design & Verification in SV & UVM
➢ Deep understand into Signal features of AMBA Protocols

➢ 1*3 Router Project in UVM Verification

➢ Detailed knowledge on Test plan development, writing test cases

➢ 4 Port Calculator RTL Design & UVM Verification

➢ DMA Controller Project with Coverage analysis, RTL design & Verification
 design Verification Course - Module 6
Perl Scripting
➢ Importance of Perl Scripting
Live Session
➢ How to run the commands Theory & Labs
➢ Idea on Coverage analysis
➢ Upload and extract the coverage report Hands on
Performance Expectations
Experience
➢ Walk through perl concepts Of Employees & Superiors

➢ Coding standards
➢ Explanation of Data types, Arrays
Industry
➢ Hashes, Loops Guidance
➢ Operators, Subroutines
➢ Date & Time Setting Performance
24/7 Tool
➢ References, Formats Standards
Access
➢ Directories
➢ Error Handling Placement
Support