\

Amba AXI is targeted at high performance , suitable for high-speed submicron connect .

Features:
1.separate address/control and data phases
2.support for unaligned data transfer using byte strobes
3. Its backward compatible with existing AHB and APB interface

Architecture:
1.Axi protocol is burst based ,
2.every transaction has address and control information on the address channel
3. Total 5 channels

State the differnece between AXI3 and AXI4?

1. AXI3 supports burst lengths up to 16 beats only. While AXI4 supports burst lengths of up to
256 beats.
2. AXI3 supports write interleaving. AXI4 does NOT support write interleaving
3. AXI3 supports locked transfers, AXI4 does NOT support locked transfers
4. AXI3 does NOT suppor qos.AXI4 supports qos

I have seen many IP providers e.g. Synopsys supporting burst lengths up to 256 beats in AXI3
I have also seen many IP providers e.g. Synopsys NOT supporting write interleaving in AXI3.
Looks like the industry norm is to use AXI3 with burst lenghts up to 256 beats without support
for write Interleaving.

Qos interface signals

The AXI4 signal set is extended to support two 4-bit qos identifiers:
AWQOS: A 4-bit qos identifier, sent on the write address channel for each write transaction.
ARQOS: A 4-bit qos identifier, sent on the read address channel for each read transaction.

In this specification,
Axqos:indicates AW Q O S or ARQOS.
The protocol does not specify the exact use of the qos identifier. This specification recommends
that axqos is used as a priority indicator for the associated write or read transaction. A higher
value indicates a higher priority transaction.A default value of 0b0000.indicates that the
interface is not participating in any qos scheme.
Note
Additional interpretations of the qos identifier can be used.

Why there is no separate response channel for read burst ?

I would guess it is because the VALID/READY handshake mechanism only allows for traffic flow
in one direction, so for read transactions the traffic flow is slave to master for both data and
response, sharing a VALID/READY handshake, whereas for write transactions the data is master
to slave, but the response is slave to master, hence the response needing a separate channel to
support the required VALID/READY controls.
Or
While the write address and write data channel are in same directions,
The read address and read data channel are in opposite directions.

There needs to be a mechanism where a response is required back from the destination.
In case of read, the response can be the data, but it is actually the response that follows
the data on the same read channel, which comes from the destination
In case of write, there is NO data flow from destination to source if there was no response
channel
Now since the response always follows the data, the response channel in case of read is the
same as data channel
But in case of write, the response channel has to be separate as the ONLY channel from
destination to source.

Why there was no Write response for each beat in burst Write. But there is a seperate Read
response for each beat in a Read burst ?
All of the AXI channels pass information in only 1 direction (only the xready signal goes against
the channel direction), so for a slave to give a response back to the master for a write
transaction, would need a separate channel.

BRESP[1:0] =Slave=>Response channel

Write response. This signal indicates the status of the write transaction. The allowable
Responses are OKAY, EXOKAY, SLVERR, and DECERR.

RRESP[1:0]=Slave=>data channel
Read response. This signal indicates the status of the read transfer. The allowable responses
Are OKAY, EXOKAY, SLVERR, and DECERR

I guess this channel could have been defined to include a BRESP for each write data item, but
this would increase the bandwidth requirement for this channel, and as in most applications
you will just repeat the complete transaction for a non-OKAY response, few applications would
make use of the additional detail of which transfer in a write burst caused a failure.
You do give a RRESP response for each read data item because the higher bandwidth channel is
already there,

Difference between AHB and AXI?/ Name five special features of AXI?/ How AXI is different
from AHB?
1. AHB is Advanced High-performance Bus and AXI is Advanced extensible Interface.
2. When the Advanced High-performance Bus is a single channel Bus, the Advanced extensible
Interface is a multi- channel Bus.
3. In AHB, each of the bus masters will connect to a single-channel shared bus. On the other
hand, the bus master in AXI will connect to a Read data channel, Read address channel, Write
data channel, Write address channel and Write response channel.
4. The AHB is also a shared Bus whereas the AXI is a read/write optimized bus.
5. Bus latencies in AHB starts lower than the AXI.
6. The Advanced extensible Interface uses around 50 per cent more power, which means that
AHB has an edge over it.
7. AHB Bus utilization is higher than AXI utilization
8.In AXI - once you initiate a transaction, unless you get a response back, you cannot initiate
next transaction.In AHB - hope split-retry mechanism is available, with which the next
transaction can be initiated, without responding for the first transaction

AXI protocol – main features

•Properties
–High-bandwidth & low-latency design
–Good performance with long initial latency peripherals
–Flexibility in interconnection architecture
•Features
–Separate address/control and data phases
–Separate read & write channels, request/response channels
–Multiple outstanding addresses
–Out-of-order transaction completion

What is the AXI capability of data interleaving?

When multiple masters are connected, suppose master1 and master2 wants to perform a write
transaction to the same slave then Master1 with burst of 4 and Master2 with a burst 8

Master1 Master1 Master2 Master2 Master2 .. . Master1 Master1

which means that as the both the masters are accessing the same slave, when Master1 is in idle
state during the transaction then interconnect will perform the Master2 transaction.

This happens only in AXI3 where as in AXI4 the Data interleaving is removed as there is no WID
for the Data channel.

How to terminate A read/write burst ? Specification says we can not stop bursts
intermittently.
Answer : Simple answer, you cannot.
AXI=>As soon as the AXI master indicates that it will perform X number of transfers in a
transaction, it must complete X transfers. There is no "Early Burst Termination" concept like
there was in AHB.
For write transactions the master could complete the burst, but driving the WSTRB bits all to
logic '0' (dummy accesses) so that no data is actually being transferred to the slave, but for read
transactions there is no equivalent, and so "real" read accesses will be completed.

WSTRB[3:0]=Master=>Write Data channel signal and their is no similar signal with read data
channel
Write strobes. This signal indicates which byte lanes to update in memory. There is one
Write strobe for each eight bits of the write data bus. Therefore,
WSTRB[n] corresponds to WDATA[(8×n) + 7:(8×n)].

AHB=>In AHB Bursts can be early terminated either as a result of the Arbiter removing the
HGRANT to a master part way through a burst, or after a slave returns a non-OKAY response to
any beat of a burst. Note however that a master cannot decide to terminate a defined length
burst unless prompted to do so by the Arbiter or Slave responses.
All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.

Can A master can give WLAST in middle of a burst transfer ?

No. WLAST can only be asserted while WVALID is high when the final WDATA of a burst is being
transferred. Indicating WLAST (and WVALID) too early in a burst would be a protocol violation
Also, many slave designs will not use the WLAST input, and will simply count data items coming
in, so this would not be a safe (or legal) method of terminating a burst.

In the same way if slave asserts RLAST before the completion of a busrt read?
If the slave drives RLAST (and RVALID) too early, this too is a protocol violation, and just as for
the WLAST signal, some masters might not be monitoring RLAST, so this illegal use could be
missed anyway.
If WLAST and RLAST can not do the above cases, then what is the special use of WLAST and
RLAST because we are getting individual beat responses anyway?
WLAST and RLAST can be used by masters and slaves that need to be told when the final data in
a burst is being transferred. Most masters and slaves will count the data coming in against how
many transfers were indicated on AWLEN and ARLEN, so in these designs the xlast inputs would
not be required.
AWLEN[3:0]=Master
Burst length. The burst length gives the exact number of transfers in a burst. This
information determines the number of data transfers associated with the address.
ARLEN[3:0]=Master
Burst length. The burst length gives the exact number of transfers in a burst. This
information determines the number of data transfers associated with the address
However to support all master and slave designs, masters must always drive WLAST when
appropriate, and slaves must drive RLAST.

Whats the exact use of Exclusive Read and Write Pair transaction? Where exactly these will
be used?
The basic process for an exclusive access is:
1. A master performs an exclusive read from an address location.
2. At some later time, the master attempts to complete the exclusive operation by performing
an exclusive write to the same address location.
3. The exclusive write access of the master is signalled as:
• Successful if no other master has written to that location between the read and write
accesses.
• Failed if another master has written to that location between the read and write accesses. In
this case the address location is not updated.

Eg:-Now consider a system in which two AXI master devices are using same memory or we can
say in technical term using shared memory. And as a system designer you always will make sure
that at a time your one master does not overwrite your memory written by another master.

Consider AXI Master 1 (M1) has initiated exclusive read transaction for address location
12'h100 to 12'h10F. Now slave will start monitoring these addresses for ARID given by M1. Now
till exclusive write operation is performed slave monitors that address and if that address is
changed by another master M2 it will give indication of exclusive access failure during the
exclusive write transaction and memory is dose not get updated by M1.

What happened in above scenario is that Slave has reserved some memory resource for M1
virtually by given exclusive read request from master. When master comes for write transaction
for that memory location slave will allow to write that memory resource if only if another
master device is not using that memory resource other wise data is not written to memory
resource.

This way we can avoid memory overwrite problem for shared memory using EXCLUSIVE Access
in AXI.
or
I have directly written advantage of EXCLUSIVE ACCESS in AXI to know more how Exclusive
Access

If you have a shared area of memory used for passing control information between masters (or
processes running on a master), you want to make sure that you complete the READ/WRITE
sequence without another master changing the shared location.
If your master read the shared memory location, and it was changed by another master before
your master could complete the subsequent write to that location, the interim write from the
other master would be lost, which could have an impact on how your system works (control
information lost)
So Exclusive Accesses are a hardware mechanism to support the software, indicating to the
master when it did have uninterrupted access to the shared location, meaning that no write
accesses from other masters will be accidentally overwritten.

Is there a possibility that A Read transaction can complete in One Cycle ?

"A default ARREADY value of LOW is possible but not recommended, because it implies that
the transfer takes at least two cycles, one to assert ARVALID and another to assert ARREADY"
No.
It would take a minumum of 1 clock cycle to pass the address from the master to the slave
(assumes ARREADY was high when ARVALID was asserted), and then a minimum of 1 clock cycle
to pass the data from the slave to the master (assumes RREADY was high when RVALID was
asserted).

If ARREADY is initially low when an address is signaled on ARVALID, it will take one clock cycle
for the slave to sample this ARVALID and then assert ARREADY (if it can accept the address),
and the address handshake then completes on the next clock rising edge (when both ARREADY
and ARVALID are high). So 2 clock cycles just to pass the address from master to slave if
ARREADY defaults to LOW.
It would then take at least a further clock cycle before the read data could be returned to the
master.

"By using AXI IDs, a master can issue transactions without waiting for earlier transactions to
complete".
"When asserted, AWVALID must remain asserted until the rising clock edge after the slave
asserts AWREADY".
Can someone explain how these two are possible? Say for example, the slave doesn't assert
AWREADY?
In this case, can the master sill issue transactions without waiting for earlier transactions to
complete? I DONT think so!!!
Only one command on one channel(read/write/write data/read data/cmpl) may be issued at
a time. Unless this command
is accepted by the Slave, No command on the same channel may be issued, with or without
AXI ID?
Here is an example what this actually means:
If a master wants 2 kinds of data, and if there were no ID facility in AXI, then the master would
not be able to issue say read transactions in a read,read,read,read fashion, without worrying
about the return data. I.e. The Master would not be able to pipeline reads to facilitate
continuous data stream. This is because, the master would have no way
to identify which return data belongs to which 'kind'. However by attaching ID the master can
issue read0,read1,read0,read0,read1, and pipeline the 2 kinds of data to form a continuous
read data stream.
When the data comes back it will have a ID which will identify the data as of kind0 or kind1.
The two kinds of data can be say, 'data descriptor fetch' and 'data fetch'.

Relation between Write Address and Write Data channels:

Write address and write data channels must be presented to slave at the same time. I.e the
address and data must be aligned or re-aligned (by the interconnect i.e by the fabric). This
means that the write address and write data channel cannot be independent. This is because
the address identifies the slave. If the write address and write data channels are not in sync,
then the slave will NOT receive the address and corresponding data.

INFO:
Once VALID signal is asserted, it must remain asserted until the handshake occurs, at a rising
clock edge at which VALID and READY are both asserted.
If READY is asserted, the destination is permitted to de-assert the READY signal before VALID is
asserted. Even if a slave has only one source of read-data, it must assert the RVALID signal only
in response to a request for data.

For a write transaction, a single response is signaled for the entire burst, and not for each data
transfer within the burst.While, in a read transfer, the slave can signal diff responses for
different transfers in a burst. For example, in a burst of 16 read transfers, the slave might return
an OKAY response for 15 of the transfers and a SLVERR response for one of the transfers.

Slaves are required to reflect on the appropriate BID or RID response an AXI ID received from a
master.
The interconnect appends additional bits to the ARID, AWID and WID identifiers that are unique
to that master port.
This means:
1). A masters on a fabric need not worry about what ID the other masters(s) would use, as the
ID will be uniquified by the fabric
2). ID width at slave will be larger than the ID width at Master.

ORDERING:
A AXI4 Master(i.e. Without any WID signal in its write data channel), MUST issue the write data
"in the same order in which it issues the transaction addresses".
The slave must ensure that the RID value of any returned data matches the ARID value of the
address to which it is responding.

Explain about burst length and burst size ..

Burst length gives the exact number of transfers in a burst. For example if ARLEN/AWLEN is
[3:0] then It can be 1,2,3...16. For wrapping burst is 2^n i.e. 2,4,8...16.
Burst size (AWSIZE) indicates the size of each transfer in the burst. Here byteLane strobe comes
into picture. It can be 1,2,4,...128bytes.
These are the constraints which detects maximum transfer size of AXI burst i.e. 4KB.

Why and how 4KB boundary limit is imposed?

A burst must not cross a 4KB address boundary.
Note
This prevents a burst from crossing a boundary between two slaves. It also limits the number of
address increments that a slave must support
Lot of things on computer hardware is bounded to 4 kB. Maybe it's because DDR memory rows
are 4 kB in size, so crossing such a boundary would force the memory controller to run two row
fetch operations. But once the limitation is set, I'm not sure it helps asking why they did it
__________________________________________
Explain the valid ready handshake in AXI?
Each of the five independent channels consists of a set of information signals and uses
a two-way VA L I D and READY handshake mechanism.
The information source uses the VA L I D signal to show when valid data or control
information is available on the channel. The destination uses the READY signal to show when it
can accept the data. Both the read data channel and the write data channel also include a LAST
signal to indicate when the transfer of the final data item within a transaction takes place.
______________________________________________________________________________
Explain the channel concept
AXI protocol – the 5 channels

Read and write address channels

Read and write transactions each have their own address channel which carries all of the
required address and control information for a transaction.
The following mechanisms are supported:
• variable-length bursts, from 1 to 16 data transfers per burst (axlen signal)
• bursts with a transfer size of 8-1024 bits (axsize signal)
• wrapping, incrementing, and non-incrementing bursts (axburst signal)
• atomic operations, using exclusive or locked accesses (axlock signal)
• system-level caching and buffering control (axcache signal)
• protection information (axprot signal)
• control information on read/write channels are maintained until the corresponding xready
signal is asserted
Read data channel
The read data channel conveys both the read data and read response information
from the slave back to the master. It includes:
• the data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide (RDATA)
• a read response indicating the completion status of the read transaction.
• data and response group signals are maintained until the rready signal is asserted

Write data channel

The write data channel conveys the write data from the master to the slave and includes:
• the data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide (WDATA)
• one byte lane strobe for every byte, indicating which bytes of the data bus are valid (WSTRB)
• the last transfer inside a burst must be signalled through the WLAST signal
• data, strobe and wlast information are maintained until the wready signal is asserted
Write Response channel
The write response channel provides a way for the slave to respond to write transactions.
• All write transactions use completion signaling.
• The completion signal occurs once for each burst, not for each individual data transfer
within the burst.
• Response group signals are maintained until the bready signal is asserted

AXI Protocol – Transaction Ordering

•Transactions from different masters can complete in any order
•Read and write transactions from the same master can complete in any order
•Done using transaction ids for each channel
•ARM1176 does not support it yet! Ó feature not implemented into RAPU PSS bridges

Explain out-of-order concept?

Out-of-order transactions can improve system performance in two ways:
•The interconnect can enable transactions with fast-responding slaves to complete
in advance of earlier transactions with slower slaves.
•Complex slaves can return read data out of order. For example, a data item for a
later access might be available from an internal buffer before the data for an
earlier access is available

What is fixed burst type?

___________________
Explain the AXI response types?
The AXI protocol allows response signalling for both read and write transactions. For
read transactions the response information from the slave is passed alongside the read
data itself, however for writes the response information is conveyed along the write
response channel.
The AXI protocol responses are:
•OKAY
•EXOKAY
•SLVERR
•DECERR.

________________
______________________________________________________________________________
AHB

The Advanced Microcontroller Bus Architecture (AMBA)

specification defines an onchip communications standard for designing high-performance
embedded microcontrollers.
Three distinct buses are defined within the AMBA specification:
• the Advanced High-performance Bus (AHB)
• the Advanced System Bus (ASB)
• the Advanced Peripheral Bus (APB).
Advanced High-performance Bus (AHB)
The AMBA AHB is for high-performance, high clock frequency system modules. The AHB acts as
the high-performance system backbone bus. AHB supports the efficient connection of
processors , on-chip memories and off-chip external memory interfaces with low-power
peripheral macrocell functions. AHB is also specified to ensure ease of use in an efficient design
flow using synthesis and automated test techniques.

Advanced System Bus (ASB)

The AMBA ASB is for high-performance system modules. AMBA ASB is an alternative system
bus suitable for use where the high-performance features of AHB are not required. ASB also
supports the efficient connection of processors, on-chip memories and off-chip external
memory interfaces with low-power peripheral macrocell functions.

Advanced Peripheral Bus (APB)

The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power
consumption and reduced interface complexity to support peripheral functions. APB can be
used in conjunction with either version of the system bus.

Terminology
The following terms are used throughout this specification.
Bus cycle: A bus cycle is a basic unit of one bus clock period and for the purpose of AMBA AHB
or APB protocol descriptions is defined from rising-edge to rising-edge transitions. An ASB bus
cycle is defined from falling-edge to falling-edge transitions. Bus signal timing is referenced to
the bus cycle clock.

Bus transfer: An AMBA ASB or AHB bus transfer is a read or write operation of a data object,
which may take one or more bus cycles. The bus transfer is terminated by a completion
response from the addressed slave. The transfer sizes supported by AMBA ASB include byte (8-
bit), halfword (16-bit) and word (32-bit). AMBA AHB additionally supports wider data transfers,
including 64-bit and 128-bit transfers. An AMBA APB bus transfer is a read or write operation of
a data object, which always requires two bus cycles.
Burst operation: A burst operation is defined as one or more data transactions, initiated by a
bus master, which have a consistent width of transaction to an incremental region of address
space. The increment step per transaction is determined by the width of transfer (byte, half
word, word). No burst operation is supported on the APB.

A typical AMBA AHB system design contains the following components:

1)AHB master: A bus master is able to initiate read and write operations by providing an
address and control information. Only one bus master is allowed to actively use the bus at any
one time.
2)AHB slave: A bus slave responds to a read or write operation within a given address-space
range. The bus slave signals back to the active master the success, failure or waiting of the data
transfer.
3)AHB arbiter: The bus arbiter ensures that only one bus master at a time is allowed to initiate
data transfers. Even though the arbitration protocol is fixed, any arbitration algorithm, such as
highest priority or fair access can be implemented depending on the application requirements.
An AHB would include only one arbiter, although this would be trivial in single bus master
systems.
4)AHB decoder The AHB decoder is used to decode the address of each transfer and provide a
select signal for the slave that is involved in the transfer. A single centralized decoder is
required in all AHB implementations.

When to use AMBA AHB/ASB or APB

1)A full AHB or ASB interface is used for:
• bus masters • on-chip memory blocks • external memory interfaces • high-bandwidth
peripherals with FIFO interfaces • DMA slave peripherals.
2)A simple APB interface is recommended for:
• simple register-mapped slave devices • very low power interfaces where clocks cannot be
globally routed • grouping narrow-bus peripherals to avoid loading the system bus.

AHB:AHB signal prefixes H indicates an AHB signal.

For example, HREADY is the signal used to indicate that the data portion of an AHB transfer can
complete. It is active HIGH.
ASB:ASB signal prefixes A is a unidirectional signal between ASB bus masters and the arbiter B is
an ASB signal D is a unidirectional ASB decoder signal. For example, bnres is the ASB reset
signal. It is active LOW.

APB:APB signal prefixes P indicates an APB signal. For example, PCLK is the main clock used by
the APB.
How AHB is pipelined architecture?
APB protocol will required clock cycles to transfer bytes in total (4 bytes in each tx)
APB does not have concept of overlap
AHB protocl will requires 26 clock cycles to transfer 100 bytes in total(4 bytes in each tx)
1)1st clock:1st tx address phase (no data transferres yet)
2)2st clock:2st tx address phase+1st tx data phase
3)3st clock:3st tx address phase +2nd tx data phase
4)4st clock:4st tx address phase +3rd tx data phase
5)26st clock:No addres sphase + 25th tx data phase
Above concept of data phase,aligned with next address phase :pipelining
AXI also does same ,AXI in addition has ID

Explain 1k boundary concept in AHB?

The 1KB restriction you refer to is not a restriction on maximum slave size but a constraint
within AHB that says that a burst must not cross a 1KB boundary. The limit is designed to
prevent bursts crossing from one device to another and to give a reasonable trade-off between
burst size and efficiency. In practise, this means that a master must ALWAYS break a burst that
would otherwise cross the 1KB boundary and restart it with a non-sequential transfer, thus:
Address: 0x3f0 0x3f4 0x3f8 0x3fc 0x400 0x404 0x408
Transfer: NSEQ SEQ SEQ SEQ NSEQ SEQ SEQ

Why is a burst not allowed to cross a 1 kilobyte boundary?

If an AHB slave samples hselx at the start of a burst transaction, it knows it will be selected for
the duration of the burst. Also, a slave which is not selected at the start of a burst will know
that it will not become selected until a new burst is started.
1 kilobyte is the smallest area an AHB slave may occupy in the memory map. Therefore, if a
burst did cross a 1 kilobyte boundary, the access could start accessing one slave at the
beginning of the burst and then switch to another on the boundary, which must not happen for
the above reason.
The 1 kilobyte boundary has been chosen as it is large enough to allow reasonable length
bursts, but small enough that peripherals can be aligned to the 1 kilobyte boundary without
using up too much of the available memory map

Okay response is single cycle? but error/split/retry is two cycle, why?

or
Explain the concept of two cycle response?
During a transfer the slave shows the status using the response signals,
HRESP[1:0]:
OKAY The OKAY response is used to indicate that the transfer is progressing normally and when
HREADY goes HIGH this shows the transfer has completed successfully.
ERROR The ERROR response indicates that a transfer error has occurred and the transfer has
been unsuccessful.
RETRY and SPLIT Both the RETRY and SPLIT transfer responses indicate that the transfer cannot
complete immediately, but the bus master should continue to attempt the transfer.

Only an OKAY response can be given in a single cycle. The ERROR, SPLIT and RETRY responses
require at least two cycles. To complete with any of these responses then in the penultimate
(one before last) cycle the slave drives HRESP[1:0] to indicate ERROR, RETRY or SPLIT while
driving HREADY LOW to extend the transfer for an extra cycle. In the final cycle HREADY is
driven HIGH to end the transfer, while HRESP[1:0] remains driven to indicate ERROR, RETRY or
SPLIT.
If the slave needs more than two cycles to provide the ERROR, SPLIT or RETRY response then
additional wait states may be inserted at the start of the transfer. During this time the HREADY
signal will be LOW and the response must be set to OKAY.
The two-cycle response is required because of the pipelined nature of the bus. By the time a
slave starts to issue either an ERROR, SPLIT or RETRY response then the address for the
following transfer has already been broadcast onto the bus. The twocycle response allows
sufficient time for the master to cancel this address and drive HTRANS[1:0] to IDLE before the
start of the next transfer.
For the SPLIT and RETRY response the following transfer must be cancelled because it must not
take place before the current transfer has completed. However, for the ERROR response, where
the current transfer is not repeated, completion of the following transfer is optional.
What if the slave gets the address out of range?
default slave will be selected

How to connect multiple slaves to single master?

Explain the round robin arbitration concept?

Round robin arbitration is a scheduling scheme which gives to each requestor its share of using
a common resource for a limited time or data elements. The basic algorithm implies that once a
requestor has been serves he would “go around” to the end of the line and be the last to be
served again. The simplest form of round robin arbiter is based on assignment of a fixed time
slot per requestor; this can be implemented using a circular counter. Alternatively, the
weighted round robin arbiter is defined to allow a specific number X of data elements per each
requestor, in which case X data elements from each requestor would be processed before
moving to the next one. Round robin arbiters are typically used for arbitration for shared
resources, load balancing, queuing systems, and resource allocation. Any application requiring a
minimal fairness where none of the requestors is suffering from starvation is a valid application
for a round robin arbiter.
Explain the split-retry concept?

Split and retry

The SPLIT and RETRY responses provide a mechanism for slaves to release the bus when they
are unable to supply data for a transfer immediately. Both mechanisms allow the transfer to
finish on the bus and therefore allow a higher-priority master to get access to the bus.
The difference between SPLIT and RETRY is the way the arbiter allocates the bus after a SPLIT or
a RETRY has occurred:
• For RETRY the arbiter will continue to use the normal priority scheme and therefore only
masters having a higher priority will gain access to the bus.
• For a SPLIT transfer the arbiter will adjust the priority scheme so that any other master
requesting the bus will get access, even if it is a lower priority. In order for a SPLIT transfer to
complete the arbiter must be informed when the slave has the data available.
The SPLIT transfer requires extra complexity in both the slave and the arbiter, but has the
advantage that it completely frees the bus for use by other masters, whereas the RETRY case
will only allow higher priority masters onto the bus.
A bus master should treat SPLIT and RETRY in the same manner. It should continue to request
the bus and attempt the transfer until it has either completed successfully or been terminated
with an ERROR response.

What is the difference between HREADY and HREADY_OUT signals?

An AHB slave must have the HREADY signal as both an input and an output.
HREADY is required as an output from a slave so that the slave can extend the data phase of a
transfer.
HREADY is also required as an input so that the slave can determine when the previously
selected slave has completed its final transfer and the first data phase transfer for this slave is
about to commence.
Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT)
which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the
global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves
as the HREADY input.

What is the slave response for BUSY transfer?

Do all slaves have to support the BUSY transfer type?

Yes. All slaves must support the BUSY transfer type to ensure they are compatible with any bus
master.

Can a BUSY transfer occur at the end of a burst?

A BUSY transfer can only occur at the end of an undefined length burst (INCR). A BUSY transfer
cannot occur at the end of a fixed length burst (SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16,
WRAP16).

What is the difference between WRAP4 and INCR4?

or
How to terminate the INCR type transfer?
or
Explain wrapping calculation?
Let say HADDR=0x1004
 Hsize=1(2 bytes per beat)
Hwrite=1
Hburst=WRAP(8 beats)

Calculate boundary?
Boundary size =8*2=16 bytes will be transfered in total
Boundaries will be multiple of 16
O 0,16,32,48,64
O 0x1004=>which boundary does it fall it in?
-> Lower boundary:4096(0x1000)
->Upper boundary:4096+15(0x100f)
1st beat:0x1004,0x1005
2st beat:0x1006,0x1007
3st beat:0x1008,0x1009
4st beat:0x100a,0x100b
5st beat:0x100c,0x100d
6st beat:0x100e,0x100f
7st beat:0x1000,0x1001(INCR8:0x1010,0x1011)
8st beat:0x1002,0x1003(INCR8:0x1012,0x1013)

Explain Wrap Boundary Calculation in AHB ? WRAP4,WRAP8,WRAP16 ?

Answer
Wrap boundary depends on both Hsize and the No of beats(4 ,8,16)
"For wrapping bursts, if the start address of the transfer is not aligned to the total number of
bytes in the burst (size x beats) then the address of the transfers in the burst will wrap when
the boundary is reached"
Case1: Start Address is 0x4,Wrap4,Hsize is 2.
0000 0100 - beat1 - 0x4
0000 1000 - beat2 - 0x8
0000 1100 - beat3 - 0xc
0000 0000 - beat4 - 0x0
Here as Hsize is 2,it means 4 bytes are to be transfered. As it is Wrap4 no of beats are 4. Total
no of bytes is 16(beats*Hsize in bytes). Therefore 4bit alignment is to be done.
In beat3 the address is 0000 1100.Now as Hsize is 2,address shld be incremented by 4.
0000 1100
+0000 0100
---------------

0001 0000 ( it is crossing the address boundary(4 bits) )

So we are aligning it to 0000 0000.-beat4

Case2: Start Address is 0x4,Wrap4,Hsize is 1.

0000 0100 - beat1 - 0x4
0000 0110 - beat2 - 0x6
0000 0000 - beat3 - 0x0
0000 0010 - beat4 - 0x2
Here as Hsize is 1,it means 2bytes are to be transfered. As it is Wrap4 no of beats are 4. Total no
of bytes is 8(beats*Hsize in bytes).
Therefore 3 bit alignment is to be done. In beat2 the address is 0000 0110. Now as Hsize is
1,address shlould be incremented by 2.
0000 0110
+0000 0010
--------------
0000 1000 ( it is crossing the address boundary(3 bits).)

So we are aligning it to 0000 0000.-beat3

Case3: Start Address is 0x4,Wrap8,Hsize is 1.

0000 0100 - beat1 - 0x4

0000 0110 - beat2 - 0x6
0000 1000 - beat3 - 0x8
0000 1010 - beat4 - 0xa
0000 1100 - beat5 - 0xc
0000 1110 - beat6 - 0xe
0000 0000 - beat7 - 0x0
0000 0010 - beat8 - 0x2

Here as Hsize is 1,it means 2 bytes are to be transfered.

As it is Wrap8 no of beats are 8.
Total no of bytes is 16 (beats*Hsize in bytes).
Therefore 4bit alignment is to be done.
In beat6 the address is 0000 1110.Now as Hsize is 1,address shld be incremented by 2.

0000 1110
+0000 0010
---------------

0001 0000 ( it is crossing the address boundary(4 bits)).

So we are aligning it to 0000 0000.-beat7

Another Wrap Boundry Calculation :

1) convert hex addr to decimal - 0x38 = 56 (dec)
2) as its a word transfer (4 bytes) and WRAP 4 so 4 x 4 = 16
3) 56 / 16 = 3.5
4) take the whole number from previous calculation as 3
5) now 3 x 16 = 48 ( dec )
6) your roll over addr is 48 (dec ) = 0x30 (hex) !!!

So the address goes as 38 - 3c - 30 and 34

Exaplain Wrap Beat Calulation in AHB ?

Answer
Following Tasks will Give Information About Wrap Boundary Beat Location Calculation

//-------------------------------------------------------
// wrap4_beat_info()
//-------------------------------------------------------
Task wrap4_beat_info (logic [2:0] hburst,logic [31:0] haddr,logic [2:0] hsize);
If(hsize==3'b010 && hburst==`AHB_WRAP4 )
Begin
If(haddr[3:2]==2'b00) wrap4_boundry_location=0 ; // No Wrap
Else if(haddr[3:2]==2'b01) wrap4_boundry_location=3 ; // Wrap at 3rd Beat
Else if(haddr[3:2]==2'b10) wrap4_boundry_location=2 ; // Wrap at 2nd Beat
Else if(haddr[3:2]==2'b11) wrap4_boundry_location=1 ; // Wrap at 1st Beat
End
Endtask : wrap4_at_info
//--------------------------------------------------------
// wrap8_beat_info()
//--------------------------------------------------------
Task wrap8_beat_info (logic[2:0] hburst,logic[31:0] haddr,logic[2:0] hsize);
If(hsize==3'b010 && hburst==`AHB_WRAP8 )
Begin
If(haddr[5:3]==3'b000) wrap8_boundry_location=0 ;
Else if(haddr[5:3]==3'b001) wrap8_boundry_location=7 ;
Else if(haddr[5:3]==3'b010) wrap8_boundry_location=6 ;
Else if(haddr[5:3]==3'b011) wrap8_boundry_location=5 ;
Else if(haddr[5:3]==3'b100) wrap8_boundry_location=4 ;
Else if(haddr[5:3]==3'b101) wrap8_boundry_location=3 ;
Else if(haddr[5:3]==3'b110) wrap8_boundry_location=2 ;
Else if(haddr[5:3]==3'b110) wrap8_boundry_location=1 ;
End
Endtask : wrap8_beat_info
//---------------------------------------------------------
// wrap16_at_info()
//---------------------------------------------------------
Task wrap16_beat_info (logic[2:0] hburst, logic[31:0] haddr,logic[2:0] hsize);
If(hsize==3'b010 && hburst==`AHB_WRAP16 )
 Begin
If(haddr[7:4]==4'b0000) wrap8_boundry_location=0 ;
Else if(haddr[7:4]==4'b0001) wrap8_boundry_location=15 ;
Else if(haddr[7:4]==4'b0010) wrap8_boundry_location=14 ;
Else if(haddr[7:4]==4'b0011) wrap8_boundry_location=13 ;
Else if(haddr[7:4]==4'b0100) wrap8_boundry_location=12 ;
Else if(haddr[7:4]==4'b0101) wrap8_boundry_location=11 ;
Else if(haddr[7:4]==4'b0110) wrap8_boundry_location=10 ;
Else if(haddr[7:4]==4'b0111) wrap8_boundry_location=9 ;
Else if(haddr[7:4]==4'b1000) wrap8_boundry_location=8 ;
Else if(haddr[7:4]==4'b1001) wrap8_boundry_location=7 ;
Else if(haddr[7:4]==4'b1010) wrap8_boundry_location=6 ;
Else if(haddr[7:4]==4'b1011) wrap8_boundry_location=5 ;
Else if(haddr[7:4]==4'b1100) wrap8_boundry_location=4 ;
Else if(haddr[7:4]==4'b1101) wrap8_boundry_location=3 ;
Else if(haddr[7:4]==4'b1110) wrap8_boundry_location=2 ;
Else if(haddr[7:4]==4'b1111) wrap8_boundry_location=1 ;
End
Endtask : wrap16_beat_info

AXI TX:
AWADDR=32'h1000_1000
AWLEN = 6 (+1)
AWSIZE= 3 (2**3)
AWBURST=INCR
AWID=8

How many bytes will written in complete tx?

o number_of_tfrs * bytes_per_transfer = 7 * 8 = 56 (tx_size)

INCR:
56 bytes will written from 32'h1000_1000 to 32'h1000_1038

WRAP:
- wrap uses boundaries
- all boundaries lower range is multiple of tx_size (in this case 56)
- ex: boundaries
1st boundary : 0 - 55
2nd boundary : 56 - 111
3rd boundary : 112 - 167
4th boundary : 168 - 223

- where 32'h1000_1000 falls

 o 32'h1000_1000 / 56 => 4793563
o lower boundary : 'h1000_0FE8
o upper boundary : 'h1000_0FE8 + 'd55 = 'h1000_101F
o 32'h1000_1000 falls in to bounrary of ('h1000_0FE8 - 'h1000_101F)
WRAP transactions will start from 'h1000_1000 ---> we write till upper
bounary('h1000_101F) -> then we wrap back to the beining of
bounary(32'h1000_0FE8)...then writes till 32'h1000_0FFF)

-------
Simplified version of above example:
AWADDR = 'h102 (258)
AWLEN = 2 (+1)
AWSIZE= 2 (2**2) => 4 bytes per transfer
AWBURST=WRAP
TX_SIZE = (2+1) * (2^^2) = 12
Bounraries: (0..11), (12..23), (24..35)....
AWADDR falls in to => (252, 263) bounary

This tx will have totally 3 beats

in 1 st beat => 4 bytes are written to locations: 258, 259 (2 bytes will not be written) =>
unaligned transfer
o WDATA = 32'h1F2F3F4F (little endian : 4F=> 256, 3F=>257, 2F=>258, 1F=>259)
o slave will ignore: 3F, 4F (little endian => lower bytes go to lower address)
o 3F, 4F will be ignored by the slave
o slave will ignore: 3F, 4F
o WDATA = 32'h1F2F3F4F (big endian : 1F=> 256, 2F=>257, 3F=>258, 4F=>259)
o slave will ignore: 1F, 2F
in 2 nd beat => 4 bytes are written to locations: 260, 261, 262, 263
in 3 rd beat => 4 bytes are written to locations: 252, 253, 254, 255
o since we have done a unaligned tranaction, we end up not writing 2 location(256, 257)
-------------------------------
Simplified version of above example:
AWADDR = 'h100 (256)
AWLEN = 2 (+1)
AWSIZE= 2 (2**2)
AWBURST=WRAP
TX_SIZE = (2+1) * (2^^2) = 12
Bounraries: (0..11), (12..23), (24..35)....
AWADDR falls in to => (252, 263) bounary

This tx will have totally 3 beats

in 1 st beat => 4 bytes are written to locations: 256, 257, 258, 259 (4 bytes will be written) =>
aligned transfer
in 2 nd beat => 4 bytes are written to locations: 260, 261, 262, 263
in 3 rd beat => 4 bytes are written to locations: 252, 253, 254, 255
-----------------------
Simplified version of above example:
AWADDR = 'h100 (256)
AWLEN = 2 (+1)
AWSIZE= 2 (2**2)
AWBURST=INCR
TX_SIZE = (2+1) * (2^^2) = 12

This tx will have totally 3 beats

in 1 st beat => 4 bytes are written to locations: 256, 257, 258, 259 (4 bytes will be written) =>
aligned transfer
in 2 nd beat => 4 bytes are written to locations: 260, 261, 262, 263
in 3 rd beat => 4 bytes are written to locations: 264, 265, 266, 267
-----------------------

Aligned, unlaiged
Wrap, INCR
-------
FIXED:
- all bytes will be written to same adddress location
AWADDR = 100
-----
WRAP will be used by L1/L2 cache when they write/read data to/from main memory
INCR will be used by processor when accessing a main memory
FIXED will be used when a write/read happens to FIFO type storage
------
For a connectin where databus width is 32 bits => awsize can never be more than '2'
o if we use 3 => 2^^3 = 8 bytes/transfer = 64 bits
o it is posisble to do awsize=0 => 1 bytes /transfer
WSTRB=4'b1000 => wdata[31:24] is valid
WSTRB=4'b0100 => wdata[23:16] is valid
WSTRB=4'b0010 => wdata[15:8] is valid
WSTRB=4'b0001 => wdata[7:0] is valid
--------------
awsize=2
data bus width=64 bits
awlen=3 (4 transfers)
how many transferred(tx) = (3+1) * (2^^awsize) = 4*4 = 16 bytes in 4 beats
1st transfer => wstrb = 8'b0000_1111 (wdata[31:0] is valid)
2nd transfer => wstrb = 8'b1111_0000 (wdata[63:32] is valid) (wdata won't be same as 1st
transfer)
3rd transfer => wstrb = 8'b0000_1111 (wdata[31:0] is valid) (wdata won't be same as 2nd
transfer)
4th transfer => wstrb = 8'b1111_0000 (wdata[63:32] is valid) (wdata won't be same as 3rd
transfer)

wstrb = 10101100 (possible, but not used in real life applicaitons

------------------
awsize=1
data bus width=64 bits(wdata width)
awlen=5 (6 transfers)
12 bytes transfered in total 6 transfers
how many transferred(tx) = (3+1) * (2^^awsize) = 4*4 = 16 bytes in 4 beats
1st transfer => wstrb = 8'b0000_0011 (wdata[15:0] is valid)
2nd transfer => wstrb = 8'b0000_1100 (wdata[31:16] is valid) (wdata won't be same as 1st
transfer)
3rd transfer => wstrb = 8'b0011_0000 (wdata[47:32] is valid) (wdata won't be same as 2nd
transfer)
4th transfer => wstrb = 8'b1100_0000 (wdata[63:48] is valid) (wdata won't be same as 3rd
transfer)
5th transfer => wstrb = 8'b0000_0011 (wdata[15:0] is valid) (wdata won't be same as 3rd
transfer)
6th transfer => wstrb = 8'b0000_1100 (wdata[31:16] is valid) (wdata won't be same as 3rd
transfer)
wstrb = 10101100 (possible, but not used in real life applicaitons

What is difference between BURST and Beat?

How to calculate the size of the burst?

Total burst size in bytes is determined by HSIZE * HBURST.

Is HREADY is Input or output to/from the slave?

Both
Is early burst termination is done by Slave/Arbiter?
or
When can Early Burst Termination occur ?
Early burst termination
There are certain circumstances when a burst will not be allowed to complete and therefore it
is important that any slave design which makes use of the burst information can take the
correct course of action if the burst is terminated early. The slave can determine when a burst
has terminated early by monitoring the HTRANS signals and ensuring that after the start of the
burst every transfer is labelled as SEQUENTIAL or BUSY. If a NONSEQUENTIAL or IDLE transfer
occurs then this indicates that a new burst has started and therefore the previous one must
have been terminated.
If a bus master cannot complete a burst because it loses ownership of the bus then it must
rebuild the burst appropriately when it next gains access to the bus. For example, if a master
has only completed one beat of a four-beat burst then it must use an undefined-length burst to
perform the remaining three transfers
____

Normally the arbiter will not hand over the bus to a new master until the end of a burst of
transfers. However, if the arbiter determines that the burst must be terminated early in order
to prevent excessive access time to the bus then it may transfer the grant to another bus
master before a burst has completed.
If a master loses ownership of the bus in the middle of a burst it must re-arbitrate for the bus in
order to complete the burst. The master must ensure that the HBURST and HTRANS signals are
adapted to reflect the fact that it no longer has to perform a complete 4, 8 or 16-beat burst.

For example, if a master is only able to complete 3 transfers of an 8-beat burst, then when it
regains the bus it must use a legal burst encoding to complete the remaining 5 transfers. Any
legal combination can be used, so either a 5-beat undefined length burst or a 4-beat fixed
length burst followed by a single-beat undefined length burst would be acceptable.
__
or
Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a
master part way through a burst, or after a slave returns a non-OKAY response to any beat of a
burst.
Note however that a master cannot decide to terminate a defined length burst unless
prompted to do so by the Arbiter or Slave responses.
All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.

When should a master assert and deassert the HLOCK signal for a locked transfer?
or
Explain the LOCKED transfer?
Arbitration signal=>hlockx Locked transfers=>Master When HIGH this signal indicates that the
master requires locked access to the bus and no other master should be granted the bus until
this signal is LOW.
The HLOCK signal must be asserted at least one cycle before the start of the address phase of a
locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at the
start of the address phase.The master should deassert the HLOCK signal when the address
phase of the last transfer in the locked sequence has started.

when will the arbiter grant another master after a locked transfer?
The arbiter will always grant the master an extra transfer at the end of a locked sequence, so
the master is guaranteed to perform one transfer with the HMASTLOCK signal low at the end of
the locked sequence. This coincides with the data phase of the last transfer in the locked
sequence.
During this time the arbiter can change the HGRANT signals to a new bus master, but if the data
phase of the last locked transfer receives either a SPLIT or RETRY response then the arbiter will
drive the HGRANT signals to ensure that either the master performing the locked sequence
remains granted on the bus for a RETRY response, or the Dummy master is granted the bus for
the SPLIT response.

What is default Master?

or
What is the difference between a dummy bus master and a default bus master?
The term default bus master is used to describe the master that is granted when none of the
masters in the system are requesting access to the bus. Usually the bus master which is most
likely to request the bus is made the default master.
The dummy bus master is a master which only performs IDLE transfers. It is required in a
system so the arbiter can grant a master which is guaranteed not to perform any real transfers.
The two cases when the arbiter would
need to do this are when a SPLIT response is given to a locked transfer and when a SPLIT
response is given and all other masters have already been SPLIT.

What is little-endian and big-endian?

the [7:0] means we're using the little-endian convention - you start with 0 at the rightmost bit
to begin the vector, then move to the left. analogy others (Arabic) written right-to-left (little-
endian).
If we had done [0:7], we would be using the big-endian convention and moving from left to
right. analogy, think of some languages (English) that are written left-to-right (big-endian)
Endianness is a purely arbitrary way of deciding which way your data will "read," but does differ
between systems, so using the right endianness consistently is important.

How slave will detects the end of INCR type burst transfer?
______________________________________________________________________________
______________________________________________________________________________

Can HTRANS change whilst HREADY is low?

In general, an AHB master should not change control signals whilst HREADY is low. However it is
allowable to change HTRANS in the following conditions:
 HTRANS=IDLE
The AHB master is performing internal operations and has not yet committed to a bus
transfer. However during the AHB wait states (HREADY low) the master may determine
that a bus transfer is required and change HTRANS on the next cycle to NONSEQ.
 HTRANS=BUSY
HTRANS is being used to give the master time to complete internal operations, which
may be entirely independent of HREADY (i.e. Wait states on the AHB). Therefore
 HTRANS can change on the next cycle to any legal value, i.e. SEQ if the burst is to
continue, IDLE if the burst has completed, NONSEQ if a separate burst is to begin.
 HRESP=SPLIT/RETRY
As stated in the AHB specification, a master must assert IDLE on HTRANS during the
second cycle of the two-cycle SPLIT or RETRY slave response so HTRANS will change
value from the first cycle to the second cycle of the response.
 HRESP=ERROR
The master is permitted to change HTRANS in reaction to an ERROR response in the
same way as in reaction to a SPLIT/RETRY response and cancel any further beats in the
current burst (even if HBURST is indicating a defined-length burst). In this case HTRANS
changes to IDLE on the second cycle of the response. Alternatively, the master is
permitted to continue with the current transfers

What is the relationship between the HLOCK signal and the HMASTLOCK signal?
At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of
the master that is about to start driving the address bus and if HLOCK is asserted at this point
then HMASTLOCK will be asserted by the arbiter for the duration of the address phase of the
transfer.

Can a master deassert HLOCK during a burst?

The AHB specification requires that all address phase timed control signals (other than HADDR
and HTRANS) remain constant for the duration of a burst.
Although HLOCK is not an address phase timed signal, it does directly control the HMASTLOCK
signal which is address phase timed.
Therefore HLOCK must remain high for the duration of a burst, and can only be deasserted such
that the following HMASTLOCK signal changes after the final address phase of the burst.

Explain Lock Transfer in AHB ?

LOCK tells the arbiter to keep the current master granted, SPLIT tells the arbiter to grant
another master, so the only possible action the arbiter can take for these contradictory
requests is to grant the dummy master that must exist in any system with SPLIT capable slaves.

The dummy master will only perform IDLE transfers (i.e. no data transfers), so cannot corrupt
the LOCKed sequence that is ongoing.
When the original slave is able to complete the SPLIT transfer, it will signal this to the arbiter on
HSPLIT and the arbiter can then re-grant the original master, and the LOCKed sequence can
then continue.
However as the slave has an HMASTLOCK input telling it that the current transfer is part of a
LOCKed sequence, it should know that there is no system advantage in returning a SPLIT.
So yes, a slave can return a SPLIT response to a LOCKed transfer, and the arbiter must then
grant the dummy master, but the slave should use the HMASTLOCK input to see that a SPLIT
response is not useful at this time.
What are the different bursts used for?
Typically a master would use wrapping bursts for cache line fills where the master wants to
access the data it requires first and then it completes the burst to fetch the remaining data it
requires for the cache line fill. Incrementing bursts are used by masters, such as DMA
controllers, that are filling a buffer in memory which may not be aligned to a particular address
boundary.

What default state should be used for the HREADY and HRESP outputs from a slave?
It is recommended that the default value for HREADY is high and the default value for HRESP is
OKAY. This combination ensures that the slave will respond correctly to IDLE transfers to the
slave, even if the slave is in some form of power saving mode.

What is the recommended default value for HPROT?

Many bus masters will not be able to generate accurate protection information and for these
bus masters it is recommended that the HPROT encoding shows, Non-cacheable, Non-
bufferable, Privileged, Data Accesses which corresponds to HPROT[3:0] = 4'b0011.

When a master rebuilds a burst which has been terminated early are there any limitations on
how it rebuilds the burst?
The only limitation is that the master uses legal burst combinations to rebuild the burst. For
example, if a master was performing an 8 beat burst, but had only completed 3 transfers before
losing control of the bus, then the remaining 5 transfers could be performed either by using a 1
beat SINGLE burst followed by a 4 beat INCR4 burst, or it could be performed using a 5 beat
undefined length INCR burst.
For simplicity it is recommended that masters use INCR bursts to rebuild the remaining
transfers

Split/Retry: Can a SPLIT or RETRY response be given at any point during a burst?
Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any transfer during a burst.
The slave is not restricted to only giving these responses to the first transfer.
General: What default state should be used for the HREADY and HRESP outputs from a slave?
Applies to: AHB
It is recommended that the default value for HREADY is high and the default value for HRESP is
OKAY. This combination ensures that the slave will respond correctly to IDLE transfers to the
slave, even if the slave is in some form of power saving mode.

What is the state of the AHB signals during reset?

The specification states that during reset the bus signals should be at valid levels. This simply
means that the signals should be logic '0' or '1', but not Hi-Z. The actual logic levels driven are
left up to the designer. HTRANS is the only signal specified during reset, with a mandatory value
of IDLE.
It is important that HREADY is high during reset. If all slaves in the system drive HREADY high
during reset then this will ensure that this is the case. However, if slaves are used which do not
drive HREADY high during reset it should be ensured that a slave which does drive HREADY high
is selected at reset.

Split/Retry: Will a master always lose the bus after a SPLIT response?
Applies to: AHB
Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same cycle that it gives the
SPLIT response and therefore the master will always lose the bus.

How many masters can there be in an AHB system?

The AHB specification caters for up to 16 masters. However, allowing for a dummy bus master
means the maximum number of real bus masters is actually 15. By convention bus master
number 0 is allocated to the dummy bus master

Is a dummy master really necessary?

A dummy master is necessary in any system which has a slave that can give SPLIT transfer
responses. The dummy master is required so that something can be granted the bus if all the
other masters have received a SPLIT response.
No logic is required for the dummy master and it can be implemented by simply tying off the
inputs to the master address/control multiplexer for the dummy master position. The
requirements for a dummy master are that HTRANS is driven to IDLE, HLOCK is driven low, and
all other master outputs are driven to legal values.

What is split transfer in AHB?

When a master initiates a transaction and slave indicates to arbiter that at present it does not
have data then arbiter may give grant to any other master. But once data is ready with the
slave then slave can indicate to arbiter that it is ready with data. Then the arbiter would grant
transfer access to the old master for master to finish transaction.

Can an arbiter be designed to always allow bursts to complete?

A SPLIT, RETRY or ERROR response from a slave can always cause a burst to be early
terminated. This is outwith the control of the Arbiter and so must be supported.

Undefined length INCR bursts cannot have their end point predicted, so there is no efficient
way that an Arbiter design can allow the burst to complete before granting another master.
INCR bursts must be arbitrated on a cycle by cycle basis.

Defined length incrx and wrapx bursts can have their beats counted, and so allowed to
complete by the Arbiter. However because of the AHB arbitration synchronous timing, there is
no way to avoid possibly terminating a burst immediately after the first transfer of the burst has
been indicated.

The Arbiter only knows that a defined length burst is in progress by sampling the HBURST bus.
However the first point at which HBURST can be sampled is after the first clock cycle of the first
burst beat, by which time the Arbiter may already have decided to grant another master and
will have changed the HGRANT outputs accordingly. Only a combinatorial path from HBURST to
HGRANT would allow the burst to be detected in time to avoid early termination in this
scenario, but combinatorial paths in the AHB bus are not allowed. Ask ARM

Why is HADDR sometimes shown as an input to the arbiter?

The address bus, HADDR, is not required as an input to the arbiter but in some system designs it
may be useful to use the address bus to determine a good point to change over between bus
masters. For example, the arbiter could be designed to change bus ownership when a burst of
transfers reachesa quad word boundary.

When can the HGRANT signal change?

The HGRANT signal can change in any cycle and the following cases are possible:
* It is possible that the HGRANT signal may be asserted and then removed before the current
transfer completes. This is acceptable because the HGRANT signal is only sampled by masters
when HREADY is high.
* A master can be granted the bus without requesting it.
* The above point also means that it is possible to be granted the bus in the same cycle that it is
requested. This can occur if the master is coincidentally granted the bus in the same cycle that
it requests it.

When should a master deassert its HBUSREQ signal?

For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it
has started the address phase of the last transfer in the burst. This will mean that if the
penultimate transfer in the burst is zero wait state then the master may be granted the bus for
an additional transfer at the end of an undefined length burst.

For a defined length burst the master can deassert the HBUSREQ signal once the master has
been granted the bus for the first transfer. This can be done because the arbiter is able to count
the transfers in the burst and keep the master granted until the burst completes.

However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the
master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has
been completed.

If a master is currently granted the bus by default, how many cycles before starting an non-
IDLE transfer does it have to assert HBUSREQ?
None. It can start a non IDLE transfer immediately.

Can a master perform transfers other than IDLE when the bus was granted to it, but not
requested by the master?
Yes. A master can perform transfers other than IDLE when it had not requested the bus. Please
note that in this case it is still recommended that the master asserts its request signal so that
the arbiter does not change ownership of the bus to a lower priority master while the transfers
are in progress.
The specification recommends that only 16 wait states are used. What should you do if more
than 16 cycles are needed?
For some slaves it is acceptable to insert more than 16 wait states. For example, a serial boot
ROM which is only ever accessed at initial power up could insert a larger number of wait states
and it would not affect the calculation of the system performance and latency once system
power up has been completed.
For other slaves a number of options exist. A SPLIT or RETRY response could be used to indicate
that the slave is not yet able to perform the requested data transfer, or the slave could be
accessed either in response to interrupts or after polling a status register, in either case
indicating that the slave is now able to respond in an acceptable number of cycles.

Can an AHB master be connected directly to an AHB slave?

Any slave which does not use SPLIT responses can be connected directly to an AHB master. If
the slave does use SPLIT responses then a simplified version of the arbiter is also required.

If an AHB master is connected directly to an AHB slave it is important to ensure that the slave
drives HREADY high during reset and that the select signal HSEL for the slave is tied
permanently high.

What is the state of the AHB signals during reset?

The specification states that during reset the bus signals should be at valid levels. This simply
means that the signals should be logic '0' or '1', but not Hi-Z. The actual logic levels driven are
left up to the designer. HTRANS is the only signal specified during reset, with a mandatory value
of IDLE.
It is important that HREADY is high during reset. If all slaves in the system drive HREADY high
during reset then this will ensure that this is the case. However, if slaves are used which do not
drive HREADY high during reset it should be ensured that a slave which does drive HREADY high
is selected at reset.

What is a default slave?

If the memory map of a system does not define the full 4 gigabyte address space then a default
slave is required, which is selected when an access is attempted to the empty areas of the
memory map. The default slave should use an OKAY response for IDLE/BUSY transfers and an
ERROR response sequence for NONSEQ/SEQ transfers.

Is a default slave really necessary?

If the entire 4 gigabyte address space is defined then a default slave is not required. If,
however, there are undefined areas in the memory map thenit is important to ensure that a
spurious access to a non-existent address location will not lock up the system. The functionality
of the default
slave is extremely simple and it will often make sense to implement this within the decoder.

Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?
Yes, the control signals must remain constant throughout the duration of a burst.
What default state should be used for the HREADY and HRESP outputs from a slave?
It is recommended that the default value for HREADY is high and the default value for HRESP is
OKAY. This combination ensures that the slave willrespond correctly to IDLE transfers to the
slave, even if the slave is in some form of power saving mode.

Can a master change the address/control signals during a waited transfer?

Yes. If the address/control signals are indicating an IDLE transfer then the master can change to
a real transfer (NONSEQ) when HREADY is low.However, if a master is indicating a real transfer
(NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a
SPLIT,RETRY or ERROR response.

What is the recommended default value for HPROT?

Many bus masters will not be able to generate accurate protection information and for these
bus masters it is recommended that the HPROT encoding shows, Non-cacheable, Non-
bufferable, Privileged, Data Accesses which corresponds to HPROT[3:0] = 4'b0011.

What system support is required if a slave can be powered down or have its clock stopped?
If a slave access is attempted while that slave is in a power down state or has had its clock
stopped, you must ensure that an access will cause the power/clock to be restored, or else
configure the AHB decoder up to redirect any such accesses to the dummy slave so that the
system does not hang forever when an access to the device is made when it is disabled.

Redirecting the access in this way will ensure that random "IDLE" addresses are treated with
the HREADY high and HRESP=OKAY default response, but real accesses (NONSEQ or SEQ) will be
detected with an ERROR response.

Does the address have to be aligned, even for IDLE transfers?

Yes. The address should be aligned according to the transfer size (HSIZE) even for IDLE
transfers. This will prevent spurious warnings from bus monitors used during simulation.

Is it legal for a master to change HADDR when a transfer is extended?

If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY transfer then it cannot
change the address during an extended transfer (when HREADY is low) unless it receives an
ERROR, RETRY or SPLIT response.
If the master is indicating that it wants to do an IDLE transfer then it may change the address.

What sequences of transfers types (HTRANS) can occur on the bus?

The following examples show some of the sequences of HTRANS that can occur on the bus:
A normal burst of four transfers followed by an IDLE.
N-S-S-S-I
A normal burst of four transfers which includes BUSY transfers.
N-S-B-S-B-S-I
A burst of four transfers followed by another burst.
N-S-S-S-N-S-S-S-I
A single transfer followed by a burst of four transfers.
N-N-S-S-S-I
A single transfer followed by an IDLE
N-I
An undefined length burst which concludes with a BUSY transfer.
N-B-S-B-S-B-I
An undefined length burst which concludes with a BUSY transfer and is followed
immediately by another burst.
N-B-S-B-S-B-N-S

How should AHB to APB bridges handle accesses that are not 32-bits?
The bridge should simply pass the entire 32-bit data bus through the bridge. Please note that
when transfers less than 32-bits are performed to an APB slave it is important to ensure that
the peripheral is located on the appropriate bits of the APB data bus.

What value should be used for HTRANS when an AHB master gets a RETRY response from a
slave in the middle of burst?
Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it may also be
necessary to adjust the HBURST information (usually just to indicate INCR).

What address should be on the bus during the IDLE cycle after a SPLIT or RETRY?
It does not matter what address is driven onto the bus during this cycle.The slave selected by
the driven address should not take any action and must respond with a zero wait state OKAY
response.
In many cases it will be simpler for the master to leave the address unaltered during this cycle,
so that it remains at the address of the next transfer that the master wishes to perform and
only in the following cycle does the master return the address to that of the transfer that must
be
repeated because of the SPLIT or RETRY response.
In some designs it may be possible for the master to return the address to that required to
repeat the previous transfer during the IDLE cycle and this behaviour is also perfectly
acceptable.

Do all masters have to support SPLIT and RETRY?

Yes. All masters must support SPLIT and RETRY responses to ensure they are compatible with
any bus slave. A master will handle both SPLIT and RETRY responses in an identical manner.

Can a SPLIT or RETRY response be given at any point during a burst?

Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any transfer during a burst.
The slave is not restricted to only giving these responses to the first transfer.

Will a master always lose the bus after a SPLIT response?

Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same cycle that it gives the
SPLIT response and therefore the master will always lose the bus.
Can a slave assert hsplitx in the same cycle that it gives a SPLIT response?
No. The specification requires that hsplitx can only be asserted after the slave has given a SPLIT
response.

Do all slaves have to support the SPLIT and RETRY responses?

No. A slave is only required to support the response types that it needs to use. For example, a
simple on-chip memory block which can respond to all transfers in just a few wait states does
not need to use either the SPLIT or RETRY responses.

Can a slave use both SPLIT and RETRY responses?

Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT response should be
used by any slave that may be accessed by many different masters at the same time. The RETRY
response is intended to be used by peripherals that are only accessed by one bus master.

What is the difference between SPLIT and RETRY responses?

Both the Split and Retry responses are used by slaves which require a large number of cycles to
complete a transfer. These responses allow a data phase transfer to appear completed to avoid
stalling the bus, but at the same time indicate that the transfer should be re-attempted when
the master is next granted the bus.
The difference between them is that a SPLIT response tells the Arbiter to give priority to all
other masters until the SPLIT transfer can be completed (effectively ignoring all further requests
from this master until the SPLIT slave indicates it can complete the SPLIT transfer), whereas the
RETRY response only tells the Arbiter to give priority to higher priority masters.

A SPLIT response is more complicated to implement than a RETRY, but has the advantage that it
allows the maximum efficiency to be made of the bus bandwidth.

The master behaviour is identical to both SPLIT and RETRY responses, the master has to cancel
the next access and re-attempt the current failedaccess.

How should AHB to APB bridges handle accesses that are not 32-bits?
The bridge should simply pass the entire 32-bit data bus through the bridge. Please note that
when transfers less than 32-bits are performed to an APB slave it is important to ensure that
the peripheral is located on the appropriate bits of the APB data bus

What is the concept of global hready?

When Core act as Slave:
1. Slave should check only t_hready_glb during the address phase. (No need to consider
t_hready in address phase).
2. Slave should check only t_hready during data phase. (No Need to consider t_hready_glb in
data phase).

When Core act as Master:

Master should consider only m_hready (currently addressed target's hready) in both address
and data phase. No need to consider t_hready_glb in both address and data phase.

Explain the concept of Retry and Split in AHB?

Lets say the master is doing 4beat transaction. For the first data phase, the slave sends OK
response, and for the second data phase the slave sends split/retry response. For both retry
and split, the master has to do the new transaction for 3Dwords, because only first Dword sent
successfully in first data phase. So here the burst size will change. Because the master initiated
with 4beat burst and because of split/retry response, only one DWORD is sent successfully and
the master has to do the remaining 3 Dwords in Single transfers (new transactions). So it is
recommended for the slave to send split or retry only during first data phase, so that the
master can retry the entire 4beat transaction again (instead of changing the burst size for the
remaining transactions).

The main difference between split and retry is,

For retry, the arbiter will send the grant whenever the master request for a bus, whereas
For split, the arbiter will assert the grant only when slave sends hsplit to the master.

Which is the only active low signal in AHB?

Hresetn is the only active low signal in AHB.

Does AHB supports address bus more than 32 bits?

No, AHB supports only 32 bit address bus.

What is maximum data width of an AHB bus?

AHB supports data width from 8 bits to 1024 bits.

How many Master/Slave can be connected?

We can connect maximum of 16 Master/Slave.
Can the bus master cancel a transfer it has started?
No provision is made within the AHB specification for a bus master to cancel a transfer once it
has commenced.

How many wait states a slave insert?

It is recommended, but not mandatory, that slaves do not insert more than 16 wait states to
prevent any single access locking bus for a large number of clock cycles.

AHB vs AXI
AHB is Advanced High-performance Bus and AXI is Advanced extensible Interface. Both the ABH
and AXI are Bus masters, which are really different in many aspects.
When the Advanced High-performance Bus is a single channel Bus, the Advanced extensible
Interface is a multi- channel Bus. The AHB is also a shared Bus whereas the AXI is a read/write
optimized bus.
In AHB, each of the bus masters will connect to a single-channel shared bus. On the other hand,
the bus master in AXI will connect to a Read data channel, Read address channel, Write data
channel, Write address channel and Write response channel.
Another difference that is noticed is that the Bus latencies in AHB start lower than the AXI. The
AHB starts at 16 Byte transactions where as the AXI starts at 64 Byte transactions. It can also be
seen that the AHB Bus utilization is higher than AXI utilization. Moreover, The Advanced
extensible Interface uses around 50 per cent more power, which means that AHB has an edge
over it.
Advanced extensible Interface is the third generation of Advanced Microprocessor Bus
Architecture interface. Some of the features of AXI incude separate address/control and data
phases, burst based transactions with start address issued, support for unaligned data transfers
using byte strobes, easy addition of register stages to provide timing closure and issuing of
multiple outstanding addresses. The AXI, which suits high speed sub-micrometer interconnect,
mainly targets high clock frequency system designs and high performance.
Some of the features of Advanced High-performance Bus includes single edge clock protocol,
several bus masters, split transactions, pipelined operations, burst transfers, non-tristate
implementation and large bus-widths.
Summary
1. AHB is Advanced High-performance Bus and AXI is Advanced extensible Interface.
2. When the Advanced High-performance Bus is a single channel Bus, the Advanced extensible
Interface is a multi- channel Bus.
3. In AHB, each of the bus masters will connect to a single-channel shared bus. On the other
hand, the bus master in AXI will connect to a Read data channel, Read address channel, Write
data channel, Write address channel and Write response channel.
4. The AHB is also a shared Bus whereas the AXI is a read/write optimized bus.
5. Bus latencies in AHB starts lower than the AXI.
6. The Advanced extensible Interface uses around 50 per cent more power, which means that
AHB has an edge over it.
7. AHB Bus utilization is higher than AXI utilization
 What is the wrap burst transaction in AXI? How to calculate start & wrap boundary address ?
Ans. 1.A wrapping burst is similar to an incrementing burst, except that the address wraps
around to a lower address if an upper address limit is reached. The following restrictions apply
to wrapping bursts:
 The start address must be aligned to the size of each transfer
 The length of the burst must be 2, 4, 8, or 16 transfers.
2.wrap boundary is decided by total bytes in the burst. Lets take the following example.
Suppose a transaction with address 8(in decimal) has burst of length 4 with 32-bit bus.then
access
will be like 8->12->0->4. Address 16 is the wrap boundary in this case.

Must a read after a write to the same address return the newly written data?
Scenario
When there is an AHB write followed by a read from the same address, should the read return
the old or the new data when the read address phase is in same cycle of the write data phase?
Answer
The answer to this question is dependent on the design of the slave.
A simple slave will not be buffering any data, so the returned read data will be the latest. A
more complex slave could implement buffering for write data (if allowed by HPROT[2]) and so it
could "snoop" the write buffer contents before returning read data, or it might just return the
previously stored data regardless of what might be buffered.
In conclusion, all the AHB specification requires is that data is returned.

What system support is required if a slave can be powered down or have its clock stopped?
If a slave access is attempted while that slave is in a power down state or has had its clock
stopped, you must ensure that an access will cause the power/clock to be restored, or else
configure the AHB decoder up to redirect any such accesses to the dummy slave so that the
system does not hang forever when an access to the device is made when it is disabled.
Redirecting the access in this way will ensure that random "IDLE" addresses are treated with
the HREADY high and HRESP=OKAY default response, but real accesses (NONSEQ or SEQ) will be
detected with an ERROR response.

Can a master change the address/control signals during a waited transfer?

Yes. If the address/control signals are indicating an IDLE transfer then the master can change to
a real transfer (NONSEQ) when HREADY is low.
However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this
during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

Can an AHB master be connected directly to an AHB slave?

Any slave which does not use SPLIT responses can be connected directly to an AHB master. If
the slave does use SPLIT responses then a simplified version of the arbiter is also required.If an
AHB master is connected directly to an AHB slave it is important to ensure that the slave drives
HREADY high during reset and that the select signal HSEL for the slave is tied permanently high.
Does the address have to be aligned, even for IDLE transfers?
Yes. The address should be aligned according to the transfer size (HSIZE) even for IDLE transfers
.This will prevent spurious warnings from bus monitors used during simulation.

How many masters can there be in an AHB system?

The AHB specification caters for up to 16 masters. However, allowing for a dummy bus master
means the maximum number of real bus masters is actually 15. By convention bus master
number 0 is allocated to the dummy bus master.

Is a default slave really necessary?

If the entire 4 gigabyte address space is defined then a default slave is not required. If, however
, there are undefined areas in the memory map then it is important to ensure that a spurious
access to a non-existent address location will not lock up the system. The functionality of the
default slave is extremely simple and it will often make sense to implement this within the
decoder.

Is a dummy master really necessary?

A dummy master is necessary in any system which has a slave that can give SPLIT transfer
responses. The dummy master is required so that something can be granted the bus if all the
other masters have received a SPLIT response.
No logic is required for the dummy master and it can be implemented by simply tying off the
inputs to the master address/control multiplexer for the dummy master position. The
requirements for a dummy master are that HTRANS is driven to IDLE, HLOCK is driven low, and
all other master outputs are driven to legal values.

Is it legal for a master to change HADDR when a transfer is extended?

If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY transfer then it cannot
change the address during an extended transfer (when HREADY is low) unless it receives an
ERROR, RETRY or SPLIT response. If the master is indicating that it wants to do an IDLE transfer
then it may change the address.

Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?
Yes, the control signals must remain constant throughout the duration of a burst.

The specification recommends that only 16 wait states are used. What should you do if more
than 16 cycles are needed?
For some slaves it is acceptable to insert more than 16 wait states. For example, a serial boot
ROM which is only ever accessed at initial power up could insert a larger number of wait states
and it would not affect the calculation of the system performance and latency once system
power up has been completed.
For other slaves a number of options exist. A SPLIT or RETRY response could be used to indicate
that the slave is not yet able to perform the requested data transfer, or the slave could be
accessed either in response to interrupts or after polling a status register, in either case
indicating that the slave is now able to respond in an acceptable number of cycles.

What is the state of the AHB signals during reset?

The specification states that during reset the bus signals should be at valid levels. This simply
means that the signals should be logic '0' or '1', but not Hi-Z. The actual logic levels driven are
left up to the designer. HTRANS is the only signal specified during reset, with a mandatory value
of IDLE.
It is important that HREADY is high during reset. If all slaves in the system drive HREADY high
during reset then this will ensure that this is the case. However, if slaves are used which do not
drive HREADY high during reset it should be ensured that a slave which does drive HREADY high
is selected at reset.

When a master rebuilds a burst which has been terminated early are there any limitations on
how it rebuilds the burst?
The only limitation is that the master uses legal burst combinations to rebuild the burst. For
example, if a master was performing an 8 beat burst, but had only completed 3 transfers before
losing control of the bus, then the remaining 5 transfers could be performed either by using a 1
beat SINGLE burst followed by a 4 beat INCR4 burst, or it could be performed using a 5 beat
undefined length INCR burst.
For simplicity it is recommended that masters use INCR bursts to rebuild the remaining
transfers.

How does the AHB handle locked splits?

When a transfer is SPLIT the arbiter degrants and removes the SPLIT master out of the
arbitration until the slave indicates that the transfer can complete. When an access is locked
the access cannot be interrupted by an access from another master.
The only possible way that an AHB system can handle these two requirements simultaneously is
to grant a "dummy master" when the locked access is SPLIT. The dummy master will only
perform IDLE transactions, which are allowable during a locked transfer. To grant any other
master would violate the LOCK protocol, for the arbiter to ignore the SPLIT would violate the
SPLIT protocol - the dummy master is the only option.
The dummy master is also used when all masters are have received a SPLIT response (the
dummy master cannot receive a SPLIT response).
It is recommended that the designer of the split-capable slave(s) makes sure that the slave
monitors its HMASTLOCK input so that it doesn't return a SPLIT on a locked transfer, as this
serves no purpose.

How many clock cycles should the reset signal in an AMBA system be asserted for?
It is recommended that master and slave components should clearly state if they have a reset
requirement greater than 1 or 2 cycles. It is also recommended that the system design should
hold reset asserted for at least 16 cycles, unless it is known that a master or slave component
has a longer reset requirement.
Is it legal for an AHB wrapping burst to be aligned with respect to the total number bytes in
the burst, such that it does not wrap?
Yes, this behavior is compliant with the AHB protocol.
Consider a four-beat wrapping burst of word (4-byte) transfers (which will wrap at 16-byte
boundaries).
If the start address of the transfer is 0x30, then the burst consists of four transfers to addresses
0x30, 0x34, 0x38, and 0x3c.
Again, although HBURST is set to WRAP4, the burst will not actually wrap, which is allowed.

When should a master deassert its HBUSREQ signal?

For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it
has started the address phase of the last transfer in the burst. This will mean that if the
penultimate transfer in the burst is zero wait state then the master may be granted the bus for
an additional transfer at the end of an undefined length burst.
For a defined length burst the master can deassert the HBUSREQ signal once the master has
been granted the bus for the first transfer. This can be done because the arbiter is able to count
the transfers in the burst and keep the master granted until the burst completes.
However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the
master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has
been completed.

Can a master perform transfers other than IDLE when the bus was granted to it, but not
requested by the master?
Yes. A master can perform transfers other than IDLE when it had not requested the bus. Please
note that in this case it is still recommended that the master asserts its request signal so that
the arbiter does not change ownership of the bus to a lower priority master while the transfers
are in progress.

If a master is currently granted the bus by default, how many cycles before starting an non-
IDLE transfer does it have to assert HBUSREQ?
None. It can start a non IDLE transfer immediately.

When can the HGRANT signal change?

The HGRANT signal can change in any cycle and the following cases are possible:
 It is possible that the HGRANT signal may be asserted and then removed before the
current transfer completes. This is acceptable because the HGRANT signal is only
sampled by masters when HREADY is high.
 A master can be granted the bus without requesting it.
 The above point also means that it is possible to be granted the bus in the same cycle
that it is requested. This can occur if the master is coincidentally granted the bus in the
same cycle that it requests it.

Why is HADDR sometimes shown as an input to the arbiter?

The address bus, HADDR, is not required as an input to the arbiter but in some system designs it
may be useful to use the address bus to determine a good point to change over between bus
masters. For example, the arbiter could be designed to change bus ownership when a burst of
transfers reaches a quad word boundary.

Can an arbiter be designed to always allow bursts to complete?

A SPLIT, RETRY or ERROR response from a slave can always cause a burst to be early terminated
.This is outwith the control of the Arbiter and so must be supported. Undefined length INCR
bursts cannot have their end point predicted, so there is no efficient way that an Arbiter design
can allow the burst to complete before granting another master. INCR bursts must be
arbitrated on a cycle by cycle basis. Defined length incrx and wrapx bursts can have their beats
counted, and so allowed to complete by the Arbiter. However because of the AHB arbitration
synchronous timing, there is no way to avoid possibly terminating a burst immediately after the
first transfer of the burst has been indicated. The Arbiter only knows that a defined length burst
is in progress by sampling the HBURST bus. However the first point at which HBURST can be
sampled is after the first clock cycle of the first burst beat, by which time the Arbiter may
already have decided to grant another master and will have changed the HGRANT outputs
accordingly. Only a combinatorial path from HBURST to HGRANT would allow the burst to be
detected in time to avoid early termination in this scenario, but combinatorial paths in the AHB
bus are not allowed.

What's the difference between retry and split in AHB?

The SPLIT and RETRY responses provide a mechanism for slaves to release the bus when they
are unable to supply data for a transfer immediately. Both mechanisms allow the transfer to
finish on the bus and therefore allow a higher-priority master to get access to the bus.

When a master initiates a transaction on the AMBA bus, if the target detects that the transfer
will take a large number of cycles to perform, it can issue a SPLIT signal. What happens now is
that the arbiter can grant the bus to other masters even before the SPLIT transaction is
complete. The master to which the SPLIT has been issued has to then wait and complete the
entire transaction.

During the address phase of a transfer the arbiter generates a tag, or bus master number, on
HMASTER[3:0] which identifies the master that is performing the transfer. Any slave issuing a
SPLIT response must be capable of indicating that it can complete the transfer, and it does this
by making a note of the master number on the HMASTER[3:0] signals.

Later, when the slave can complete the transfer, it asserts the appropriate bit, according to the
master number, on the hsplitx[15:0] signals from the slave to the arbiter. The arbiter then uses
this information to unmask the request signal from the master and in due course the master
will be granted access to the bus to retry the transfer. The arbiter samples the hsplitx bus every
cycle and therefore the slave only needs to assert the appropriate bit for a single cycle in order
for the arbiter to recognize it.
The basic stages of a SPLIT transaction are:
1. The master starts the transfer in an identical way to any other transfer and
issues address and control information
2. If the slave is able to provide data immediately it may do so. If the slave
decides that it may take a number of cycles to obtain the data it gives a SPLIT
transfer response. During every transfer the arbiter broadcasts a number, or
tag, showing which master is using the bus. The slave must record this number,
to use it to restart the transfer at a later time.
3. The arbiter grants other masters use of the bus and the action of the SPLIT
response allows bus master handover to occur. If all other masters have also
received a SPLIT response then the default master is granted.
4. When the slave is ready to complete the transfer it asserts the appropriate bit of
the hsplitx bus to the arbiter to indicate which master should be regranted
access to the bus.
5. The arbiter observes the hsplitx signals on every cycle, and when any bit of
hsplitx is asserted the arbiter restores the priority of the appropriate master.
6. Eventually the arbiter will grant the master so it can re-attempt the transfer. This
may not occur immediately if a higher priority master is using the bus.
7. When the transfer eventually takes place the slave finishes with an OKAY
transfer response.

For a SPLIT transfer the arbiter will adjust the priority scheme so that any other
master requesting the bus will get access, even if it is a lower priority. In order
for a SPLIT transfer to complete the arbiter must be informed when the slave has
the data available.

For RETRY the arbiter will continue to use the normal priority scheme and
therefore only masters having a higher priority will gain access to the bus.
What value should be used for HTRANS when an AHB master gets a RETRY
Response from a slave in the middle of burst?

Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it

May also be necessary to adjust the HBURST information (usually just to
Indicate INCR).

What address should be on the bus during the IDLE cycle after a SPLIT or RETRY?
It does not matter what address is driven onto the bus during this cycle. The slave selected by
the driven address should not take any action and Must respond with a zero wait state OKAY
response.

In many cases it will be simpler for the master to leave the address Unaltered during this cycle,
so that it remains at the address of the next Transfer that the master wishes to perform and
only in the following cycle Does the master return the address to that of the transfer that must
be Repeated because of the SPLIT or RETRY response.
In some designs it may be possible for the master to return the address to That required to
repeat the previous transfer during the IDLE cycle and This behaviour is also perfectly
acceptable.

Do all masters have to support SPLIT and RETRY?

Yes. All masters must support SPLIT and RETRY responses to ensure they are Compatible with
any bus slave. A master will handle both SPLIT and RETRY Responses in an identical manner.
Note that if the system is based on AHB-Lite, SPLIT and RETRY responses are not supported.
AHB-lite is a single master solution, so SPLIT and RETRY responses would have no meaning.

Can a SPLIT or RETRY response be given at any point during a burst?

Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any Transfer during a burst.
The slave is not restricted to only giving these Responses to the first transfer.

Will a master always lose the bus after a SPLIT response?

Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same Cycle that it gives the
SPLIT response and therefore the master will always Lose the bus.

Can a slave assert hsplitx in the same cycle that it gives a SPLIT Response?
No. The specification requires that hsplitx can only be asserted after the Slave has given a SPLIT
response.

Do all slaves have to support the SPLIT and RETRY responses?

No. A slave is only required to support the response types that it needs to Use. For example, a
simple on-chip memory block which can respond to all Transfers in just a few wait states does
not need to use either the SPLIT Or RETRY responses.

Can a slave use both SPLIT and RETRY responses?

Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT Response should
be used by any slave that may be accessed by many different Masters at the same time. The
RETRY response is intended to be used by Peripherals that are only accessed by one bus master.

What is the diffrence between split and retry ?

Both the Split and Retry responses are used by slaves which require a large number of cycles to
complete a transfer. These responses allow a data phase transfer to appear completed to avoid
stalling the bus, but at the same time indicate that the transfer should be re-attempted when
the master is next granted the bus.

The difference between them is that a SPLIT response tells the Arbiter to give priority to all
other masters until the SPLIT transfer can be completed (effectively ignoring all further requests
from this master until the SPLIT slave indicates it can complete the SPLIT transfer), whereas the
RETRY response only tells the Arbiter to give priority to higher priority masters.
A SPLIT response is more complicated to implement than a RETRY, but has the advantage that it
allows the maximum efficiency to be made of the bus bandwidth.

The master behaviour is identical to both SPLIT and RETRY responses, the master has to cancel
the next access and re-attempt the current failed access.

Do all slaves have to support the SPLIT and RETRY responses ?

No. A slave is only required to support the response types that it needs to use. For example, a
simple on-chip memory block which can respond to all transfers in just a few wait states does
not need to use either the SPLIT or RETRY responses.

What address should be on the bus during the IDLE cycle after a SPLIT or RETRY ?
It does not matter what address is driven onto the bus during this cycle. The slave selected by
the driven address should not take any action and must respond with a zero wait state OKAY
response.

In many cases it will be simpler for the master to leave the address unaltered during this cycle,
so that it remains at the address of the next transfer that the master wishes to perform and
only in the following cycle does the master return the address to that of the transfer that must
be repeated because of the SPLIT or RETRY response.

In some designs it may be possible for the master to return the address to that required to
repeat the previous transfer during the IDLE cycle and this behaviour is also perfectly
acceptable.

What value should be used for HTRANS when an AHB master gets a RETRY response from a
slave in the middle of burst ?
Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it may also be
necessary to adjust the HBURST information (usually just to indicate INCR).