Design_test
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Setting standards in VLSI Design
Table of Contents
Part- 1: Digital ....................................................................................................................................... 3
Part- 2: Verilog...................................................................................................................................... 4
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Setting standards in VLSI Design
Part- 1: Digital(25 Maks)
1. Figure shows a diagram for an automobile alarm circuit used to detect certain
desirable conditions. The three switches are used toindicate the status of the door by
the driver’s seat, the ignition, and the headlights, respectively. Design the logic circuit
with these three switches as inputs so that the alarm will be activated whenever either
of the following conditions exists:
■ The headlights are on while the ignition is off.
■ The door is open while the ignition is on.
(8M)
2. Determine the input conditions needed to produce x _ 1 in Figure
(5M)
3. Design a sequential circuit to detect the following sequences in overlapping manner.
a) 101 when sel is 00
b) 111 when sel is 01
c) 010 when sel is 10
d) 011 when sel is 11
Note: you need not draw the FSM (12M).
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VLSI Training Services
Setting standards in VLSI Design
Part- 2: Verilog(25 marks)
1. Draw the RTL schematic for the below RTL snippet: (5M)
2. Write RTL code to design a Toggle flip-flop with the following features:
Inputs: clock(posedge triggered), reset(active high synchronous), t_in(toggle input)
Outputs: q_out (5M)
3. Give 2 differences between Regular & Intra-delays with examples. (5M)
4. A dual port synchronous Static RAM of size (64x16). “clock” is posedge triggerred,
“clr” is active high asynchronous clear ,address pointers are input ports. The memory
doesn’t support simultaneous read and write operation. An error output signal is
asserted if read & write is attempted together.
[A] Draw the block diagram. (2M)
[B] Write the synthesizable RTL code for the design. (4M)
[C] Write the TB and verify 4 random write operation. (4M)
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