Printed Page: 1 of 2

Subject Code: KOE049

0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM IV) THEORY EXAMINATION 2021-22
DIGITAL ELECTRONICS

Time: 3 Hours Total Marks: 100

Note: Attempt all Sections. If you require any missing data, then choose suitably.

SECTION A
1. Attempt all questions in brief. 2x10 = 20
Qno Questions CO
(a) Define the term binary codes with an example. 1
(b) Differentiate between SOP & POS form. 1
(c) Define the term combinational logic with an example. 2
(d) Discuss universal gates. 2
(e) Explain the term Latch. 3
(f) Explain the term registers. 3
(g) Define Asynchronous circuits. 4
(h) Discuss hazards. 4
(i) Discuss logic family and its use. 5
(j) What do you mean by a memory? 5

SECTION B
2. Attempt any three of the following: 10x3 = 30
Qno Questions CO
(a) Explain the implementation of an X-OR gate with NAND 1
implementation.
(b) Illustrate the working of Serial and parallel adders and differentiate the 2
operations.
(c) Explain the working of J-K Flip-Flop. 3
(d) Define the state reduction steps for a machine. 4
(e) Discuss different types of RAM memory cell. 5

SECTION C
3. Attempt any one part of the following: 10x1 = 10
Qno Questions CO
(a) Minimize the following Boolean function using K Map 1
𝒇 𝑨, 𝑩, 𝑪, 𝑫 𝒎 𝟎, 𝟏, 𝟒, 𝟖, 𝟗, 𝟏𝟎 𝒅 𝟐, 𝟏𝟏
(b) Explain different steps associated to Quine Mc Culsy (Tabular 1
Method) of minimizing Boolean Functions.

4. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Design a 4-bit magnitude comparator. 2
(b) Design a full adder and full subtractor using NAND gates only. 2

5. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Describe the Design of J-K FF using T FF. 3
(b) Describe the operations and applications of a Serial-in Parallel-out 3
Shift Register with a neat diagram.
 Printed Page: 2 of 2
Subject Code: KOE049
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM IV) THEORY EXAMINATION 2021-22
DIGITAL ELECTRONICS

6. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Design a sequential circuit with two flip flops A & B and one input x. 4
when x = 0, the state of the circuit remains the same and when x = 1
the circuit passes through the state transitions from 00 to 01 to 11 to 10
back to 00 and repeat.
(b) A sequential circuit has two J K flip flops A & B, two inputs X & Y, 4
and one output Z. The equations defining this system are as following:
𝑱𝑨 𝑩𝑿 𝑩 𝒀 𝑲𝑨 𝑩 𝑿𝒀 𝑱𝑩 𝑨 𝑿 𝑲𝑩 𝑨 𝑿𝒀′
𝒁 𝑨𝑿𝒀 𝑩𝑿 𝒀
Design the circuit.

7. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Explain the working and structure of EEPROM cell. 5
(b) Describe the difference between PAL & PLA using neat diagram and 5
suitable examples.
Printed Pages: 2 Sub Code:KOE049
Paper Id: 238145 Roll No.

B. TECH.
(SEM IV) THEORY EXAMINATION 2022-23
DIGITAL ELECTRONICS
Time: 3 Hours Total Marks: 100
NOTE: 1. Attempt all Sections. If require any missing data, then choose suitably.

SECTION A

1. Attempt all questions in brief. 2 x 10 = 20

(a) Interpret the binary number (1011) 2 into (i) Gray code (ii) Excess-3 Code.
(b) Evaluate (1011)2 - (1101)2 using 1’s and 2’s complement method.
(c) Differentiate between the serial and parallel adder.
(d) How many 4 X 1 multiplexers are required to implement 64 X 1 multiplexer.
(e) What is the difference between characteristic and excitation table.
(f) Differentiate between combinational and sequential circuits.
(g) How many address lines are needed to represent 8K meaning.
(h) Define term propagation delay.
90

2
(i) Define race around condition in JK flip flop.

13
_2
(j) Give the difference between PAL and PLA.

2.
P2

24
3E

SECTION B

5.
.5
2. Attempt any three of the following: 10x3=30
P2

17
(a) Implement the Boolean function F(x,y,z)=(1,2,3,4,6,7) using NAND gates.
Q

(b) Construct a full adder and implement the full adder with the help of half adders.
|1
Also implement the full adder with NAND gates only.
0

(c) Discuss excitation table for SR, JK, T and D flip flop.
:3

(d) Design 8Kx8 RAM memory system, using 1Kx8 memory ICs.
26

(e) Discuss Mealy and Moore finite state machine with an example.
:
13
3

SECTION C
02

3. Attempt any one part of the following: 10x1=10

-2

(a) Simplify Y=∑m (3,6,7,8,10,12,14) + d (0,1,6,15) using K-map method and

08

implement the simplified circuit using logic gates.

3-

(b) Minimize the following Boolean function using tabulation method:

|0

F (a,b,c,d,e) = ∑ m (0,4,12,16,19,24,27,28,29,31)

4. Attempt any one part of the following: 10x1=10

(a) Design a BCD adder using 4-bit parallel adder.
(b) Draw and Explain 2-bit magnitude comparator. Also represent output with the
help of logic diagram.

QP23EP2_290 | 03-08-2023 13:26:30 | 117.55.242.132

5. Attempt any one part of the following: 10x1=10
(a) Design and implement MOD-10 synchronous counter.
(b) For the clocked JK Flip-Flop write the state table, state equation with state
diagram.

6. Attempt any one part of the following: 10x1=10

(a) Why ECL is better? Implement NAND gate with DTL and TTL.
(b) Define noise margin, Fan-in, Fan-out as characteristics of logic families.
Implement NAND gate with CMOS.

7. Attempt any one part of the following: 10x1=10

(a) Explain State Reduction and assignment with suitable example.
(b) Design a sequential circuit with two flip flops, A & B and one input X. When
X=0 state of the circuit remains the same, when X =1 circuit passes through the
state transition from 00 to 01 to 11 to 10 back to 00 and repeat.

90

2
13
_2

2.
P2

24
3E

5.
.5
P2

17
Q

|1
0
:3
: 26
13
3
02
-2
08
3-
|0

QP23EP2_290 | 03-08-2023 13:26:30 | 117.55.242.132

Printed Pages: 2 Sub Code:KOE049
Paper Id: 238145 Roll No.

B. TECH.
(SEM IV) THEORY EXAMINATION 2022-23
DIGITAL ELECTRONICS
Time: 3 Hours Total Marks: 100
NOTE: 1. Attempt all Sections. If require any missing data, then choose suitably.

SECTION A

1. Attempt all questions in brief. 2 x 10 = 20

(a) Interpret the binary number (1011) 2 into (i) Gray code (ii) Excess-3 Code.
(b) Evaluate (1011)2 - (1101)2 using 1’s and 2’s complement method.
(c) Differentiate between the serial and parallel adder.
(d) How many 4 X 1 multiplexers are required to implement 64 X 1 multiplexer.
(e) What is the difference between characteristic and excitation table.
(f) Differentiate between combinational and sequential circuits.
(g) How many address lines are needed to represent 8K meaning.
(h) Define term propagation delay.
90

2
(i) Define race around condition in JK flip flop.

13
_2
(j) Give the difference between PAL and PLA.

2.
P2

24
3E

SECTION B

5.
.5
2. Attempt any three of the following: 10x3=30
P2

17
(a) Implement the Boolean function F(x,y,z)=(1,2,3,4,6,7) using NAND gates.
Q

(b) Construct a full adder and implement the full adder with the help of half adders.
|1
Also implement the full adder with NAND gates only.
0

(c) Discuss excitation table for SR, JK, T and D flip flop.
:3

(d) Design 8Kx8 RAM memory system, using 1Kx8 memory ICs.
26

(e) Discuss Mealy and Moore finite state machine with an example.
:
13
3

SECTION C
02

3. Attempt any one part of the following: 10x1=10

-2

(a) Simplify Y=∑m (3,6,7,8,10,12,14) + d (0,1,6,15) using K-map method and

08

implement the simplified circuit using logic gates.

3-

(b) Minimize the following Boolean function using tabulation method:

|0

F (a,b,c,d,e) = ∑ m (0,4,12,16,19,24,27,28,29,31)

4. Attempt any one part of the following: 10x1=10

(a) Design a BCD adder using 4-bit parallel adder.
(b) Draw and Explain 2-bit magnitude comparator. Also represent output with the
help of logic diagram.

QP23EP2_290 | 03-08-2023 13:26:30 | 117.55.242.132

5. Attempt any one part of the following: 10x1=10
(a) Design and implement MOD-10 synchronous counter.
(b) For the clocked JK Flip-Flop write the state table, state equation with state
diagram.

6. Attempt any one part of the following: 10x1=10

(a) Why ECL is better? Implement NAND gate with DTL and TTL.
(b) Define noise margin, Fan-in, Fan-out as characteristics of logic families.
Implement NAND gate with CMOS.

7. Attempt any one part of the following: 10x1=10

(a) Explain State Reduction and assignment with suitable example.
(b) Design a sequential circuit with two flip flops, A & B and one input X. When
X=0 state of the circuit remains the same, when X =1 circuit passes through the
state transition from 00 to 01 to 11 to 10 back to 00 and repeat.

90

2
13
_2

2.
P2

24
3E

5.
.5
P2

17
Q

|1
0
:3
: 26
13
3
02
-2
08
3-
|0

QP23EP2_290 | 03-08-2023 13:26:30 | 117.55.242.132

 Printed Page: 1 of 2
Subject Code: KOE049
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM IV) THEORY EXAMINATION 2021-22
DIGITAL ELECTRONICS

Time: 3 Hours Total Marks: 100

Note: Attempt all Sections. If you require any missing data, then choose suitably.

SECTION A
1. Attempt all questions in brief. 2x10 = 20
Qno Questions CO
(a) Define the term binary codes with an example. 1
(b) Differentiate between SOP & POS form. 1
(c) Define the term combinational logic with an example. 2
(d) Discuss universal gates. 2
(e) Explain the term Latch. 3
(f) Explain the term registers. 3
(g) Define Asynchronous circuits. 4
(h) Discuss hazards. 4
(i) Discuss logic family and its use. 5
(j) What do you mean by a memory? 5

SECTION B
2. Attempt any three of the following: 10x3 = 30
Qno Questions CO
(a) Explain the implementation of an X-OR gate with NAND 1
implementation.
(b) Illustrate the working of Serial and parallel adders and differentiate the 2
operations.
(c) Explain the working of J-K Flip-Flop. 3
(d) Define the state reduction steps for a machine. 4
(e) Discuss different types of RAM memory cell. 5

SECTION C
3. Attempt any one part of the following: 10x1 = 10
Qno Questions CO
(a) Minimize the following Boolean function using K Map 1
𝒇 𝑨, 𝑩, 𝑪, 𝑫 𝒎 𝟎, 𝟏, 𝟒, 𝟖, 𝟗, 𝟏𝟎 𝒅 𝟐, 𝟏𝟏
(b) Explain different steps associated to Quine Mc Culsy (Tabular 1
Method) of minimizing Boolean Functions.

4. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Design a 4-bit magnitude comparator. 2
(b) Design a full adder and full subtractor using NAND gates only. 2

5. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Describe the Design of J-K FF using T FF. 3
(b) Describe the operations and applications of a Serial-in Parallel-out 3
Shift Register with a neat diagram.
 Printed Page: 2 of 2
Subject Code: KOE049
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

BTECH
(SEM IV) THEORY EXAMINATION 2021-22
DIGITAL ELECTRONICS

6. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Design a sequential circuit with two flip flops A & B and one input x. 4
when x = 0, the state of the circuit remains the same and when x = 1
the circuit passes through the state transitions from 00 to 01 to 11 to 10
back to 00 and repeat.
(b) A sequential circuit has two J K flip flops A & B, two inputs X & Y, 4
and one output Z. The equations defining this system are as following:
𝑱𝑨 𝑩𝑿 𝑩 𝒀 𝑲𝑨 𝑩 𝑿𝒀 𝑱𝑩 𝑨 𝑿 𝑲𝑩 𝑨 𝑿𝒀′
𝒁 𝑨𝑿𝒀 𝑩𝑿 𝒀
Design the circuit.

7. Attempt any one part of the following: 10x1 = 10

Qno Questions CO
(a) Explain the working and structure of EEPROM cell. 5
(b) Describe the difference between PAL & PLA using neat diagram and 5
suitable examples.