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Gales Sonat
18EC36
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\2\ Sa fy! Semester B.E. Degree Examination, Feb./Mar. 2022
A Verilog HDL
“isi Sb ‘Max. Marks: 100
Note: Answer any FIVE full questions, choosing ONE full question from each module.
E 1° a. Explain a typical design flow for designing VLSI IC circuits sing the block diagram.
é (10 Marks)
2 b. Explain the importance of HDLs. — (0s Marks)
i c. Explain the trends in HDLs. (0S Marks)
g2 OR
2 a, Explain the different levels of abstraction used for programming in verilog. (08 Marks)
Es b. Write the verilog code for 4-bit ripple cary counter. Also write the stimulus, (12 Marks)
g i
3. a. Explain the components of verilog mhodiile with block diagram. (06 Marks)
i b. Explain the following data types with an example in verilog.
E i) Registers ii) Arrays ii) Parameters iv) Nets v) Integers. + (10 Marks)
Be cc. Explain the port connection rules in verilog, 4 (04 Marks)
Ee OR
GE 4 a. Write the verliog description of SR latch. Also write stimulus code, (10 Marks)
7 b. Explain Sdisplay, Smonitor, Sfinish and Sstop system tasks with examples. (10 Marks)
Se
Ef Module-3
Ze 5 a. Whatare rise, fall and tum off delays? How they are specified in verilog? (06 Marks)
ge b. What would be the output of the following for A = 4'b0F11 an dB = 4’b1001.
BE i) &Bii) A<<<2 iii) {A, B}. iv) {2{B}) v) A°B vi) AJB vii) A*B viii) A<=B, (08 Marks)
Se ©. Mention the symbol, truth table and an example for BUFIFI and BUFIFO primitive gates.
6 (6 Marks)
a OR
22 6 a. Design AOI based:4 to | multiplexer and write the verilog description and its stimulus.
z (10 Marks)
a b. Write the verilog data flow description for 4-bit full adder with carry look ~ahead logic.
ee (0 Marks)
bz Module-4
=" 7 a. Explain blocking and non-blocking assignments with an example. (10 Marks)
3 b. Write a verilog code for clock generation with a period of 20 units using forever loop.
z (05 Marks)
i ©. Write the differences between the tasks and functions. (05 Marks)
4 oR
8 a, Discuss sequential and parallel blocks with examples. (10 Marks)
b. Write a Verilog program for 8 : 1 multiplexer using case statement. (10 Marks)
1of2 10
18ECS6
Module-5
Write the verilog description for D — flipflop.using assign and deassign procedural
continuous assignments. (0 Marks)
Explain defparam statement with an example, (QO Marks)
OR
What is logic synthesis? Explain the flow diagram for the designer's mind as the logic
synthesis tool. (10 Marks)
What will be the following statements translate to when run on.a logic synthesis tool
Assign (C-out, sum} =a+b+Cin;
Assign out = (8)? il :i05 (do Marks)
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