Contents:

Introduction
Block Diagram and Pin Description of the
8051
Registers
Memory mapping in 8051
I/O Port Programming
Addressing modes
Instruction set

1
Why do we need to learn
Microprocessors/controllers?

 The microprocessor is the core of computer

systems.
 Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
 A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.

2
Different aspects of a
microprocessor/controller

 Hardware :Interface to the real world

 Software :order how to deal with inputs

3
The necessary tools for a
microprocessor/controller
 CPU: Central Processing Unit
 I/O: Input /Output
 Bus: Address bus & Data bus
 Memory: RAM & ROM
 Timer
 Interrupt
 Serial Port
 Parallel Port

4
 Microprocessors:
General-purpose microprocessor
 CPU for Computers
 No RAM, ROM, I/O on CPU chip itself
 Example：Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

5
Microcontroller :
 A smaller computer
 On-chip RAM, ROM, I/O ports...
 Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC
16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

6
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
 CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
 designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports.
• for applications in which cost,
 expansive power and space are critical
 versatility • single-purpose
 general-purpose

7
 Embedded System

 Embedded system means the processor is embedded into that

application.
 An embedded product uses a microprocessor or microcontroller to
do one task only.
 In an embedded system, there is only one application software that
is typically burned into ROM.
 Example：printer, keyboard, video game player

8
 Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost

effectively
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
3. wide availability and reliable sources of the microcontrollers.

9
 Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data

10
11
Pin Description of the 8051

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2)
P0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

12
Pins of 8051

 Vcc (pin 40)

 Vcc provides supply voltage to the chip.
 The voltage source is +5V.
 GND (pin 20): ground
 XTAL1 and XTAL2 (pins 19,18)

13
XTAL Connection to 8051

 Using a quartz crystal oscillator

 We can observe the frequency on the XTAL2 pin.

C2
XTAL2
30pF

C1
XTAL1
30pF

GND

14
Pins of 8051
 RST (pin 9): reset
 It is an input pin and is active high, normally low.
 The high pulse must be high at least 2 machine cycles.
 It is a power-on reset.
 Upon applying a high pulse to RST, the
microcontroller will reset and all values in registers
will be lost.
 Reset values of some 8051 registers
 ACC, B, DPTR, and Most of the registers having 0
 SP=07H, Port pins are logic 1

15
Power-On RESET Circuit
Vcc

10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST

16
Pins of 8051

 /EA（pin 31）：external access

 There is no on-chip ROM in 8031 and 8032 .
 The /EA pin is connected to GND to indicate the code is
stored externally.
 /PSEN ＆ ALE are used for external ROM.
 For 8051, /EA pin is connected to Vcc.
 “/” means active low.
 /PSEN（pin 29）：program store enable
 This is an output pin and is connected to the OE pin of the
ROM.

17
Pins of 8051
 ALE（pin 30）: address latch enable
 It is an output pin and is active high.
 8051 port 0 provides both address and data.
 The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.
 I/O port pins
 The four ports P0, P1, P2, and P3.
 Each port uses 8 pins.
 All I/O pins are bi-directional.

18
Pins of I/O Port
 The 8051 has four I/O ports
 Port 0 （pins 32-39）：P0（P0.0～P0.7）
 Port 1（pins 1-8） ：P1（P1.0～P1.7）
 Port 2（pins 21-28）：P2（P2.0～P2.7）
 Port 3（pins 10-17）：P3（P3.0～P3.7）
 Each port has 8 pins.
 Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X
 Ex：P0.0 is the bit 0（LSB）of P0
 Ex：P0.7 is the bit 7（MSB）of P0
 These 8 bits form a byte.
 Each port can be used as input or output (bi-direction).

19
Hardware Structure of I/O Pin
 Each pin of I/O ports
 Internal CPU bus：communicate with CPU
 A D latch store the value of this pin
 D latch is controlled by “Write to latch”
 Write to latch＝1：write data into the D latch
 2 Tri-state buffer：
 TB1: controlled by “Read pin”
 Read pin＝1：really read the data present at the pin
 TB2: controlled by “Read latch”
 Read latch＝1：read value from internal latch
 A transistor M1 gate
 Gate=0: open
20
 Gate=1: close
D Latch:

21
A Pin of Port 1
Read latch Vcc
TB2
Load(L1)

Internal CPU D Q P1.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin

8051 IC 22
 Writing “1” to Output Pin P1.X
Read latch Vcc
TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q
1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1

TB1
Read pin

8051 IC 23
 Writing “0” to Output Pin P1.X
Read latch Vcc
TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q
0 P1.X
Internal CPU
bus P1.X pin
1 output 0
Write to latch Clk Q M1

TB1
Read pin

24
 Reading “High” at Input Pin
Read latch Vcc 2. MOV A,P1
TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

25
 Reading “Low” at Input Pin
Read latch Vcc 2. MOV A,P1
TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

26
Port 3 Alternate Functions

P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
27
 Registers
A

R0
DPTR DPH DPL
R1

R2 PC PC
R3

R4 Some 8051 16-bit Register

R5

R6

R7

Some 8-bitt Registers of

the 8051

28
Memory mapping in 8051

 ROM memory map in 8051 family

4k 8k 32k
0000H 0000H 0000H

0FFFH
DS5000-32

1FFFH
8751
AT89C51
8752
AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

29
RAM memory space allocation in the 8051
7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH (Stack) Register Bank 1
08H
07H
Register Bank 0
00H

30
Memory Space

31
Bit Addressable RAM

Summary
of the 8051
on-chip
data
memory
(RAM)

32
 Bit Addressable RAM

Summary
of the 8051
on-chip
data
memory
(Special
Function
Registers)

33
Register Banks

 Four banks of 8 byte-sized registers, R0 to R7

 Addresses are :
18 - 1F for bank 3
10 - 17 for bank 2
08 - 0F for bank 1
00 - 07 for bank 0 (default)

34
 Address Multiplexing for External Memory

Multiplexing
the address
(low-byte)
and data
bus

35
 Accessing External Code Memory

Accessing
external
code
memory

36
37
 Accessing External
Data Memory

Figure
2-11
Interface
to 1K
RAM

38
Assembler Directives

 Assembler Directives are Instructions for the

ASSEMBLER
 NOT 8051 instructions
 Examples:
cseg stands for “code segment”
cseg 1000h ;address of next instruction
is 1000h
GREEN_LED equ P1.6 ;symbol for Port 1, bit 6

39
Assembler Directives
 DATA
 Used to define a name for memory locations
SP DATA 0x81 ;special function registers
MY_VAL DATA 0x44 ;RAM location

Address
 EQU
 Used to create symbols that can be used to
represent registers, numbers, and addresses
LIMIT EQU 2000
VALUE EQU LIMIT – 200 + 'A'
SERIAL EQU SBUF
COUNT EQU R5
MY_VAL EQU 0x44 Registers, numbers, addresses

40
Addressing Modes

 The various addressing modes of a microprocessor are

determined when it is designed, and therefore cannot be
changed by the programmer.
 The 8051 provides a total of five distinct addressing modes.
(1) immediate
(2) register
(3) direct
(4) register indirect
(5) indexed

41
Immediate addressing mode

 The operand comes immediately after the op-code.

 The immediate data must be preceded by the pound sign,
"#".

42
Register addressing mode

 Register addressing mode involves the use of registers to

hold the data to be manipulated.

43
ACCESSING MEMORY USING VARIOUS
ADDRESSING MODES

Direct addressing mode

There are 128 bytes of RAM in the 8051.
The RAM has been assigned addresses 00 to 7FH.
 1. RAM locations 00 - 1 FH are assigned to the register
banks and stack.
 2. RAM locations 20 - 2FH are set aside as bit-addressable
space to save singlebit data.
 3. RAM locations 30 - 7FH are available as a place to save
byte-sized data.

44
Direct addressing mode

 It is most often used to access RAM locations 30 - 7FH.

 This is due to the fact that register bank locations are

accessed by the register names of R0 - R7.

 There is no such name for other RAM locations so must use

direct addressing.

45
Direct addressing mode

 In the direct addressing mode, the data is in a RAM memory

location whose address is known, and this address is given as
a part of the instruction.

46
Special Function Registers

In the 8051, registers A, B, PSW, and DPTR are

part of the group of registers commonly referred to
as SFR.
The SFR can be accessed by their names or by their
addresses.
For example, register A has address E0H and
register B has been designated the address F0H.

47
SFR

48
ACCESSING MEMORY USING VARIOUS
ADDRESSING MODES

SFR registers and their addresses 49

Stack and direct addressing mode

 Another major use of direct addressing mode is the stack.

 In the 8051 family, only direct addressing mode is allowed
for pushing onto the stack.
 An instruction such as "PUSH A" is invalid. Pushing the
accumulator onto the stack must be coded as "PUSH
0E0H.
 Direct addressing mode must be used for the POP instruction
as well.
 "POP 04" will pop the top of the stack into R4 of bank 0.

50
Register indirect addressing mode

 A register is used as a pointer to the data.

 If the data is inside the CPU, only registers R0 and R 1 are

used for this purpose.

 R2 - R7 cannot be used to hold the address of an operand

located in RAM when using indirect addressing mode.

 When RO and R 1 are used as pointers they must be

preceded by the @ sign.

51
Register indirect addressing mode

52
Advantage of register indirect addressing mode

One of the advantages of register indirect

addressing mode is that it makes accessing data
dynamic rather than static as in the case of direct
addressing mode.

Looping is not possible in direct addressing mode.

This is the main difference between the direct and

register indirect addressing modes.

53
Advantage of register indirect addressing mode

54
Limitation of register indirect addressing mode in the 8051

 R0 and R1 are the only registers that can be used for pointers
in register indirect addressing mode.

 Since R0 and Rl are 8 bits wide, their use is limited to

accessing any information in the internal RAM (scratch pad
memory of 30H - 7FH, or SFR).

 To access data stored in external RAM or in the code space

of on-chip ROM, we need a 16-bit pointer, the DPTR.

55
Indexed addressing mode and on-chip ROM access

 Indexed addressing mode is widely used in accessing data

elements of look-up table entries located in the program
ROM space of the 8051.
 The instruction used for this purpose is :
MOVC A, @ A+DPTR
 The 16-bit register DPTR and register A are used to form the
address of the data element stored in on-chip ROM.
 Because the data elements are stored in the program (code)
space ROM of the 8051, the instruction MOVC is used
instead of MOV. The "C" means code.
 In this instruction the contents of A are added to the 16-bit
register DPTR to form the 16bit address of the needed data.

56
Indexed addressing mode and MOVX instruction

 The 8051 has another 64K bytes of memory space set aside
exclusively for data storage.
 This data memory space is referred to as external memory
and it is accessed by the MOVX instruction.
 The 8051 has a total of 128K bytes of memory space since
64K bytes of code added to 64K bytes of data space gives us
128K bytes.
 One major difference between the code space and data space
is that, unlike code space, the data space cannot be shared
between code and data.

57
BIT ADDRESSES FOR I/O AND RAM

58
BIT ADDRESSES FOR I/O AND RAM

59
Instruction set
 Arithmetic Instructions
 Logical Instruction
 Data Transfer
 Boolean Variable Manipulation
 Program Branching

60
Arithmetic Instructions

61
Logical Instructions

62
Data Transfers

63
Data Transfers

64
Boolean Manipulation Instructions

65
Program Branching Instructions

66