FLOWS

LEC
The primary purpose pf LEC is to verify that two different representations
of a digital circuit are functionally equivalent. Specifically, it compares the
behavior of the original RTL description of the circuit with the gate-level
netlist generated after RTL synthesis
here are three basic steps in equivalence checking:
1. Setup
2. Mapping
3. Compare
Tool :
Inputs : lib, golden netlist, revised netlist
➢ synth tool : write the do file
write_lec_do -golden <file_name.v>
➢ To invoke tool : lec <do_file.v>

➢ SETUP :::
Mode : tcl mode
setting libs: Lib_files <files>
setting RTL vs Netlist :
Golden_verilog_file “rtl_file.v’
Revised_verilog_filre “netlist.v”

➢ MAPPING ::
o Mapping_file “file.v” + constraints
o Read lef and lib files :
Read_lef_files “file.lef”
Read_lib_files “file.lib”
o Read revised and golden netlist :
Read_verilog -golden <rtl.v> -revised <netlist.v>

➢ COMPARE :
o Mode :
Set_system_mode lec
Compare
- Un reachable DFF
- Un compared ports
 CLP
CLP : its perform power intent checks (upf)
1. Power intent quality check (pre synth)
2. Structal check (post synth)
Once we start working on low power design, we need to perform low power
checks
That includes
Reading the PG netlist
Reading the UPF
Run low power checks called CLP
Synopsis : check_mv_design
Cadence : report_rule_check -lp
Check lowpower cells
Tool :
➢ Inputs : pre synth :lib ,RTL, UPF
Post synth : lib, netlist ,UPF
➢ To invoke tool : lec_1801 -lp -verfy -dofile <file>
➢ Set_low_power_option -native_1801 (upf formate)
➢ Pre synth or post synth analysis :
Set_low_power_option -analysis_style pre_synthesis
➢ Set search path for netlist or RTL :
Set_search_path -design <netlist.v>
➢ Read libs and netlist :
Read_library -both -lp <files.lib>
➢ Elobarate design only for RTL vs UPF
Elaborate_design -root <chiptop> -rootonly
Report_rule_check -design
➢ Read UPF
Read_power_intent -1801 <file.upf>
Commit_power_intent
➢ Checks :
Report_rule_check -lp
Check_low_power_cells

Checks :
• The isolation, level shifter, or retention supply is powered-down during
the active isolation, level shifting, or retention period.
• The power signal of a power domain gets corrupted.
• The input of a power domain toggles when the power domain is
powered-down.
• The power state table or the supply port reaches an illegal or undefined
state.
 IR & EM (voltus)

Early grid check ( after power plan) Static and Dynamic analysis
(post route)
➢ Power mesh analysis
Inputs:
Inputs :
- Pg netlist
- Powerplan.db - Routed def
- .pp file (power pad file) - Spef
- Pgvg files (.cl)
- Mcmm
- SAIF / VDC

Inputs Required :

• . v file -Gate level netlist

• . lef file-Library Exchange Format

• .def file - Design Exchange Format

• .lib file- Liberty Timing File

• .sdc file - System design constraints

• Common Power Format

• .spef file - Standard Parasitic Exchange Format

• Power Grid View

1. Flat Method :
In the traditional flat analysis flow, the entire design data is given as input for Power
analysis to perform power calculation and generate current files. These current files,
along with the complete design and power grid views of primitive cells, are used as
input for rail analysis to generate IR drop results.
2.Hierarchical method :
For the hierarchical rail analysis, requires the flat or hierarchical current files (.cl) , top-
level design data, and PGV of hierarchical blocks and primitive cells. This flow does not
require block level design data, instead it requires the PGV of hierarchical blocks.
Therefore, the design information required for Rail analysis is very less. Thereby
hierarchical flow provides the flexibility and scalability to perform static and dynamic
rail analysis on very large designs with fast turnaround time.

PGVG generation :
Figure 3 shows the block diagram for generation of hierarchical Power Grid Views. The
hierarchical PGV generation of a block is part of the top-level hierarchical rail analysis.
The inputs for hierarchical PGV generation are DEF and LEF files for the hierarchical
blocks, PGVs of primitive cells, power, and ground information of the blocks.

➢ Figure 4 briefs about the hierarchical method of analyzing IR drop, Signal

Electromigration (SEM) and Self Heating Effect (SHE). A top-level of chip is
considered to perform hierarchical IR drop analysis.

The following steps describes the hierarchical analysis flow:

• To load the Top-level hierarchical design. Specifying the block-level Verilog, DEF,
primitive cell‟s LEF and block level LEF files in the design.

• To ensure that there are no connectivity violations around the block.

• To perform hierarchical PGV generation.

• Run static/dynamic rail analysis

Tool :
Static Analysis :
1.read lef , netlist , Def files
- Read_lib -lef <xyz.lef>
- read_verilog <file.v>
- read_def <xyz.def.gz>
2. Load and commit cpf :
Read_power_domain -cpf <file.cpf>
3. Read SPEF :
Read_spef -rc_corner RC_WC <xyz.spef.gz>
4. Analysis mode :
Set_power_analysis_mode -method static
5. Default switching activity :
Set_default_switching_activi ……..
6. Run power analysis
Report_power
Analyze_rail
Dynamic Analysis :
1. Vectorless Methodology

Cmd: to enable thevectorless propagation based analysis

Set_power_analysis_mode -method dynamic_vectorless
-enable_state_propagation true
2. Vector based Methodology :
 STA
➢ Static timing analysis (STA) is a method of validating the timing
performance of a design by checking all possible paths for timing
violations. STA breaks a design down into timing paths, calculates the
signal propagation delay along each path, and checks for violations of
timing constraints inside the design and at the input/output interface.
➢ Another way to perform timing analysis is to use dynamic simulation,
which determines the full behavior of the circuit for a given set of input
stimulus vectors. Compared to dynamic simulation, static timing
analysis is much faster because it is not necessary to simulate the
logical operation of the circuit. STA is also more thorough because it
checks all timing paths, not just the logical conditions that are
sensitized by a set of test vectors. However, STA can only check the
timing, not the functionality, of a circuit design.
➢ How Does STA Work :
When performing timing analysis, STA first breaks down the design into
timing paths.
An STA tool may let you specify the following types of exceptions:
• False path. A path that is never sensitized due to the logic
configuration, expected data sequence, or operating mode.
• Multicycle path. A path designed to take more than one clock cycle
from launch to capture.
Tool :
➢ Load input files
Mcmm , netlist, sdc, spef
Read_mcmm <file>
Read_verilog <file.v>
Read_spef …
➢ Perform timing analysis
Set up and hold : Report_timing , time_design
DRVs : Report_constraint

➢ Fixes
Cadence : sizeing = eco_update_cell -cell <inst_name> -up_size
Buffer adding = eco_add_repeater -net <net_name> -cell <cell_name>
Synopsis : fix_eco , add_buffer
 PV
Inputs :

Checks :

LVS flow :
LVS checks :

DRC :
Checks :

Tool :

➢ Preparation of source netlist :

- V2lvs
➢ Layout netlist extraction
- Write_stream
➢ Compare
- Calibre -hier -hyper -turbo <file.compare>