Lecture 13 – Timing Analysis

I. References

II. ASIC vs FPGA Design Flow

Lecture 13 – Timing Analysis
III. Synthesis
Ryan Robucci
IV. Packing
DEPARTEMENT OF COMPUTER SCIENCE
V. Place and Route AND ELECTRICAL ENGINEERING

VI. Timing Analysis and Post-

Place-and-Route simulation
I. References
VII. FPGA vs ASIC Tools

VIII. Static Timing Analysis [ꭝ] Illustration from The Design Warriors's Guide to FPGAs by Clive Maxfield, Elsevier
[ꭝꭝ] Modeling, Synthesis and Rapid Prototyping with the Verilog HDL, Michael D. Ciletti
IX. Timing Analysis Concepts
Basic Timing Analysis Concepts:
X. Clock Period Constraint https://eclipse.umbc.edu/robucci/cmpe415/attachments/Lecture14.pdf#page=10 Page 10-31
XI. Clock Domain Defined by
Seq. Elements
II. ASIC vs FPGA Design Flow
XII. Setup and Hold Times

XIII. Clock Skew

XIV. Positive Clock Skew

XV. Negative Clock Skew

XVI. Setup Timing Slack in

Critical Path

XVII. Setup Time Analysis

(slack)

XVIII. Hold Time Analysis and

Slack

XIX. Unconstrained Paths

XX. Related Clock Domains

XXI. Multicycle Paths

XXII. False Paths

Source: Xilinx Training Material fpga-vs-asic-design-fow.ppt
XXIII. Asynchronous Signals
(e.g. Async Clear)

XXIV. Dynamic Timing Analysis III. Synthesis

XXV. Dynamic Timing Analysis
Mapping is the process of associating entities such as gate-level functions in the gate-level netlist with
using Event-Driven Simulation
the physical LUT-level functions available on the FPGA
XXVI. Dynamic vs Static Timing
Analysis; Functional vs Timing
Verification

XXVII. Review Static vs

Dynamic

ꭝMaxfield
Lecture 13 – Timing Analysis

I. References

II. ASIC vs FPGA Design Flow

III. Synthesis

IV. Packing

V. Place and Route

VI. Timing Analysis and Post-

Place-and-Route simulation ꭝMaxfield

VII. FPGA vs ASIC Tools

VIII. Static Timing Analysis

IV. Packing
IX. Timing Analysis Concepts

X. Clock Period Constraint Packing is grouping of LUT and registers into CLBs

XI. Clock Domain Defined by Collection

Seq. Elements
of CLBs
XII. Setup and Hold Times Collection CLB
CLB
of LUTs LUT
XIII. Clock Skew

XIV. Positive Clock Skew

LUT LUT
XV. Negative Clock Skew LUT CLB

XVI. Setup Timing Slack in

LUT
LUT
Critical Path
LUT
XVII. Setup Time Analysis
(slack)

XVIII. Hold Time Analysis and

LUT CLB

Slack
LUT
XIX. Unconstrained Paths LUT
XX. Related Clock Domains

XXI. Multicycle Paths

V. Place and Route
XXII. False Paths

XXIII. Asynchronous Signals Place and Route is the process of placing CLBs and finding routing configuration to make required
(e.g. Async Clear) interconnections
Placment
XXIV. Dynamic Timing Analysis Programmable CLB
Locations

XXV. Dynamic Timing Analysis LUT LUT LUT

CLB
CLB
using Event-Driven Simulation LUT LUT LUT LUT
XXVI. Dynamic vs Static Timing LUT
Analysis; Functional vs Timing
CLB
Verification LUT LUT LUT LUT
XXVII. Review Static vs LUT LUT LUT LUT
Dynamic

CLB
Programmed Switches
LUT to Configure Routing
LUT LUT LUT
LUT
LUT LUT LUT

VI. Timing Analysis and Post-Place-and-Route simulation

After Place and route, we have a fully routed physical design and a timing analysis tool can extract
timing and check for any timing violations (setup, hold,etc...) associated with any of the internal
registers.
These are more accurate than load estimates that would be used before place and route
 A new netlist can be generated that includes accurate delays in a standard delay format SDF file
associated with the post place and route netlist (can't push delays directly back to original
Lecture 13 – Timing Analysis
description as lots of stuff has moved around or changed)
I. References

II. ASIC vs FPGA Design Flow

VII. FPGA vs ASIC Tools
III. Synthesis

IV. Packing FPGAs vs ASICs: FPGAs are regular structures and a represent a constrained design space for
analysis tools (and synthesis tools).
V. Place and Route
Many designs will emerge from one underlying physical hardware design.
VI. Timing Analysis and Post- This underlying hardware can be heavily characterized in the fabricated IC. This for allows tools that
Place-and-Route simulation
can perform accurate general design analysis for anyone using the same underlying hardware. In
VII. FPGA vs ASIC Tools ASICs, each design can be very different, meaning it is more difficult for tools to accurately predict

VIII. Static Timing Analysis

timing for every possible design. In ASIC Design, SPICE-Level simulation is sometimes used.

IX. Timing Analysis Concepts

X. Clock Period Constraint VIII. Static Timing Analysis

XI. Clock Domain Defined by
Static timing analysis refers to using using delays extracted from physical implementation to
Seq. Elements
analyze timing directly rather than through simulation
XII. Setup and Hold Times Place-and-routed delays are extracted from place and routed design
XIII. Clock Skew Static timing analysis does not involve driving inputs input the system and analyzing resulting
waveforms
XIV. Positive Clock Skew
Static Timing Analysis is often fast and may be part of an automation tool’s optimization process to
XV. Negative Clock Skew
test and evaluate design option trade-offs
XVI. Setup Timing Slack in Pre place-and-route estimates delays and can drive synthesis, timing-driven synthesis, Timing-
Critical Path Driven Synthesis logic option
XVII. Setup Time Analysis Typically pessimistic delay assumptions are made to arrive at a worst-case model – a data-driven
(slack) simulation may reveal what delays are actually relevant in a design

XVIII. Hold Time Analysis and

Slack
IX. Timing Analysis Concepts
XIX. Unconstrained Paths

XX. Related Clock Domains User Constraints (e.g. user constraints file, directives, * project settings)
Clock Domains
XXI. Multicycle Paths
Clock Jitter
XXII. False Paths Aync Reset
XXIII. Asynchronous Signals Multi-cycle Paths
(e.g. Async Clear) False Paths

XXIV. Dynamic Timing Analysis

XXV. Dynamic Timing Analysis X. Clock Period Constraint

using Event-Driven Simulation

XXVI. Dynamic vs Static Timing For Xilinx Tools, a PERIOD constraint should be supplied for every clock
Analysis; Functional vs Timing
Verification NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
XXVII. Review Static vs
Dynamic
– or NET "CLK_50MHZ" TNM_NET=’’TNM_clk50”
TIMESPEC “TS_clk50” = PERIOD “TNM_clk50” 20.0ns HIGH 40%;

partia l
b

c y
 XI. Clock Domain Defined by Seq. Elements
Lecture 13 – Timing Analysis
Sequential Elements Include
I. References
Flip Flops
II. ASIC vs FPGA Design Flow
Latches
III. Synthesis Clocked Distributed and Block RAM/ROM
FIFOs
IV. Packing
I/O Hardware with Clock Input (e.g. I/O SerDes)
V. Place and Route
Hardware bocks with Clock Input (e.g. Xilnix MULT18/18)
VI. Timing Analysis and Post- The combinational paths between sequential elements in the same clock domain are constrained
Place-and-Route simulation and must be analyzed
VII. FPGA vs ASIC Tools

VIII. Static Timing Analysis

XII. Setup and Hold Times
IX. Timing Analysis Concepts

X. Clock Period Constraint

XI. Clock Domain Defined by

Seq. Elements

XII. Setup and Hold Times

Thold Thold
XIII. Clock Skew Tsu Tsu

XIV. Positive Clock Skew Clock

XV. Negative Clock Skew Tsla ck(setup)
Slow Pa th with
XVI. Setup Timing Slack in Positive Setup Sla ck
Critical Path Tsla ck(setup)
Slow Pa th with
XVII. Setup Time Analysis
Negative Setup Sla ck
(slack)
Fa st Pa th with Tsla ck(hold)
XVIII. Hold Time Analysis and
Slack
Positive Hold Sla ck
0.2 " Tslack(hold)
XIX. Unconstrained Paths
Fa st Pa th with
Negative Hold Sla ck
XX. Related Clock Domains
Setup and Hold times define a window around a clock edge during which data inputs to a register
XXI. Multicycle Paths should not transition.
XXII. False Paths Setup Time defines the time before a clock edge that a signal must settle. A violation occurs with a
path delay is too large. (It so happens that negative setup times are common)
XXIII. Asynchronous Signals
Hold Time defines the time after a clock edge that a signal must not begin a transition. A violation
(e.g. Async Clear)
occurs when a path delay is too small.
XXIV. Dynamic Timing Analysis
Setup and Hold Time Slack quantify how much “room to spare” before and error occurs. A negative
XXV. Dynamic Timing Analysis slack indicates a violation.
using Event-Driven Simulation

XXVI. Dynamic vs Static Timing

Analysis; Functional vs Timing
XIII. Clock Skew
Verification

XXVII. Review Static vs

Dynamic
Lecture 13 – Timing Analysis Clock
I. References Tsource clock de la y

II. ASIC vs FPGA Design Flow Source Clock

III. Synthesis
Tdestina tion clock dela y
IV. Packing

V. Place and Route

Destina tion Tsu
Thold
Tsu
Thold

VI. Timing Analysis and Post-

Clock
Place-and-Route simulation

VII. FPGA vs ASIC Tools Tskew

VIII. Static Timing Analysis Clocks are buffered through a clock routing network. Clock signals are delayed with respect to the
IX. Timing Analysis Concepts original clock.
Paths are defined starting at a source register and terminating at a destination register
X. Clock Period Constraint
Path delay: TPD ​ = Tclk−to−q + Tcomb. path delay
​ ​

XI. Clock Domain Defined by

Clock Skew is the difference in arrival time of clock edges at destination registers and source
Seq. Elements
registers
XII. Setup and Hold Times

XIII. Clock Skew

XIV. Positive Clock Skew
XIV. Positive Clock Skew

XV. Negative Clock Skew

XVI. Setup Timing Slack in

Critical Path

XVII. Setup Time Analysis

Tskew
(slack) .
XVIII. Hold Time Analysis and
Slack Clock
XIX. Unconstrained Paths
Source
XX. Related Clock Domains
Clock Available Path Delay
XXI. Multicycle Paths Without clock skew
Available Path Delay
XXII. False Paths
with clock Skew
XXIII. Asynchronous Signals Min Allowed TPD w/ o clock Skew
(e.g. Async Clear) Min Allowed TPD with clock Skew

XXIV. Dynamic Timing Analysis

Destina tion Tsu
Thold (worse)
Tsu
Thold

Clock
XXV. Dynamic Timing Analysis
using Event-Driven Simulation Setup and hold time windows are defined with respect to the destination register clock edge
If the destination clock is more delayed than the source clock, it represents positive clock skew
XXVI. Dynamic vs Static Timing
Analysis; Functional vs Timing with regard to that path. This gives more time for a path to settle and thus avoid a setup time
Verification violation. It unfortunately delays the cutoff time for holding a data signal.

XXVII. Review Static vs

Dynamic
XV. Negative Clock Skew
 .
Lecture 13 – Timing Analysis
● Clock
I. References
Source
II. ASIC vs FPGA Design Flow
Clock Ava ilable Path Delay
III. Synthesis Without clock skew

IV. Packing Ava ilable Path Delay

with clock Skew
V. Place and Route
Min Allowed TPD w/ o clock Skew Tskew
VI. Timing Analysis and Post- Min Allowed TPD with clock Skew
Place-and-Route simulation (better)

VII. FPGA vs ASIC Tools Destina tion Tsu

Thold
Tsu
Thold

VIII. Static Timing Analysis Clock

IX. Timing Analysis Concepts
If the destination clock is less delayed than the source clock, it represents negative clock skew
X. Clock Period Constraint
with respect to that path. This gives less time for a path to settle and advances the cutoff time
XI. Clock Domain Defined by for when a signal must hold.
Seq. Elements

XII. Setup and Hold Times

XVI. Setup Timing Slack in Critical Path
XIII. Clock Skew

XIV. Positive Clock Skew Static Timing Analysis is a structural analysis based on previous characterizations. A key parameter
from the analysis is the setup timing slack
XV. Negative Clock Skew
TCLK TO Q : Delay from clock edge to sequential gates update
​

XVI. Setup Timing Slack in

TCPD : Delay through combinatorial gates and routing
​

Critical Path
TPD : Path Delay, TCLK TO Q + TCPD
​ ​ ​

XVII. Setup Time Analysis

(slack) Critical Path Timing requirement: Tclk ​
+ Tskew > TPD + Tsetup
​ ​

Tskew : Time from when clk edge occurs at an source flip-flip to when the edge occurs at a destination
XVIII. Hold Time Analysis and
​

(e.g. clock delay 1 -clock delay 2) As defined here, positive clock skew with respect to a critical path
Slack
increases setup slack, while negative skew reduces it.
XIX. Unconstrained Paths

XX. Related Clock Domains

XXI. Multicycle Paths

XXII. False Paths

XXIII. Asynchronous Signals

(e.g. Async Clear)

XXIV. Dynamic Timing Analysis

XXV. Dynamic Timing Analysis

using Event-Driven Simulation
XVII. Setup Time Analysis (slack)
XXVI. Dynamic vs Static Timing
Analysis; Functional vs Timing For each path there should be some slack to the timing. A positive slack value refers to how much
Verification
extra delay could be added or how much faster a clock rate could be..
XXVII. Review Static vs TsuSlack : positive slack indicates the timing requirement is met for a defined clock period while a
​

Dynamic negative slack means it has not

TsuSlack = Tclk − (TPD + Tsetup ) + Tskew − (Jitter or Uncertainty)
​ ​ ​

All possible paths must be analyzed. The paths with the longest delay are important, but the
analysis should be a combination of path delay and clock skew and clock and path delay
uncertainty, not just path delay.
A short delay path could still be a problem because of race conditions
Setup Time Analysis = Data Path Delay including source clock-to-q delay + Desitination
Synchronous Element Setup Time - Clock Path Skew
Lecture 13 – Timing Analysis a
I. References
pa rtia l
II. ASIC vs FPGA Design Flow b
III. Synthesis

IV. Packing c
V. Place and Route

VI. Timing Analysis and Post-

Place-and-Route simulation

VII. FPGA vs ASIC Tools XVIII. Hold Time Analysis and Slack
VIII. Static Timing Analysis
Hold Time Analysis Avoids Race Conditions
IX. Timing Analysis Concepts Tslack(hold) = TPD -Thold- Tskew
X. Clock Period Constraint

XI. Clock Domain Defined by

Seq. Elements

XII. Setup and Hold Times

XIII. Clock Skew

XIV. Positive Clock Skew

Most problematic are “short” combinatorial paths and high clock skew (e.g. back-to-back registers
XV. Negative Clock Skew
far from each other on the clock network)
XVI. Setup Timing Slack in Can fix by slowing path (adding several slow buffers in series)
Critical Path In VLSI, tend to route clock in oposite direction of data whenever creating shift register chains.
XVII. Setup Time Analysis
(slack)

XVIII. Hold Time Analysis and

XIX. Unconstrained Paths
Slack
What is (not) Included? Input Offsets and Output requirements
XIX. Unconstrained Paths Assume CLKA and CLKB are independently constrained – Unrelated Clock Domains
XX. Related Clock Domains

XXI. Multicycle Paths

XXII. False Paths

XXIII. Asynchronous Signals

(e.g. Async Clear)

XXIV. Dynamic Timing Analysis

XXV. Dynamic Timing Analysis

using Event-Driven Simulation

XXVI. Dynamic vs Static Timing

Analysis; Functional vs Timing
Verification
Source: Xilinx Timing Constraints User Guide
XXVII. Review Static vs
Dynamic By default, the input and output paths, regardless if there is only one or more clock domains, are not
analyzed
Can add a specification for time after a clock edge allowed to reach output pad
Can add a specification for the transition window for input to analyze setup and hold time
Cross domain paths are paths originating from the output of a sequential element in one clock
domain and ending at the input of sequential elements in another clock domain
By default, if multiple clock domains are present, cross-domain paths are not constrained and not
analyzed.

XX. Related Clock Domains

If the clocks of two clock domains are related in some limited ways, the paths can be analyzed, if
the relationship is specified...
 Slide Source: Xilinx Timing Constraints User Guide

Lecture 13 – Timing Analysis

I. References

II. ASIC vs FPGA Design Flow

Following is an example of the PERIOD constraint syntax. The TS_Period_2 constraint value is a
III. Synthesis
multiple of the TS_Period_1 TIMESPEC.
IV. Packing
TIMESPEC TS_Period_1 = PERIOD "clk1_in_grp" 20 ns HIGH 50%;
V. Place and Route TIMESPEC TS_Period_2 = PERIOD "clk2_in_grp" TS_Period_1 * 2;

VI. Timing Analysis and Post-

Note that if the two PERIOD constraints are not related in this method, the cross clock domain data
Place-and-Route simulation
paths is not covered or analyzed by any PERIOD constraint.
VII. FPGA vs ASIC Tools
Other information can be specified like lag (phase)
VIII. Static Timing Analysis The existence of paths that cannot be analyzed by STA, unconstrained paths, will be noted in the

IX. Timing Analysis Concepts

timing analysis report

X. Clock Period Constraint

XI. Clock Domain Defined by XXI. Multicycle Paths

Seq. Elements
Can override delay on some paths, such as providing a series of multipliers two clock cycles instead
XII. Setup and Hold Times
of one to complete
XIII. Clock Skew In this example the assertion of the enable signals (en) determines the actual constraints. An STA
XIV. Positive Clock Skew tool may not have an understanding/information about the design to infer this
Consult documentation for adjusting timing constraints of individual paths
XV. Negative Clock Skew

XVI. Setup Timing Slack in

Critical Path

XVII. Setup Time Analysis

(slack)

XVIII. Hold Time Analysis and

Slack

XIX. Unconstrained Paths

XX. Related Clock Domains XXII. False Paths

XXI. Multicycle Paths
Can exclude paths were timing based on a single-cycle is not important (false paths)
XXII. False Paths
In the following example, assume mode is a signal set once upon processor power-up initialization.
XXIII. Asynchronous Signals
...
(e.g. Async Clear)
S3: D <= (endianMode?{AH,AL}:{AL,AH})
+ (endianMode?{BH,BL}:{BL,BH});
XXIV. Dynamic Timing Analysis

XXV. Dynamic Timing Analysis

The transition on endianMode is therefore not required for timing analysis, but it would make
using Event-Driven Simulation
sense to request 2 STA, on the case where endianMode is 1 and when it is 0
XXVI. Dynamic vs Static Timing Where the design accounts for timing concerns, such as explicit designs to handle Clock Domain
Analysis; Functional vs Timing
Crossing and Synchronizers, standard analysis and warning isn't meaningful
Verification
always @ (posedge clk) begin
XXVII. Review Static vs Q1<=in;
Dynamic Q2<=Q1;
end

Or if the architecture doesn't require a path to meet timing. For instance in the following example, it
may be the case that selA and selB are never both high, meaning the path through C1 and C3 is a
false path
Lecture 13 – Timing Analysis selA selB
C0 sel C2 sel
I. References 0 0
II. ASIC vs FPGA Design Flow 1 1
C1 C3
III. Synthesis

IV. Packing

V. Place and Route Other Examples:

https://www.edn.com/design/integrated-circuit-design/4433229/Basics-of-multi-cycle---false-paths
VI. Timing Analysis and Post-
Place-and-Route simulation

VII. FPGA vs ASIC Tools XXIII. Asynchronous Signals (e.g. Async Clear)
VIII. Static Timing Analysis
Note that asynchronous signals are not easily analyzed for timing and are sensitive to glitches.
IX. Timing Analysis Concepts

X. Clock Period Constraint

XI. Clock Domain Defined by

Seq. Elements

XII. Setup and Hold Times

XIII. Clock Skew

XIV. Positive Clock Skew

XV. Negative Clock Skew

XVI. Setup Timing Slack in

Wherever sensitivity to glitches exits, use registered output logic to generate the control signal.
Critical Path

XVII. Setup Time Analysis

(slack) XXIV. Dynamic Timing Analysis
XVIII. Hold Time Analysis and
Slack
Whereas static timing analysis processes timing equations based on the circuit structure, dynamic
timing analysis uses the results of a temporal simulation
XIX. Unconstrained Paths
The generated/saved waveforms (i.e. transient waveforms) are analyzed for timing violations and
XX. Related Clock Domains glitches
XXI. Multicycle Paths A complexity is that suitable input sequences (input vectors) must be created to test characteristics
of the circuit at internal points.
XXII. False Paths

XXIII. Asynchronous Signals

(e.g. Async Clear) XXV. Dynamic Timing Analysis using Event-Driven
XXIV. Dynamic Timing Analysis
Simulation
XXV. Dynamic Timing Analysis
using Event-Driven Simulation Verilog tools include several methods for annotating timing including use of

XXVI. Dynamic vs Static Timing

specify blocks
Analysis; Functional vs Timing
Verification

XXVII. Review Static vs

Dynamic

[ꭝꭝ] Figure 2.8 Michael D. Ciletti

Timing Data augmentation using a sidecar files e.g. Standard Delay Format Files
Delay parameters (e.g. #) may also be used to model timing delays
Assertions
Verilog also support timing check tasks to flag violations during simulation
These can be added to code with sequential logic
$hold (reference_event, data_event, limit[,notifier]) ;

Assertion violations are detected during simulation and reported

 XXVI. Dynamic vs Static Timing Analysis; Functional vs
Lecture 13 – Timing Analysis
Timing Verification
I. References

II. ASIC vs FPGA Design Flow Functional simulation and verification refers to verifying logical descriptions, including Boolean
expressions and register transfers
III. Synthesis
Timing verification refers to making sure that all timing requirements, external and internal (setup,
IV. Packing hold, etc..) are satisfied
V. Place and Route Dynamic Timing Analysis refers to analysis of timing by simulating the system with inputs and
examining the resulting waveforms.
VI. Timing Analysis and Post-
Place-and-Route simulation Static timing analysis uses no data and does not use a simulation – is just analyzes the structure
A timing analysis tool stores delays in a separate file Standard Delay Format SDF file along side the
VII. FPGA vs ASIC Tools
post place and route netlist
VIII. Static Timing Analysis

IX. Timing Analysis Concepts

XXVII. Review Static vs Dynamic
X. Clock Period Constraint

XI. Clock Domain Defined by Dynamic timing analysis and functional simulation each require well-selected input sequences
Seq. Elements These are called test-vectors. Static Timing analysis uses no test vectors.

XII. Setup and Hold Times

Dynamic timing analysis is sometimes combined with functional simulation while static timing
analysis can not
XIII. Clock Skew
Though Dynamic Timing and Functional Analysis use an event driven simulation which is much
XIV. Positive Clock Skew faster than SPICE-level “analog” circuit simulation, Static Timing Analysis is much faster and is used

XV. Negative Clock Skew during place and route iterations.

Static timing analysis is more straight forward with one clock domain, though can be extended to
XVI. Setup Timing Slack in
handle multiple clock domains. Dynamic timing analysis can automatically handle multiple clock
Critical Path
domains.
XVII. Setup Time Analysis
(slack)

XVIII. Hold Time Analysis and

Slack

XIX. Unconstrained Paths

XX. Related Clock Domains

XXI. Multicycle Paths

XXII. False Paths

XXIII. Asynchronous Signals

(e.g. Async Clear)

XXIV. Dynamic Timing Analysis

XXV. Dynamic Timing Analysis

using Event-Driven Simulation

XXVI. Dynamic vs Static Timing

Analysis; Functional vs Timing
Verification

XXVII. Review Static vs

Dynamic