COUNTERS

• Counter is basically used to count the number of clock pulses applied to a flip-
flop. It can also be used for Frequency divider, time measurement, frequency
measurement, distance measurement, and also for generating square waveforms.
• Counters are broadly divided into synchronous and asynchronous counter.

1. Synchronous Counter is a sequential circuit that generates a count sequence of 4

bits with a single clock signal. The count sequence consists of a series of binary
values that repeat after reaching the maximum count value.

RTL Code and Testbench

module up_down_counter(input clk, reset,up_down, output[3:0] counter);

reg [3:0] counter_up_down;
always @(posedge clk)
begin
if(reset)
counter_up_down <= 4'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 4'd1;
else
counter_up_down <= counter_up_down - 4'd1;
end
assign counter = counter_up_down;
endmodule

Testbench

module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;
up_down_counter dut(clk, reset,up_down, counter);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule

2. Ripple counter-Asynchronous Counter

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 • It is a cascaded arrangement of flip-flops where the output of one flip-flop drives
the clock input of the following flip-flop.
• A n-bit ripple counter can count up to 2n states. It is also known as MOD n counter.
It is known as ripple counter because of the way the clock pulse ripples its way
through the flip-flops.

RTL Code and Testbench

module ripplecounter(clk,rst,q);
input clk,rst;
output [3:0]q;
tff tf1(q[0],clk,rst);
tff tf2(q[1],q[0],rst);
tff tf3(q[2],q[1],rst);
tff tf4(q[3],q[2],rst);
endmodule

module tff(q,clk,rst);
input clk,rst;
output q;
wire d;
dff df1(q,d,clk,rst);
not n1(d,q);
endmodule

module dff(q,d,clk,rst);
input d,clk,rst;
output q;
reg q;
always @(posedge clk or posedge rst)
begin
if(rst) q=1'b0;
else q=d;
endripplecounter
endmodule

Testbench

module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;
up_down_counter dut(clk, reset,up_down, counter);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
2
#200;
up_down=1;
end
endmodule

SHIFT REGISTERS
A shift register is a type of digital circuit that can store and shift data in a sequential
manner. It is a cascade of flip-flops, where the output of one flip-flop is connected to the
input of the next flip-flop. The data is shifted from one flip-flop to the next on every clock
cycle, allowing the circuit to delay or store the data. The 4-bit shift register is shown
below.

Types of Shift Registers

a. SISO (Serial in Serial out Register)

The SISO shift register circuit accepts serial data on its input pin and shifts it out serially
on its output pin. The number of bits that can be shifted out before the next bit arrives
depends on the speed of the clock signal that controls the operation of the shift register.

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RTL Code:
module sisomod(clk, rst, si, so);
input clk,si,rst;
output so;
reg so;
reg [3:0] tmp;

always @(posedge clk )

begin
if (rst==1)
tmp <= 4'b0000;
else
tmp <= tmp << 1;
tmp[0] <= si;
so<=tmp[3];
end
endmodule

Testbench code
module sisot_b;
reg clk;
reg rst;
reg si;
wire so;

sisomod uut (.clk(clk), .rst(rst),.si(si),.so(so));

initial begin
clk = 0;
4
si = 0;
rst=1'b1;
#5 rst=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'b0;
#10 si=1'b1;
end

always #5 clk = ~clk;

initial #100 $stop;

initial
$monitor ("[%0tns] clk=%0b rst=%0b si=0x%0h so=%0b", $time, clk,rst, si,so);
endmodule

b. SIPO (Serial in Parallel out Register)

In this type of shift register, the input data is given bit by bit serially. For each clock pulse,
the input data at all the FFs can be shifted by a single position. The o/p at every flip-flop
can be received parallel.

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RTL Code:
module sipomod(clk,clr,si,pout);
input clk,si,clr;
output [3:0] pout;
reg [3:0] tmp;

always @(posedge clk )

begin
if (clr==1)
tmp <= 4'b0000;
else
tmp <= tmp << 1;
tmp[0] <= si;
so<=tmp;
end
endmodule

Testbench code
module sisot_b;
reg clk;
reg clr;
reg si;
wire so;

sipomod uut (.clk(clk), .clr(clr),.si(si),.pout(pout));

initial begin
clk = 0;
si = 0;
clr=1'b1;
#5 rst=1'b0;
#10 si=1'b1;
#10 si=1'b0;
#10 si=1'b0;
#10 si=1'b1;
end

always #5 clk = ~clk;

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 initial #100 $stop;

initial
$monitor ("[%0tns] clk=%0b clr=%0b si=%0b pout=0x%0h ", $time, clk,clr, si,pout);
endmodule

FLIP FLOPS

JK Flipflop- RTL Code and Testbench

module jkff(clk, reset ,j , k, q,qb);

input clk, reset, j, k;
output reg q,qb;
always @ (posedge clk)
begin
if(reset)
q <= 0;
else begin
case({j,k})
2'b00:
q <= q;
2'b01:
q <= 0;
2'b10:
q <= 1;
2'b11:
q <= ~q;
default:
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 q <= q;
endcase
end
qb<=~q;
end

endmodule
Testbench

module tb_jk;
reg j,k,clk,reset;
wire q,qb;
jkff n1(clk, reset, j, k, q,qb);
always
#5 clk=~clk;
initial
begin
clk=0;
j=0; k=0;
# 10 k=1;
#10 j=1;k=0;
#10 j=1;k=1;
#20 $finish
end
endmodule

SR Flipflop- RTL Code and Testbench

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module SR_flipflop (
input clk, rst,
input s,r,
output reg q,
output qb
);
always@(posedge clk) begin
if(!rst) q <= 0;
else begin
case({s,r})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= 1'bx; // Invalid inputs
endcase
end
end
assign qb = ~q;
endmodule

Testbench

module tb_sr;
reg s,r,clk,rst;
wire q,qb;
SR_flipflop n1(clk, rst, s, r, q,qb);
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always
#5 clk=~clk;
initial
begin
clk=0;
s=0; r=0;
# 10 r=1;
#10 s=1;s=0;
#10 s=1;r=1;
#20 $finish
end
endmodule

T Flipflop- RTL Code and Testbench

module tff (
input clk, rst,
input t,
output reg q,
output qb
);

always@(posedge clk) begin

if(!rst) q <= 0;
else begin
q <= (t?~q:q);
end
end
assign qb= ~q;
endmodule

Test Bench:
module tfftb;
reg t,clk,rst;
wire q,qb;
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tff t1(.t(t),.clk(clk),.rst(rst),.q(q),.qb(qb));
initial
begin
clk=1’b0;
always
#5 clk=~clk;
rst=1’b1;
#20 rst=1’b0; t=1’b0;
#10 t=1’b1;
end
endmodule

Mealy and Moore Type Finite State Machines

There are two basic ways to design clocked sequential circuits. These are using:
1. Mealy Machine
2. Moore Machine.

Mealy Machine

▪ In a Mealy machine, the outputs are a function of the present state and the
value of the inputs as shown in Figure 1.
▪ Accordingly, the outputs may change asynchronously in response to any
change in the inputs.

Figure 1: Mealy Type Machine

Mealy Machine
▪ In a Moore machine the outputs depend only on the present state as shown in
Figure 2.
▪ A combinational logic block maps the inputs and the current state into the
necessary flip-flop inputs to store the appropriate next state just like Mealy
machine.
▪ However, the outputs are computed by a combinational logic block whose
inputs are only the flip-flops state outputs.

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 ▪ The outputs change synchronously with the state transition triggered by the
active clock edge.

Figure 2: Moore Type Machine

Meal sequence detector for 101

RTL Code
module mealyfsm(
input clk,rst,x,
output reg y
);
parameter s0=2'b00;
parameter s1=2'b01;
parameter s2=2'b10;
parameter s3=2'b11;
reg [1:0] cst,nst;

always@(posedge clk)
begin
if(rst)
begin
y=0;

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nst=s0;
cst=s0;
end
else
//begin
cst=nst;
//end

//always@(cst,x)
//begin
case(cst)
s0:if (x==1)
begin
y=0;
nst=s1;
end
else
begin
y=0;
nst=s0;
end
s1:if (x==1)
begin
y=0;
nst=s1;
end
else
begin
y=0;
nst=s2;
end
s2:if (x==1)
begin
y=1;
nst=s1;
end
else
begin
y=0;
nst=s0;
end
endcase
end

endmodule

Testbench

module mealytb;

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 // Inputs
reg clk;
reg rst;
reg x;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

moorefsm uut (
.clk(clk),
.rst(rst),
.x(x),
.y(y)
);

initial begin

clk = 0;
rst = 1;
x = 0;
#10;
rst=0;
#10;

x=1;
#10;

x=0;
#10;

x=1;
#10;
end
always
#5 clk=~clk;

endmodule

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