/tools1/mentor/tessent_2022.1/bin/tessent -shell -dofile scan_insertion.

tcl -
logs ../logs/scan.log -replace
// Tessent Shell 2022.1-p1 Sat Jul 09 21:03:47 GMT 2022
// Unpublished work. Copyright 2022 Siemens
//
// This material contains trade secrets or otherwise confidential
// information owned by Siemens Industry Software Inc. or its affiliates
// (collectively, "SISW"), or its licensors. Access to and use of this
// information is strictly limited as set forth in the Customer's
// applicable agreements with SISW.
//
// Siemens software executing under x86-64 Linux on Tue Jul 30 16:06:45 IST 2024.
// 64 bit version
// Host: sjrvlsiserver2.tessolve.com (1031674 MB RAM, 894011 MB Swap)
//
// Note: License will be released if tool is idle for 360 minutes
// command: set_context dft -scan -design_id gate
// command: # You must Specify the same output directory you used in the second
DFT passes (edt_occ insrted)
// command: # copy the edt_occ tsdb_outdir to here and specify this dir as output
dir here
// command: #set_tsdb_output_directory ./outputs/tsdb_outdir_dsplx7_occ_edt_mbist
// command: set_tsdb_output_directory ../tsdb_outdir_v98_v3/
// command: # Read mdt Library
// command: read_cell_library
/project1/metanoia_tools/tsmc_library/*/*/TSMCHOME/digital/Front_End/mentor_dft/*/
*.mdt
// Reading DFT Library file
/project1/metanoia_tools/tsmc_library/tcbn12ffcllbwp16p90cpdlvt_100d/
V270001_20230914/TSMCHOME/digital/Front_End/mentor_dft/
tcbn12ffcllbwp16p90cpdlvt_100c/tcbn12ffcllbwp16p90cpdlvt.mdt
// Finished reading file
/project1/metanoia_tools/tsmc_library/tcbn12ffcllbwp16p90cpdlvt_100d/
V270001_20230914/TSMCHOME/digital/Front_End/mentor_dft/
tcbn12ffcllbwp16p90cpdlvt_100c/tcbn12ffcllbwp16p90cpdlvt.mdt
// Reading DFT Library file
/project1/metanoia_tools/tsmc_library/tcbn12ffcllbwp20p90cpdlvt_100d/
V270001_20230914/TSMCHOME/digital/Front_End/mentor_dft/
tcbn12ffcllbwp20p90cpdlvt_100c/tcbn12ffcllbwp20p90cpdlvt.mdt
// Finished reading file
/project1/metanoia_tools/tsmc_library/tcbn12ffcllbwp20p90cpdlvt_100d/
V270001_20230914/TSMCHOME/digital/Front_End/mentor_dft/
tcbn12ffcllbwp20p90cpdlvt_100c/tcbn12ffcllbwp20p90cpdlvt.mdt
// Reading DFT Library file
/project1/metanoia_tools/tsmc_library/tphn12ffcll_18od33sdio_150a/
V270001_20230914/TSMCHOME/digital/Front_End/mentor_dft/
tphn12ffcll_18od33sdio_150a/tphn12ffcll_18od33sdio.mdt
// Finished reading file
/project1/metanoia_tools/tsmc_library/tphn12ffcll_18od33sdio_150a/
V270001_20230914/TSMCHOME/digital/Front_End/mentor_dft/
tphn12ffcll_18od33sdio_150a/tphn12ffcll_18od33sdio.mdt
// Reading DFT Library file
/project1/metanoia_tools/tsmc_library/tphn12ffcll_18osc_100c/V270001_20230914/
TSMCHOME/digital/Front_End/mentor_dft/tphn12ffcll_18osc_100a/tphn12ffcll_18osc.mdt
// Finished reading file
/project1/metanoia_tools/tsmc_library/tphn12ffcll_18osc_100c/V270001_20230914/
TSMCHOME/digital/Front_End/mentor_dft/tphn12ffcll_18osc_100a/tphn12ffcll_18osc.mdt
// Reading DFT Library file
/project1/metanoia_tools/tsmc_library/tphn12ffcllgv18e_150a/V270001_20230914/
TSMCHOME/digital/Front_End/mentor_dft/tphn12ffcllgv18e_140a/tphn12ffcllgv18e.mdt
// Finished reading file
/project1/metanoia_tools/tsmc_library/tphn12ffcllgv18e_150a/V270001_20230914/
TSMCHOME/digital/Front_End/mentor_dft/tphn12ffcllgv18e_140a/tphn12ffcllgv18e.mdt
// command: #memory ATPG model - fastscan
// command: read_cell_library
/project1/metanoia_cobra/TE10833/design_lib_rev_97/cobra/chip/ts6n12ffcllulvtb32x25
6m1b_130b/DFT/ATPG/ts6n12ffcllulvtb32x256m1b_130b_fscan.lib
// Reading DFT Library file
/project1/metanoia_cobra/TE10833/design_lib_rev_97/cobra/chip/ts6n12ffcllulvtb32x25
6m1b_130b/DFT/ATPG/ts6n12ffcllulvtb32x256m1b_130b_fscan.lib
// Finished reading file
/project1/metanoia_cobra/TE10833/design_lib_rev_97/cobra/chip/ts6n12ffcllulvtb32x25
6m1b_130b/DFT/ATPG/ts6n12ffcllulvtb32x256m1b_130b_fscan.lib
// command: read_cell_library
/project1/metanoia_cobra/TE10833/design_lib_rev_97/cobra/chip/ts1n12ffcllsbsvtc256x
96m4swb_130c/DFT/ATPG/ts1n12ffcllsbsvtc256x96m4swb_130c_fscan.lib
// Reading DFT Library file
/project1/metanoia_cobra/TE10833/design_lib_rev_97/cobra/chip/ts1n12ffcllsbsvtc256x
96m4swb_130c/DFT/ATPG/ts1n12ffcllsbsvtc256x96m4swb_130c_fscan.lib
// Finished reading file
/project1/metanoia_cobra/TE10833/design_lib_rev_97/cobra/chip/ts1n12ffcllsbsvtc256x
96m4swb_130c/DFT/ATPG/ts1n12ffcllsbsvtc256x96m4swb_130c_fscan.lib
// command: #if any third party IP to add into scan chain. Ex: tried party OCC
// command: #Specify the "location" of the TCD Scan file that describes the OCC's
scan segment
// command: #set_design_sources -format tcd_scan -Y
./tsdb_out_dpd/instruments/dpd_cobra_dpd_occ.instrument -extension tcd_scan
// command: # Read synthesized netlist
// command: #read_verilog
/projects_export/metanoia_cobra/TE7389/Cobra_chip_ver47/lx7_scan/scan_exp/inputs/
Xm_LX7_COBRA_RC1Xtmem_hacked.v
// command: #read_verilog ./inputs/Xm_LX7_COBRA_RC1Xtmem.pass1.v.gz
// command: read_verilog
/dft/ramkrishna10843/release/release_customer/dft/REV_99/NETLIST_for_DFT2/
dpd_m.v.gz
// command: #read data from edt_insertion pass : use the same gate_id used for
second DFT insertion pass
// command: read_design dpd -design_id rtl2 -no_hdl -verbose
// sub-command: read_icl
../tsdb_outdir_v98_v3/dft_inserted_designs/dpd_rtl2.dft_inserted_design/dpd.icl -
skip_child_blocks -no_notes
// sub-command: source
../tsdb_outdir_v98_v3/dft_inserted_designs/dpd_rtl2.dft_inserted_design/dpd.pdl
// sub-command: read_core_descriptions
../tsdb_outdir_v98_v3/dft_inserted_designs/dpd_rtl2.dft_inserted_design/dpd.tcd
// command: set_module_matching_options -suffix {{_[0-9]+_DPD}} -append -regexp
// command: #add_black_boxes -auto
// command: #set_design_sources -format tcd_scan -y
/dft/navya10791/Cobra_chip_ver47/netlist_egis/scan_exp/design -extensions tcd_scan
// command: #set top module and elab
// command: set_current_design dpd
// Note: 3 duplicate cell library models were read. The last model read of the
same name was kept.
// To see detailed messages per duplicate model, issue
'set_cell_library_options -report_duplicate_models on'
// before issuing 'read_cell_library'.
// Warning: 103 cases: Net in netlist not connected
// Note: Issue set_current_design with the -show_elaboration_warnings option to
see more details about previous warnings
// ---------------------------------------------------------------------------
// Begin ICL elaboration and checking.
// -----------------------------------
// ICL elaboration completed, CPU time=0.33 sec.
// ---------------------------------------------------------------------------
// Warning: Primary input 'tessent_persistent_cell_shift_capture_clock/Q_pport' is
added at pin '/tessent_persistent_cell_shift_capture_clock/Q'
// Note: Specified test clock connection point
tessent_persistent_cell_shift_capture_clock/Q will be mapped to internal clock
tessent_persistent_cell_shift_capture_clock/Q_pport
// command: #add_input_constraints scan_mode -C1
// command: set_system_mode insertion
// command: intercept_connection clk_div2g_inst/scan_mode -cell_function_name
inverter
// command: intercept_connection clk_div2g_inst/power_down_n -cell_function_name
or -input2 scan_mode
// command: intercept_connection clk_div2g_inst/power_down_n -cell_function_name
or -input2 mbist_mode
// command: intercept_connection clk_div2g_inst/rst_n -cell_function_name or -
input2 scan_mode
// command: intercept_connection clk_div2g_inst/rst_n -cell_function_name or -
input2 mbist_mode
// command: report_dft_signals > ../reports/dft_signals.rpt
// command: #set_system_mode setup
// command: #After drc check following;
// command: #1. check total flops in log : Begin scan chain identification
process, memory elements = 40730
// command: #2. check total scan flops in log : Begin shift register
identification for 40196 sequential library cells
// command: #3. check non-scan flops : report_drc_rules D5 : 534 sequential
library cells are treated as non-scan
// command: #add_nonscan_instances rst_sync
// command: #added for cg_fix - change1
// command: #set_system_mode insertion
// command: #source ./cgc_connection.tcl
// command: set_system_mode setup
// command: add_nonscan_instances -instances clk_div2g_inst
// command: add_nonscan_instances -instances clk_gated_inst
// command: add_nonscan_instances -modules s_clk_ctrl_0_DPD
// command: add_nonscan_instances -modules s_clk_ctrl_1_DPD
// command: add_nonscan_instances -instances rst_sync
// command: add_nonscan_instances -instances rst_sync_div2
// command: check_design_rules
// Warning: Rule FN1 violation occurs 143 times
// Warning: Rule FN4 violation occurs 50996 times
// Flattening process completed, cell instances=1004533, gates=2263609,
PIs=587+5(pseudo ports), POs=568, CPU time=22.85 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses.
// --------------------------------
// Learning completed, CPU time=20.19 sec.
// ---------------------------------------------------------------------------
// Begin scan chain identification process, memory elements = 50996,
// sequential library cells = 50996.
// ---------------------------------------------------------------------------
// Begin simulation of test_setup procedure with 126 cycles.
// Simulation of test_setup procedure completed, CPU time=0.5 sec.
// Begin simulation of auto-generated load_unload procedure.
// Simulation of load_unload procedure completed, CPU time=1.3 sec.
// Scan segment = /dpd_rtl1_tessent_sib_sti_inst/ltest_so successfully traced with
scan_cells = 7.
// Scan segment = /dpd_rtl2_tessent_occ_clk_gated_inst/scan_out successfully
traced with scan_cells = 3.
// Scan segment = /dpd_rtl2_tessent_occ_clk_div2g_inst/scan_out successfully
traced with scan_cells = 3.
// Scan segment = /dpd_rtl2_tessent_occ_pclk_inst/scan_out successfully traced
with scan_cells = 3.
// 3 external shadows that use shift clocking have been identified.
// 16 scan cells have been identified in 4 scan segments.
// Longest scan segment has 7 scan cells.
// Warning: 4 edge-triggered clock ports set to stable high. (D7)
// Note: Adding 1 functional clock.
// Warning: Model 'LNQD1BWP20P90CPDLVT' has no muxscan scan equivalent and is
treated as nonscan model
// ------------------------------------------------------------------------------
// 2448 sequential library cells are treated as non-scan.
// ------------------------------------------------------------------------------
// 2172 sequential library cells missing mux-scan equivalent.
// 71 sequential library cells below hard module.
// 205 sequential library cells defined non-scan.
// ---------------------------------------------------------------------------
// Begin scannability rules checking for 48526 sequential library cells
// and 4 scan segments. The scan segments contain 22 additional cells.
// ---------------------------------------------------------------------------
// Note: There were 33 S7 violations (Potentially scannable cell that is not in
the clock path is driven by a constant value).
// 48526 sequential library cells and 4 scan segments identified as scannable.
// ---------------------------------------------------------------------------
// Begin transparent latch checking for 2185 latches.
// ---------------------------------------------------------------------------
// Warning: 1 latches not transparent due to unobservable. (D6)
// Number transparent latches = 2184.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
// ---------------------------------------------------------------------------
// 9 scan clock/set/reset lines have been identified.
// All scan clocks successfully passed off-state check.
// 12475 sequential cells passed clock stability checking.
// There were 60 clock rule C3 fails (clock may capture data affected by its
captured data).
// Warning: There were 1025 clock rule C4 fails (clock may be affected by its
captured data).
// Note: Trailing edge triggered device can capture data affected by leading edge.
// ---------------------------------------------------------------------------
// 2447 non-scan memory elements are identified.
// ---------------------------------------------------------------------------
// 96 non-scan memory elements are identified as TIE-0. (D5)
// 29 non-scan memory elements are identified as TIE-1. (D5)
// 1 non-scan memory element is identified as TIE-X. (D5)
// 137 non-scan memory elements are identified as INIT-X. (D5)
// 2184 non-scan memory elements are identified as TLA. (D5)
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
// Begin RAM rules checking.
// ---------------------------------------------------------------------------
// Warning: All 8384 RAMs are unobservable. (A14)
// Warning: All 8384 RAMs cannot write. (A16)
// RAM Summary Results: #RAMs = 8384 #TieXs = 0 #testable = 0 #data_hold =
8384
// Test Capability: #read_only = 0 #ram_sequential = 8384
#seq_transparent = 0
// Write stability: #unstable_control = 0 #unstable_load = 0
// Read stability: #unstable_control = 0 #unstable_load = 0
// ---------------------------------------------------------------------------
// Begin shift register identification for 48526 sequential library cells.
// ---------------------------------------------------------------------------
// Number of shift register flops recorded for scan insertion: 229 (0.45%)
// Number of shift registers recorded for scan insertion: 113
// Longest shift register has 3 flops.
// Shortest shift register has 2 flops.
// Potential number of nonscan flops to be converted to scan cells: 0
// Potential number of scan cells to be converted to nonscan flops: 94
// Note: The user did not specify a top level control signal for the internal
clock net "tessent_persistent_cell_shift_capture_clock/Q".
// However, a sensitized path was found between the top level clock pin
named "/test_clock"
// and the internal net. The top level clock pin "/test_clock" will be used
in the ATPG setup files.
// Number of targeted sequential library cells = 48526
// command: report_clocks
User-defined Clocks (9):
=========================

Sync and Async Source Clocks

============================
----------------------------------------------------- -------------------
--------- -------- ----------------
-----------------------------------------------------------------------------
Name Label Off
State Internal Other Properties Pin(s)

----------------------------------------------------- -------------------
--------- -------- ----------------
-----------------------------------------------------------------------------
'test_clock' test_clock
0 No

'tessent_persistent_cell_shift_capture_clock/Q_pport' ck0
0 Yes 'tessent_persistent_cell_shift_capture_clock/Q'

'ijtag_tck' ijtag_tck
0 No

'inferred_occ_clock0' inferred_occ_clock0
0 Yes Capture only
'dpd_rtl2_tessent_occ_clk_gated_inst/tessent_persistent_cell_clock_out_mux/y'
'inferred_occ_clock1' inferred_occ_clock1
0 Yes Capture only
'dpd_rtl2_tessent_occ_clk_div2g_inst/tessent_persistent_cell_clock_out_mux/y'
'inferred_occ_clock2' inferred_occ_clock2
0 Yes Capture only
'dpd_rtl2_tessent_occ_pclk_inst/tessent_persistent_cell_clock_out_mux/y'
'inferred_occ_clock3' inferred_occ_clock3
0 Yes Capture only
'dpd_rtl1_tessent_sib_sti_inst/tessent_persistent_cell_ltest_clock_mux/y'
 'pclk' pclk
0 No

'clk' clk
0 No

// command: report_input_constraints > ../reports/input_constraints.rpt

// command: # Exclude the EDT channel in and out ports from wrapper chain
analysis. # The ijtag_* edt_update ports are automatically excluded
// command: set_wrapper_analysis_options -exclude_ports [ get_ports
{*_edt_channels_*} ]
// command: # To force insertion of dedicated wrapper cell use the following
command
// command: # set_dedicated_wrapper_cell_options on -ports {.... }
// command: #set_dedicated_wrapper_cell_options on <reset ports>
// command: # Perform wrapper cell analysis
// command: analyze_wrapper_cells
//
// Port information and user constraints:
// --------------------------------------
// Input ports: 587 total, 14 ignored, 2 excluded, 0 off,
0 on, 571 auto
// Output ports: 568 total, 1 ignored, 2 excluded, 0 off,
0 on, 565 auto
//
//
// Wrapper analysis summary:
// -------------------------
// 0 output ports required a dedicated wrapper cell.
// 532 input ports required a dedicated wrapper cell.
// 607 flip-flops were converted into output shared wrapper cells.
// 646 flip-flops were converted into input shared wrapper cells.
// Use report_wrapper_cells for more details.
//
// command: report_wrapper_cells -Verbose > ../reports/wrapper_cells.rpt
// command: report_drc_rules D5 > ../reports/non_scan_cells.rpt
// command: # Find edt_instance
// command: set edt_instance [get_instances -of_icl_instances [get_icl_instances -
filter tessent_instrument_type==mentor::edt]]
// command: # Specify different modes (internal and external) of the chains that
need to be stitched
// command: # The type internal/external and enable_dft_signal are inferred from
the registered DFT signals(int_mode and ext_mode)
// command: #change2
// command: add_scan_mode int_mode -edt_instances $edt_instance
// Reading core description file
../tsdb_outdir_v98_v3/instruments/dpd_rtl2_edt.instrument/dpd_rtl2_tessent_edt_c1.t
cd
// Setting the chain count to the number of specified scan connections (196).
// Automatically inferring '-enable_dft_signal int_mode' from the specified scan
mode name.
// Automatically inferring '-type internal' from the scan mode type (internal)
associated with the enable DFT signal 'int_mode'.
// command: #add_scan_mode ext_mode -chain_count 2
// command: add_scan_mode ext_mode -chain_length 300
// Automatically inferring '-enable_dft_signal ext_mode' from the specified scan
mode name.
// Automatically inferring '-type external' from the scan mode type (external)
associated with the enable DFT signal 'ext_mode'.
// command: # Before scan insertion you can analyze the different scan modes and
scan # chains
// command: analyze_scan_chains
// Chain allocation of 'int_mode' mode completed:
// 196 distributed chains of sizes ranging from 250 to 251
// Chain allocation of 'ext_mode' mode completed:
// 6 distributed chains of sizes ranging from 299 to 300
// command: set_gate_report -clock_domains_in_capture_cycles on
// command: report_clock_gating > ../reports/clk_gaters.rpt
// command: report_drc_rules S7 > ../reports/S7.rpt
// command: report_drc_rules > ../reports/drc.rpt
// command: #master - the primary memory element of a scan cell => similar to
report seq cells
// command: report_gates -type master -summary
// Total number of master gates = 48542

// command: report_gates -type master > ../reports/report_gates_type_master.rpt

// command: ## convert normal flops to scan flops and connect scan chains and
write the scan inserted design into the TSDB
// command: insert_test_logic
=============================
Test Logic Insertion Summary:
=============================

Structural Data:
----------------
Added top-level port count: 2
Added instance count: 5074

Logical Data:
-------------
Added clock gater control logic count: 452
Added input wrapper logic count: 1824
Added output wrapper logic count: 1214
Added pipelining logic count: 10
Added retiming logic count: 209
Added scan chain count (int_mode): 196
Added scan chain count (ext_mode): 6

// Warning: Flattened model deleted.

//
// Writing out netlist and related files in
../tsdb_outdir_v98_v3/dft_inserted_designs/dpd_gate.dft_inserted_design
// command: #stop
// command: #reports scan chains
// command: report_scan_chains > ../reports/scan_chains.rpt
// command: #reports flops in scan chains
// command: report_scan_cells > ../reports/scan_cells.rpt
// command: #report_clock_gating > ./reports/clk_gaters.rpt
// command: #report non-scan elements
// command: ##write atpg setup
// command: #write_atpg_setup ../atpg/scan_edtoccmodes_setup -replace
// command: extract_sdc
// Note: Changing the context to 'patterns -ijtag'.
// Writing SDC file:
../tsdb_outdir_v98_v3/dft_inserted_designs/dpd_gate.dft_inserted_design/dpd.sdc

// command: set_system_mode setup

// command: #exit