SRAM MEMORY

CELL
Presented by
P.ASHOK KUMAR
What is a
Memory?
• Memory in computing refers to
hardware devices that store and
retrieve data.
• It allows the CPU to access data
and instructions needed for
processing and operation.
History of Memory
• Early Memory Devices (1940s-1950s):
• Punched Cards and Magnetic Tape: Early forms of
memory, used for input and storage.
• ENIAC (1945): One of the first computers with minimal
memory (vacuum tubes) and used punch cards.
• Magnetic Core Memory (1950s-1960s):
• First Random Access Memory (RAM).
• Magnetic core memory was made of tiny magnetic rings
that stored data using magnetic fields.
Introduction of Semiconductor memory
• The transistor-based integrated circuits (ICs)
replaced magnetic core memory, enabling smaller,
faster, and more reliable memory systems.
• Development of SRAM (1960s-1970s):
• Static RAM (SRAM) was introduced as a faster
alternative to DRAM. Unlike DRAM, SRAM doesn’t
require refreshing, but it’s more expensive and uses
more transistors.
Memory
Arrays
Working Principle of
SRAM
• How SRAM Works:
▪ SRAM stores data using a flip-flop circuit, which holds one bit of
data in two stable states.
▪ A 6-transistor SRAM cell consists of:
• 4 transistors to form a cross-coupled pair that stores data.
• 2 transistors used to access the data for read or write
operations.
• Key Features:
• No Need for Refreshing: Unlike DRAM, SRAM does not need to be refreshed to
maintain data.
• Faster Access Time: SRAM offers faster read and write speeds than DRAM
SRAM VS DRAM
 Faster than DRAM due to
Speed: direct access with no
refreshing required.

Higher power consumption in

idle states compared to DRAM,
Power Consumption: but less power is consumed
when actively accessed.
Characteristics
of SRAM Lower storage capacity due
Size and Density: to higher number of transistors
per bit.

More durable than DRAM as it

Reliability: does not rely on capacitors.
 • Cache Memory:
• L1, L2, and L3 caches in CPUs to store frequently
used data.
• Embedded Systems:
• Used in microcontrollers, communication devices,
and automotive systems.

Applications • Networking Equipment:

• Found in routers, switches, and firewalls to store
of SRAM routing tables and other data.
• Graphics Memory:
• Used in frame buffers and GPU memory.
• High-Speed Buffers:
• Employed in systems that require rapid data access,
such as digital signal processors (DSPs).
SRAM
Architecture

• 6-Transistor SRAM Cell: The basic

unit of SRAM consists of 4
transistors for data storage and 2 for
read/write access.
• Flip-Flop Mechanism: Data is
stored as binary values in stable
states, and access is provided
through bit and word lines.
Basic 6-Transistor
SRAM Cell:
• The most common SRAM cell design, consisting of 6 transistors
(6T).
• 2 Cross-Coupled Inverters (made of 4 transistors) form a latch
that stores the data.
• 2 Access Transistors are connected to the bit lines for data
read/write.
• Working:
• The two inverters in the SRAM cell hold the data (a binary 0 or 1) in a
stable state.
• Read Operation: The bit lines are connected to the cross-coupled
inverters through access transistors, allowing data to be read out.
• Write Operation: Data is written by pulling the appropriate bit line
high or low, which forces the cell to change its stored value.
Register Files:

Register Files are arrays of SRAM cells that are used to store data that is
actively used by the CPU, like general-purpose registers.

Register files are essential for quick access to data in CPU operations (like
holding intermediate results during computations).

Organized in words (multiple bits per register).

Key Features: Each word is typically 32-bits or 64-bits wide in modern processors.
The CPU can access any register in the file via a register address.

Typically, a register file consists of multiple rows of SRAM cells, where each
row is a register.
Structure: Registers are often grouped together to allow parallel access to multiple
values.
Word Line Decoder:
• Word Line Decoder is responsible for selecting
which row in the register file or SRAM array is
activated during a read or write operation.
• Function:
o The decoder takes the address input from the
CPU and decodes it to activate the
corresponding word line.
o When a specific word line is selected, it
connects the access transistors of the selected
SRAM cells to the bit lines, allowing the data to
be read or written.
Sense Amplifier
• The Sense Amplifier is used in SRAM to amplify small voltage differences on the bit
lines during read operations.
• Purpose:
• During a read, the bit lines (connected to the SRAM cells) will have a small
difference in voltage (depending on the stored value, 0 or 1).
• The sense amplifier detects this small voltage difference and amplifies it to a full
logic level (either high or low) so the data can be properly read.
How It Works
• When a word line is activated, the
stored value in the SRAM cell (0 or 1)
is transferred to the bit lines.
• The sense amplifier latches onto
the difference in voltage between
the bit lines and amplifies the signal
to full logic level.
• This ensures that even a small
voltage difference is readable as a
high (1) or low (0) binary value.
Data Multiplexers
• Data Multiplexers are used to select and route the
data between the SRAM array and the CPU or other
components in the system.
• Function:
• The multiplexer allows the data bus to read or write
data to/from the correct register in the register file
or SRAM array.
• It selectively routes data between different SRAM
rows, CPUs, or memory controllers based on the
operation.
Working
• During a write operation, the
multiplexer selects the correct data
input and routes it to the appropriate
SRAM cell.
• During a read operation, the
multiplexer routes the data from the
selected SRAM cell or register back
to the data bus for the CPU to use.
SRAM Layout Guidelines
• General Design Principles
• Symmetry: Maintain symmetry in cell layout, bitlines, and wordlines to ensure balanced
performance, minimize delays, and reduce power consumption.
• Compactness: Minimize SRAM cell area without compromising stability and performance.
Consider 4T or 5T designs for area efficiency.
• Bitline and Wordline Layout
• Bitlines: Minimize bitline capacitance and resistance to speed up access. Use wider bitlines
for lower resistance, but avoid excessive area.
• Wordlines: Ensure low wordline resistance and minimize wordline capacitance to reduce
access time. Keep routing short and wide.
• Crossing Avoidance: Avoid overlapping of bitlines and wordlines to prevent short circuits.
THANK YOU

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