Enabling Compact Modeling R&D Exchange

European Open Source PDK Initiative

Wladek Grabinski, IEEE EDS DL

MOS-AK (EU)

Rene Scholz, IHP

Leibniz Institute for High Performance Microelectronics
Frankfurt (Oder)

www.mos-ak.org
 Motivation: A call for Building Talent and Skills

[REF] EU Chips Act Drives Pan-European Full-Stack Innovation Partnerships

Plenary Session at ISSCC, FEB.20, 2023
Jo De Boeck, Executive VP and CSO, imec & KU Leuven, Belgium

www.mos-ak.org
 IHP Institute for High Performance Microelectronics

IHP Institute for High Performance Microelectronics

 IHP Open PDK & Open Tool Development

• IHP started on existing experiences from SkyWater PDK

<https://github.com/google/skywater-pdk
• IHP will offer an analog design flow, later RF design
• Quality should fulfill requirements for academic education
• Open Tools has to be improved, interface development is
crucial
• For a sustainable approach, we/IHP have to improve
capabilities to a level to support productive projects
• Secure long term funding for MPW and Foundry Service
• Achieve industrial/non-public funding
Digital Open Source Design Flow

● Yosys + ABC
● Magic
● Netgen
● CVC
● SPEF-Extractor
● OpenSTA
● KLayout
● Fast/TritonRoute
● TritonCTS
● other (?)
Analog/RF Open Source Design Flow

● KLayout-oriented flow
○ Layout design
○ Parameteric cells
○ Physical Verification
● QUCS-S, xschem
● ngspice, xyce
● OpenEMS
● other (?)
 OpenEMS ElectroMagnetic Solver
• 3D FDTD solution targeting RF EM simulations
• Model built by Python or Octave scripting
• Graphical viewer for model + mesh (CSXCAD)
• Some interfaces to EDA packages, but no KLayout
support yet
• No internal support for GDSII import, interface was
created
• using Python library gdspy
• S-Parameter output
• Useful tutorials for RF examples
• Possible issue:
– small residual energy at low frequency or DC
might create DC leakage in simulation results
– Mostly manual mesh definition
– No user-friendly GUI for IC designer
 QUCS-S Custom Library
with IHP OpenPDK Devices
 Iguana - Integrated Systems Laboratory
(ETH Zürich)

https://wiki.f-si.org/index.php?title=Industry-Grade_SystemVerilog_IPs_And_The_Open_Flow:_How_We_Synthesized_Iguana
 SAR – ADC Project
(JKU Linz)

Design of a 1.2MS/s Charge-Redistribution Non-Binary

SAR-ADC utilizing the Open-Source SKY130 PDK
https://github.com/iic-jku/SKY130_SAR-ADC1

• Transfer to open SG13G2 PDK in progress

• Mixed Signal capabilities of open PDK needed
• Both Design Projects can be used to benchmark
and optimize open PDK and open Tools

[Note] IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital
chip design
<https://github.com/iic-jku/iic-osic-tools>
 IHP Open PDK Roadmap
• Adjust to common goals for an open source design flow – to channel effort
• Leveraging community efforts, public funding and corporate contributions

• Initiate cooperation's and joint projects with open source community

• Demonstration of successful open source designs
• Demonstration of design training courses in academic institutions
• Support chip design possibilities for small commercial design projects
• Achieve a commercial successful project
 Acknowledgment
• The IHP PDK Team with Rene Scholz, Open PDK Project Lead
• ETH Zurich + JKU Linz + all the open source community
• German public founded projects:
– VE-HEP (16KIS1339K) https://elektronikforschung.de/projekte/ve-hep-1
– IHP Open130-G2 (16ME0852)
– https://www.elektronikforschung.de/projekte/ihp-open130-g2
– FMD-QNC (16ME0831)
https://www.elektronikforschung.de/projekte/fmd-qnc
– FMD-QNC with VDI/VDE (IHP PDK Workshop funding)
 FOSS EKV2.6 at GitHub

Wladek Grabinski1, Marcelo Pavanello2, Michelly de Souza2,

Daniel Tomaszewski3, Jola Malesinska3, Grzegorz Głuszko3, Matthias Bucher4,
Nikolaos Makris4, Aristeidis Nikolaou4, Ahmed Abo-Elhadid5, Marek Mierzwinski6,
Laurent Lemaitre7, Mike Brinson8, Christophe Lallement9, Jean-Michel Sallese10,
Sadayuki Yoshitomi11, Paul Malisse12, H.J. Oguey13, Stefan Cserveny13,
Christian C. Enz10, Francois Krummenacher10 and Eric Vittoz10
‘
1
MOS-AK Association (EU), 2 Centro Universitario FEI, Sao Bernardo do Campo (BR),
3
Institute of Electron Technology, Warsaw (PL), 4 Technical University of Crete, Chania (GR),
5
Mentor Graphics (USA), 6 Keysight Technologies (USA), 7 Lemaitre EDA Consulting,
8
London Metropolitan University (UK), 9 ICube, Strasbourg University (F), 10 EPFL Lausanne (CH),
11
Toshiba (J), 12 Europractice/IMEC (B), 13 CSEM S.A., Neuchatel (CH)
FOSS EKV2.6 Verilog-A
OUTLINE
□ Moore’s Law
□ FOSS Modeling/Simulation Flow
□ Development of the Compact Models
□ EKV v2.6 Model Structure
□ Testchip Layout
□ Parameter Extraction Methodology
□ Electrical Characterization
■ Pinch-off Voltage Characteristic
■ IV and CV Characteristic
■ 1/f Noise Characteristic
□ Model Implementation
■ ADMS
■ Qucs Benchmarks
■ FOSS EKV2.6 Verilog-A at https://github.com/ekv26/model
□ Summary

W.Grabinski et al. FOSS EKV2.6 Verilog-A at: ESSDERC 2 of 21

Moore’s Law

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 3 of 21

Moore’s Law (cont.)

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 4 of 21

FOSS Modeling/Simulation Flow

• Cogenda TCAD • Spice/Verilog-A • Ngspice

• DevSim TCAD Simulators • Qucs
• other • Verilog-A • Xyce
Standardization
EM Simulators • GnuCap
○ ADMS
• other
○ MAPP
• measurements
• parameterization
• other
W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 5 of 21
Development of the Compact Models
1000
BSIM4v4 BSIM6 BSIM
BULK
PSP
BSIM3v3
MM11v2 PSP 103.6
BSIM3v2 HiSIM 2.5.2

BSIM2 HiSIM 2.4.0

No. of Model Parameters

100 HSP28
BSIM3v3 BSIM4 PSP 103.6

BSIM BSIM3v2 MM11v2PSPBSIM6 BSIM

BSIM2 BULK
PCIM SP ACM
HSP28
LEVEL3 BSIM3v1 MM9 EKV3.01
BSIM EKV3.0
LEVEL2 EKV2.6
EKV
10
earlyEKV

LEVEL1

Including L,W,P scaling

Without scaling
1
1960 1970 1980 1990 2000 2010 2020
Years
□ Number of DC model parameters vs. the year of the introduction of the model
Most recent versions of the BSIM, EKV, HiSIM and PSP models are included
□ Significant growth of the parameter number that includes geometry (W/L) scaling

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 6 of 21

Development of the Compact Models
1000
BSIM4v4 BSIM6 BSIM
BULK
PSP
BSIM3v3
MM11v2 PSP 103.6
BSIM3v2 HiSIM 2.5.2

BSIM2 HiSIM 2.4.0

No. of Model Parameters

100 HSP28
BSIM3v3 BSIM4 PSP 103.6

BSIM BSIM3v2 MM11v2PSPBSIM6 BSIM

BSIM2 BULK
PCIM SP ACM
HSP28
LEVEL3 BSIM3v1 MM9 EKV3.01
BSIM EKV3.0
LEVEL2 EKV2.6
EKV
10
earlyEKV

LEVEL1

Including L,W,P scaling

Without scaling
1
1960 1970 1980 1990 2000 2010 2020
Years
□ Number of DC model parameters vs. the year of the introduction of the model
Most recent versions of the BSIM, EKV, HiSIM and PSP models are included
□ Significant growth of the parameter number that includes geometry (W/L) scaling
□ Independent MOSFET model development based on the roots of the semiconductor
physics and the design driven EKV modeling methodology
□ EKV preserves coherent charge-based framework for static/dynamic modeling
W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 7 of 21
EKV v2.6 Model Structure

Bulk-reference, symmetric model structure.

Drain current expression including drift and diffusion:

where:

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 8 of 21

EKV v2.6 Model Structure (cont.)
Physical model basis leads to accurate description of
transconductance-to-current ratio at all current levels allows
coherent derivation of all model quantities including static,
dynamic and noise modeling aspects.

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 9 of 21

 Testchip Layout in 180nm CMOS

Type of devices Parameters

n-channel MOSFETs W=0.24 μm; L=0.18 μm (min.size

p-channel MOSFETs devices)
T(N/P)1-14 W=3 μm; L=0.18, 0.24, 0.3, 0.4, 0.6, 1.0
μm
W=0.24, 0.3, 0.5, 1.0 μm; L=1.0 μm
W=10 μm; L=10 μm (max.size devices)
10 parallel fingers of W=5 µm, L=10 µm
W=50 µm, L=10 µm (wide devices)
CMOS inv. INV1 WN=0.24 μm, WP=0.24 μm, LN= LP =0.18
μm
CMOS ring osc. WN=0.24 μm, WP=0.24 μm, LN= LP =0.18
OSC1 μm
31 stages
n+-pwell, p+-nwell W=L=100 µ
diodes D(N/P)1-2 W=10 µm, L=100 µm (10 fingers)

Europractice is acknowledged for providing free access to UMC 180 nm

CMOS silicon and all corresponding libraries and PDKs for the EKV2.6
test chip design and manufacturing.

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 10 of 21

Parameter Extraction Methodology

• Parameter extraction methodology established for EKV v2.6

• Sequential task performed from an array of transistors
in the W/L plane.

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 11 of 21

Pinch-off Voltage Characteristic

• Pinch-off voltage measurement at constant current (IS/2)

• Gate voltage VG is swept and VP=VS is measured at the source for a
transistor biased in moderate inversion and saturation
• Effects of short- and narrow-channels are analyzed using the
charge-sharing approach.
• Corresponding parameters: LETA and WETA
W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 12 of 21
Transfer Characteristics in Saturation

• ID-VG measurement in saturation

• Determine gate transconductance gm
• Extract technology current I0, slope factor n a

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 13 of 21

p- and n-MOS IV Characteristics

• ID-VG and ID-VD measurements

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 14 of 21

CV Characteristics – Extraction of Cox

• Split CV measurements Parameter Units NMOS PMOS

• CGG total gate capacitance COX F/m2 8.00E-3 7.80E-3
• CGC channel capacitance
• CGB gate-bulk capacitance TOX m 4.31E-9 4.42E-9
• Extraction of gate capacitance Cox
• Cox obtained in inversion:
Cox=CGG, inv(max)/(W∙L)

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 15 of 21

Input Noise Power Spectral Density Svg(f)

• Referring output noise to the input: Parameter Units NMOS PMOS

• SVG(f) =SID(f)/gm2 KF V2F 6E-25 6E-24

• Extract KF, AF parameters AF - 0.92 1.33

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 16 of 21

Comparison nMOS-pMOS 180nm CMOS

•Use input referred noise to compare among different devices

• nMOS input referred noise is lower than pMOS @f ≤ 250 Hz
• But: … nMOS has higher corner frequency fc.
• “1/f” is not always 1/f !

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 17 of 21

ADMS - Overview
Simulator-Specific
ADMS-XML Interfaces

Verilog-A ADMS
XML ADMS
Model Code Parser
Internal Data Base
data

Other
Testing Other
Code Generator ADMS-XML
prior applications
Tools
implementation

c-code for: •Documentation

ADS, Eldo, Mica, hspice, •Circuit Test Benches
Spectre, Titan, zspice,
ngspice, QUCS, Gnucap, Xyce

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 18 of 21

Qucs EKV2.6 n-MOSFET Long Channel IVs

Transfer Ids-Vgs characteristics Output Ids-Vds characteristics

[REF] http://qucs.sourceforge.net

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 19 of 21

FOSS EKV2.6 Verilog-A Outlook

● EKV RF modeling

● SOI and TFT

Technologies

● EKV HV

● Cryogenic electronics

● Ageing, radiation effects,

reliability modeling

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 20 of 21

FOSS EKV2.6 Verilog-A

Summary
□ Moore’s Law
□ FOSS Modeling/Simulation Flow
□ Development of the Compact Models
□ EKV v2.6 Model Structure
□ Testchip Layout
□ Parameter Extraction Methodology
□ Electrical Characterization
■ Pinch-off Voltage Characteristic
■ IV and CV Characteristic
■ 1/f Noise Characteristic
□ Model Implementation
■ ADMS
■ Qucs Benchmarks
■ FOSS EKV2.6 Verilog-A at https://github.com/ekv26/model

W.Grabinski et al. FOSS EKV2.6 Verilog-A at GitHub 21 of 21

 FOSS TCAD/EDA Tools
for Compact Modeling
Technology - Devices - Applications

Wladek Grabinski
MOS-AK Association (EU)
wladek@mos-ak.org
 Over two decades of MOS-AK in brief

17 subsequent MOS-AK modeling workshops

3 consecutive compact modeling TRACK4
at ESSDERC/ESSCIRC Conferences
27 international MOS-AK modeling workshops
in Europe, USA, China (planning Latin America)
16 special compact modeling sessions
at MIXDES Conference
50+ active sponsors and technical program promoters
300+ MOS-AK technical CM papers and posters
(available on line www.mos-ak.org)
4 modeling MOS-AK modeling books
http://www.mos-ak.org/books/
www.mos-ak.org
 MOS-AK Scientific Publications

Special Compact Modeling Issues

Compact/SPICE Modeling Books

TRACK4: Compact Modeling of Devices and Circuits

www.mos-ak.org
 MOS-AK: 2019 Events
❑ 2nd MOS-AK India: Feb. 25-27, 2019 IIT Hyderabad (IN)
❑ MOS-AK at 1st LAEDC: Feb 24, 2019 Armenia (CO)
❑ 2nd Free Silicon Congress (FSiC) March 14-16, 2019 Paris (F)
❑ 19th HICUM Workshop May: 13-14, 2019 Neubiberg (D)
❑ 4rd Sino MOS-AK Workshop
June 20-22 2019 Chengdu (CN)
❑ MIXDES Special CM Session & IEEE EDS MQ
June 26-29, 2019 Rzeszow (PL)
❑ 17th MOS-AK at ESSDERC/ESSCIRC
ESSDERC TPC Track 4: Compact Modeling
Sept. 23-26, 2019 Krakow (PL)
❑ AKB Workshop
Nov. 2019 Crolles (F)
❑ 12th MOS-AK (IEDM / Q4 CMC timeframe)
Dec.11, 2019 Silicon Valley (US)
www.mos-ak.org
FOSS TCAD/EDA Tools for Compact Modeling
Technology - Devices - Applications

Outline
• Moore’s Law
• Open Source CAD for Compact Modeling
<www.mos-ak.org/books/CAD_CM_Book.php>
– 2/3D Numerical TCAD Device Simulations
– Schematic entry and circuit simulation
– Device Level Parameter Extraction
– Standardized Data Exchange Format For Device Modeling
• 2019 MOS-AK Compact/SPICE Modeling Events
 Moore’s Law

Moore’s Law is the fundamental driver of the semiconductor industry, what’s even
more important is what it delivers to the end user.
 Moore’s Law (cont.)

The first working monolithic devices (IC) The Raspberry Pi a tiny and brilliantly
presented by Fairchild Semiconductor inexpensive proto-computer
on May 26, 1960 ($25 as of 2014)
 Moore’s Law (cont.)

The first working monolithic devices (IC) The Raspberry Pi Zero is half the size of a ModelA+, with
presented by Fairchild Semiconductor twice the utility. A tiny Raspberry Pi that’s affordable
on May 26, 1960 enough for any project!
($5 or event free as early 2016)
<www.raspberrypi.org/products/pi-zero>
 Five Powerful Lab Instruments
One Open Source Board
On-board is a complete arsenal of electronic engineering instruments: only $29

A. Power Supply (4.5 to 15V, 1.5W max)

B. Digital Output
C. Function Generator (2 channel, 1MSPS)
D. Oscilloscope/Multimeter (2 channel, 750kSPS)
E. Logic Analyzer (2 channel, 3MSPS)

https://espotek.com/labrador
EspoTek Labrador
4007 CMOS inverter chip measurement

https://espotek.com/labrador 10
Qucs: Quite Universal Circuit Simulator

http://qucs.sourceforge.net/ 11
 FOSS Modeling/Simulation Flow

Process/Technology • Compact Modeling Analog/RF

TCAD • Model Libraries IC Simulation

• Cogenda TCAD • Spice/Verilog-A • Ngspice

• DevSim TCAD Simulators • Qucs
• other • Verilog-A • Xyce
EM Simulators Standardization
• GnuCap
○ ADMS
• other
○ MAPP
• measurements
• parameterization
• other
 Compact/SPICE Modeling
• A model of semiconductor device charges,
currents and voltages
• Built from physically-motivated equations
• Intended for use in an analog circuit simulator

TCAD
Models
Accuracy

Compact
Models
Gate Level
Models

Speed
REF: G.J. Coram, "How to (and How NOT to) Write a Compact Model in Verilog-A", BMAS2004 Tutorial
 Process TCAD Simulation
• DevSim TCAD • Cogenda TCAD

2D MOSFET simulation 3D SRAM Cell

 Stanford TCAD Software
Device Modeling Process Modeling Framework/Utilities

PROPHET SUPREM3 ET3D

Monet SUPREM IV FOREST
PISCES SUPREM IV GS HDFVset
PISCES 2ET SUPREM ALAMOD VIP3D
PISCES 2H-B SPEEDIE Mixed Mode
SEDAN III
STRIDE

http://www-tcad.stanford.edu/
 TU Wien TCAD Software

Open Source Software No Longer Supported

ViennaCL ViennaMesh deLink 1.0
ViennaData ViennaProfiler Promis
ViennaFEM ViennaSHE SIESTA
ViennaGrid ViennaSiSpin ViennaMOS
ViennaIPD ViennaTS VMC
ViennaMag ViennaWD VSP
ViennaMath ViennaX Minimos-NT

http://www.iue.tuwien.ac.at/software/
 GTS Minimos-NT: Mixed Mode

Mixed mode TCAD simulation can be done using industry-standard Spice compact
models, including BSIM; the easy-to-use schematic editor allows to quickly edit circuits
and sub-circuits.
 FOSS Computational Electromagnetic
(EM) Modeling Tools
The software in this list is either free or available at a nominal charge and can be downloaded over the
internet. Some of the codes require the user to register with the distributor's web site. If you are familiar with
other free EM modeling software that that should be added to this list, please send the name of the software, a
hypertext link, and a brief description to CVEL-L@clemson.edu.

ASAP - Antenna Scatterers Analysis Program MMANA-GAL (basic version)

AtaiTec Free 2D Field Solver MEEP
ATLC - Arbitrary Transmission Line Calculator MMTL
ATLC2 - Arbitrary Transmission Line Calculator 2 Multiple Multipole (MMP) Algorithms
emAnalyze NEC2
EMAP newFasant (student version)
EMCoS Antenna VLab SV openEMS
EM Explorer pdnMesh
emGine Environment Puma-EM
ERMES Qsci
FastCap and FastHenry Radia
FEKO LITE SATE Static Field Analysis Toolkit (Educational)
FEMM - Finite Element Method Magnetics Students' QuickField
gprMax Sonnet Lite
MagNet (Infolytica) Trace Analyzer
 openEMS: FOSS Electromagnetic Field Solver
http://openems.de

Horn antenna Conical horn antenna Helix antenna

Helix antenna array Large helix antenna array Biquad antenna

CRLH antenna MRI birdcage model MRI ring antennas

SUGAR: FOSS Tool for MEMS

Two-degree-of-freedom optical scanner prototype

Mode 1 = 739Hz, mode 2 = 745Hz.
www-bsac.eecs.berkeley.edu/cadtools/sugar/
 about SPICE
SPICE
* SPICE = Simulation Program with Integrated Circuit Emphasis
* The very first analog circuit simulator introduced in 1973, written in Fortran
* Developed at University of California, Berkeley
* Nodal analysis, few circuit elements, fixed timestep transient analysis
SPICE 2
* Released in 1975, still written in Fortran
* Improvements: modified nodal analysis, memory allocation system,
variable timestep transient using trapezoidal and Gear integration
* Missing: parameter sweep, loop-gain and stability, RF analyses
SPICE 3
* Released in 1989, written in C
* Added X Window plotting
Commercial circuit simulators In-house circuit simulators
* Spectre (Cadence) * TITAN (Infineon)
* HSPICE (Synopsis) * Lynx (Intel)
* PSPICE (Cadence) * TISPICE (Texas Instruments)
* SIMetrix (Simetrix Tech.) * ADICE (Analog Devices),
* APLAC (Nokia now NI) * LTspice (Linear Technologies)
* FastSpice (BDA now Mentor) * Mica (Motorola/Freescale.)
* ADS (Agilent) * PowerSpice (IBM)
* Eldo (Mentor) * Pstar (NXP Semiconductor
 Lung/Airway SPICE Model
Qucs Implementation

[REF] Francesc N. Masana “Lung/Airway Dynamic Model Using ABM Elements and PSPICE”
Proceedings of the 22nd International Conference MIXDES, June 25-27, 2015, Torun, Poland
ngspice & KiCAD

http://kicad-pcb.org
 Xyce & ADMS
• Verilog-A interface, via ADMS model compiler
– VBIC, Mextram, EKV, HiCUM, etc.
• Verilog-A: industry standard format for new models
• ADMS translates Verilog-A to compilable C/C++ code;
• API automatically handles data structures, matrices, tedious details.

https://xyce.sandia.gov/
Gnucap: GNU Circuit Analysis Package
• Gnucap is a modern post-spice circuit
simulator with several advantages over Spice
derivatives.
• Additional Gnucap GIT repositories:
– ADMS model compiler
– Device models
– Gnucap-modelgen Verilog model compiler

www.gnucap.org
 ADMS - Overview
Simulator-Specific
ADMS-XML Interfaces

Verilog-A ADMS
XML ADMS
Model Code Parser Data Base
Internal
data

Other
Testing Other
Code Generator ADMS-XML
prior applications Tools
implementation

c-code for: •Documentation

ADS, Eldo, Mica, hspice, •Circuit Test Benches
Spectre, Titan, zspice,
ngspice, QUCS, Gnucap, Xyce
http:// mot-adms.sourceforge.net
Benefits Using Verilog-AMS
❑ For the model developers
❑ Develop once and run everywhere
❑ Focus on model equation, not on implementation

❑ For the software vendors

❑ Simplified implementation of the standard models
❑ Proprietary Verilog-A models are also supported

❑ For the silicon fabs

❑ Standardized model parameter set

❑ For the end-users (designers)

❑ Standardized libraries and design kits
 Model and Algorithm Prototyping
Platform (MAPP)

Berkeley MAPP is a MATLAB-based platform for prototyping numerical models

and simulation algorithms. MAPP also runs in Octave.
 Model and Algorithm Prototyping
Platform (MAPP)

MAPP eases the process of developing new device models and simulation
algorithms, especially for those who do not have an extensive background in
compact modelling or experience coding algorithms in simulators.
 TRADICA
TRAnsistor DImensioning and CAlculation program

● Provide criteria for transistor sizing

○ calculation of device dimensions
○ calculation of device configuration

● Fast means for generating consistent sets of compact model

parameters based on design rules and process information

● Compact modeling/extractions for various types of devices and

different compact model types
■ MOS (EKV)
■ Bipolar (SGPM, HICUM)
■ Passives (diode, res, mincap, …)

● Hierarchy modeling with different complexities w.r.t. physical effects

K.E.Moebus, M.Schröter, H.Wittkopf, Y.Zimmermann, M.Claus; TRAnsistor DImensioning and CAlculation program
MOS-AK Munich 2007: http://www.mos-ak.org/munich_2007/papers/07_MOS-AK_Moebus.pdf
MS Excel VBA Parameter Extraction
• Local parameter extraction using MS Excel VBA optimization

[Ref] D. Tomaszewski, A. Kociubiński, J. Marczewski, K. Kucharski, K. Domański, P. Grabiec,

"A Versatile Tool for Extraction of MOSFETs Parameters", Proc. 6th Y&D Symposium, 2003, Warsaw
Integrated Tools for Modeling and
Parameter Extraction

[Ref] D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov, W. Grabinski, "FOSS as an Efficient Tool

for Extraction of MOSFET Compact Model Parameters", MIXDES'2016
 IDL Curve Fitting and Optimization
MPFIT - Robust non-linear least squares curve fitting
The IDL routines provide a robust and relatively fast way to perform least-squares curve and
surface fitting. The algorithms are translated from MINPACK-1, which is a rugged minimization
routine found on Netlib, and distributed with permission. This algorithm is more desirable than
CURVEFIT because it is generally more stable and less likely to crash than the brute-force
approach taken by CURVEFIT, which is based upon Numerical Recipes.

http://www.physics.wisc.edu/~craigm/idl/fitting.html
PROFILE: Inverse Modeling Tool

The PROFILE [1] is a tool for inverse modeling of the

semiconductor devices using 2D data and advanced
optimization driver. All the files and its documentation
is available at the official homepage of PROFILE:

http://profile.ewi.tudelft.nl/
http://sourceforge.net/projects/profile2d

[REF] G.J.L. Ouwerling. Inverse modelling with the PROFILE

optimization driver. NASECODE VI Software Forum, Dublin, July
1989.
 PROFILE: Inverse Modeling Tool
: main.pro : main optimization loop
type v_m i_m i_s $
var real VTO UO KP $
: read measured IV data
get IdVg.dat v_m i_m $
: set LEVEL3 parameters
VTO = 1.0
UO = 425
KP = 2E-4
: Constrain specifications
constrain VTO 0.1 2
constrain UO 100 500
constrain KP 0.1E-4 1E-3
setlm deltapr 0.01
: call external non-linear model
setext call ~/bin/profile ngspice.pro >
ngspice.log
setlm talk 2
setlm itermax 15 Transfer MOSFET IV characteristic
: levmar fits a non-linear model to
measurement data.
after VTO, U0, KP extraction
levmar pro i_m v_m i_s VTO KP | UO $ (o :measured, - :simulated)

http://sourceforge.net/projects/profile2d
 Standardized Data Exchange
For Device Modeling Tools
! VERSION = 6.00
The MDM file format (developed and open by
BEGIN_HEADER
Agilent) provides the following advantages: ICCAP_INPUTS
vb V B GROUND SMU1 0.1 LIN 1 0.33 0.45 12 0.01
ve V E GROUND GND 0.1 CON 0
• ASCII based file vc V C GROUND SMU2 0.2 SYNC 1 0 vb
ICCAP_OUTPUTS
• Table-based, row-column format with ib I B GROUND SMU1 B
column header lines that make reading ic I C GROUND SMU2 B
easy—includes a list of the innermost END_HEADER
BEGIN_DB
independent variables. ICCAP_VAR ve 0
• All data tables have identical shape. A #vb vc ib ic
0.33 0.33 4.87574e-011 4.67239e-010
header at the top of the file provides an 0.34 0.34 5.77546e-011 6.85381e-010
outline of all the data in the file. After the 0.35 0.35 6.86361e-011 1.00538e-009
header has been parsed, the location of 0.36 0.36 8.18976e-011 1.47476e-009
0.37 0.37 9.82047e-011 2.16325e-009
any data group can be computed quickly, 0.38 0.38 1.18461e-010 3.17307e-009
permitting rapid location of arbitrary data 0.39 0.39 1.43910e-010 4.65412e-009
0.4 0.4 1.76281e-010 6.82619e-009
groups scattered throughout the file.
0.41 0.41 2.18003e-010 1.00115e-008
Comment lines are denoted by the 0.42 0.42 2.72518e-010 1.46826e-008
exclamation character(!). The file 0.43 0.43 3.44737e-010 2.15321e-008
0.44 0.44 4.41716e-010 3.15754e-008
extension for the data files is .mdm END_DB
(measured data management).
 FOSS Modeling/Simulation Flow

Process/Technology Compact Modeling Analog/RF

TCAD Model Libraries IC Simulation

• Cogenda TCAD • Spice/Verilog-A • Ngspice

• DevSim TCAD Modeling Platform • Qucs
• Other • measurements • Xyce
EM Simulators • parameterization • GnuCap
• other • other
FOSS TCAD/EDA Tools for Compact Modeling
Technology - Devices - Applications

SUMMARY (open topics)

• Process TCAD Simulation
– Interoperability:
Data Exchange Formats
• Compact/SPICE Modeling
– Verilog-A Standardization
– Simulated/Measured Data Exchange
• Analog/RF Circuit Simulation
– Interoperability:
Netlist/Schematic Exchange Formats
 MOS-AK: 2019 Events
❑ 2nd MOS-AK India: Feb. 25-27, 2019 IIT Hyderabad (IN)
❑ MOS-AK at 1st LAEDC: Feb 24, 2019 Armenia (CO)
❑ 2nd Free Silicon Congress (FSiC) March 14-16, 2019 Paris (F)
❑ 19th HICUM Workshop May: 13-14, 2019 Neubiberg (D)
❑ 4rd Sino MOS-AK Workshop
June 20-22 2019 Chengdu (CN)
❑ IEEE EDS MQ & MIXDES Special CM Session
June 26-29, 2019 Rzeszow (PL)
❑ 17th MOS-AK at ESSDERC/ESSCIRC
ESSDERC TPC Track 4: Compact Modeling
Sept. 23-26, 2019 Krakow (PL)
❑ AKB Workshop
Nov. 2019 Crolles (F)
❑ 12th MOS-AK (IEDM / Q4 CMC timeframe)
Dec.11, 2019 Silicon Valley (US)
www.mos-ak.org
 FOSS CAD/EDA Tools Supporting
The European Open Access PDK Initiative
Wladek Grabinski (speaker), René Scholz, Sergei Andreev, Krzysztof Herman,
Alexey Balashov, Mario Krattenmacher, Pascal Kuthe, Markus Müller,
Jean-Michel Sallese, Matthias Bucher, Daniel Tomaszewski, Guilherme Torri,
Bal Virdee, Mike Brinson, Matthias Köfferlein, Thorsten Liebig, Jan Taro Svejda,
Al Davis, Felix Salfelder, Francesco Lannutti, Paolo Nenzi, Dietmar Warning,
Holger Vogt, Murat Eskiyerli, Eric Keiter, Jason Verley, Luca Benini,
Frank Gurkaynak, Luca Alloatti, Thomas Kramer, Marie-Minerve Louerat, Jean-Paul
Chaput, Harald Pretl, Boris Murmann, Mehdi Saligane, Matt Venn, Tim Ansell

Libre-SOC, FPGA and VLSI Devroom

Brussels 3 February 2024
 FOSS CAD/EDA Tools Supporting
The European Open Access PDK Initiative
Outline:
• Motivation
• eSim FOSSEE Tool for IC Design
• Open PDK Initiative
– SkyWater (US), GF (US), AIST ACPS (J), IHP (D)
• IHP Open PDK and FOSS Tools Development
• What’s next?
– Open PDK and FOSS to Empower
Researchers and IC Designers
– IHP Open PDK Roadmap
– Challenges and Opportunities
• Acknowledgment
Motivation: A call for Building Talent and Skills

[REF] EU Chips Act Drives Pan-European Full-Stack Innovation Partnerships

Plenary Session at ISSCC, FEB.20, 2023
Jo De Boeck, Executive VP and CSO, imec and KU Leuven, Belgium
eSim FOSSEE Tool for IC Design

Features of eSim
● Draw circuits using KiCad, create a netlist and simulate using ngspice
● Add/Edit SPICE Models and subcircuits using the Model / Subcircuit Builder tools
● Perform Mixed-Signal ngspice Simulation
● Design PCB layouts and generate Gerber files using KiCad
● Support for Ubuntu and Windows
[REF] https://esim.fossee.in/home
 Open PDK Initiative

The Open-Source FPGA Foundation offers a set of free and open-source tools enabling fast prototyping for
FPGA chips and automated EDA support, through open standard collaboration https://osfpga.org/about-us/
• Semiconductor R&D: Tapeout of a design is one of the most important aspects of academic
semiconductor research and development.
• Prohibitive cost: The prohibitive cost of tapeout and complications therein has prevented the majority of
R&D folks and startups from participating.
• Open-Source: Open PDK Initiative plans to promote and facilitate the usage of open source FPGA
technologies.
• Free tapeouts: Open PDK Initiative plans to offer a very simple flow for tapeout, and several of those will
be free or at minimal costs.
Available Resources:
• SkyWater Open 130nm CMOS PDK: https://github.com/google/skywater-pdk
• OpenLane RTL2GDS Compiler: https://github.com/efabless/openlane
• Caravel Harness: https://github.com/efabless/caravel
• Caravel User Project: https://github.com/efabless/caravel_user_project
• Open MPW Precheck: https://github.com/efabless/open_mpw_precheck
FAQ:
• https://efabless.com/open_mpw_faq
 IHP Frankfurt (Oder)
Institute for High Performance Microelectronics

[REF] 130nm BiCMOS Open Source PDK, dedicated for Analog/Digital, Mixed Signal and RF Design
https://github.com/IHP-GmbH/IHP-Open-PDK
Networking Workshop FMD-QNC 27th 28th of June 2023
https://github.com/IHP-GmbH/IHP-Open-PDK/wiki/Networking-Workshop-FMD-QNC
IHP Open PDK and FOSS Tools Development

• IHP started on existing experiences from SkyWater PDK

<https://github.com/google/skywater-pdk>
• IHP will offer an analog design flow, later RF design
• Quality should fulfill requirements for academic education
• Open Tools has to be improved, interface development is
crucial
• For a sustainable approach, we/IHP have to improve
capabilities to a level to support productive projects
• Secure long term funding for MPW and Foundry Service
• Achieve industrial/non-public funding
 IHP Open PDK Project on GitHub
PDK Contents:
● Project Roadmap Gantt chart
● SG13G2 Process Specification & Layout
Rules
● Base cell set with limited set of standard
logic cells
● SRAM cells
● Primitive devices (GDS)
● GDS Test structures
● MOS/HBT/Passives measurement data
● KLayout layer property and tech files
● KLayout DRC deck (minimal rule set)
● KLayout Parameterizable pycells (limited
set)
● MOS/HBT/Passives ngspice/Xyce models
● xschem: device symbols, settings,
testbenches
● OpenEMS: tutorials, scripts, documentation

[REF] 130nm BiCMOS Open Source PDK, dedicated for Analog/Digital, Mixed Signal and RF Design
https://github.com/IHP-GmbH/IHP-Open-PDK
 Open Source Digital Design Flow

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys,
Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and
optimization. The flow performs all ASIC implementation steps from RTL all the way down to GDSII.

[REF] OpenLane is an automated RTL to GDSII flow

https://github.com/efabless/openlane
Alternative:LiP6 FOSS Logiciels: Alliance, Coriolis, Oceane, Standard Cell Libraries, Tas/Yagle
https://largo.lip6.fr/equipe-cian/logiciels/
 FOSS Analog IC Design Flow

FOSS open-source analog design flow with the following tools:

● PDK files from skywater-pdk and xschem_sky130.
● Schematic entry with xschem.
● Simulation with ngspice.
● Layout, extraction and DRC with magic
● LVS with netgen.
● Manual routing of design using magic into the caravel analog user
project. This user project is verified with precheck tool and
submitted to the shuttle.

[REF] Prof. Priyanka Raina, Stanford, EE372 https://priyanka-raina.github.io/ee372-spring2022/

FOSS EDA Tools Wiki <https://semiwiki.com/wikis/industry-wikis/eda-open-source-tools-wiki/>
IIC-OSIC-TOOLS is an all-in-one Dockers for analog and digital chip design
<https://github.com/iic-jku/iic-osic-tools>
Analog/RF Open Source Design Flow

● KLayout-oriented flow
○ Layout design
○ Parametric cells
○ Physical Verification
● QUCS-S, xschem
● ngspice, xyce
● OpenEMS
● other (?)
 SiliWiz

SiliWiz https://app.siliwiz.com/
Tiny Typeout https://tinytapeout.com/
Zero to ASIC course https://zerotoasiccourse.com/
FOSS Schematic and Layout Editors

Xschem is a schematic capture program, it allows creation of hierarchical representation of circuits with a top down
approach. By focusing on interfaces, hierarchy and instance properties, a complex system can be described in terms of
simpler building blocks. A VHDL or Verilog or Spice netlist can be generated from the drawn schematic
<https://xschem.sourceforge.io/stefan/index.html>
Magic version 8.3 is the official current released version of the program, a combined effort of the "Magic Development
Team". The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and
help magic stay abreast of fabrication technology.
<http://opencircuitdesign.com/magic/>
FOSS Schematic and Layout Editors

Revolution EDA offers a complete setup starting from schematic or Verilog-A entry, to simulation, layout, DRC and LVS.
Symbols have integrated callback functions allowing accurate simulations.
[REF] <https://reveda.eu/>

KLayout has fast loading and accurate drawing, supports GDS and OASIS file formats with automatic uncompression of
zlib compatible formats and is extensible and configurable to a large degree by custom Ruby or Python scripts
[REF] https://klayout.de/
https://peertube.f-si.org/video-channels/fsic2022/videos?sort=-publishedAtand page=2
 OpenEMS ElectroMagnetic Solver
• 3D FDTD solution targeting RF EM simulations
• Model built by Python or Octave scripting
• Graphical viewer for model + mesh (CSXCAD)
• Visualisation: paraview or pyvista-module
• Some interfaces to EDA packages
but no KLayout support yet
• No internal support for GDSII import, interface was
created using Python library gdspy
• S-Parameter output
• Useful tutorials for RF examples
• Possible issue:
– small residual energy at low frequency or DC
might create DC leakage in simulation results
– Mostly manual mesh definition
– No user-friendly GUI for IC designer

[REF] openEMS - free and open electromagnetic field solver using the FDTD method
https://www.openems.de/
 openEMS: FOSS Electromagnetic Field Solver

Horn antenna Conical horn antenna Helix antenna

Helix antenna array Large helix antenna array Biquad antenna

CRLH antenna MRI birdcage model MRI ring antennas

[REF] http://openems.de
 OpenVAF: Next-Generation Verilog-A compiler

OpenVAF Roadmap
● Reaching full compliance with the Verilog-A standard
○ Behavioral modelling features
○ Support for features that allow defining full circuits/full PDKs in Verilog-A
● OSDI integration in Xyce
● Noise analysis (released with ngspice-42*)
● Improved documentation

[REF] P. Kuthe, M. Muller and M. Schroter, “VerilogAE: An open source Verilog-A compiler for compact model parameter extraction”, J-EDS, vol. 8, pp.
1416–1423, 2020 https://openvaf.semimod.de/
* https://ngspice.sourceforge.io/docs/ngspice-42-manual.pdf
Alternative: Felix Al Davis; Verilog-AMS in Gnucap; https://fosdem.org/2024/schedule/event/fosdem-2024-3560-verilog-ams-in-gnucap/
ngspice and QUCS-S Custom Library
for IHP Open PDK

sg13g2 nMOS output characteristic test circuit

[REF] Qucs-S - circuit simulation program with Qt-based GUI

https://ra3xdh.github.io/
 ngspice and KiCAD

[REF] https://www.kicad.org/download/
Holger Vogt; ngspice circuit simulator - stand-alone and embedded into KiCad
https://fosdem.org/2024/schedule/event/fosdem-2024-2834-ngspice-circuit-simulator-stand-alone-and-embedded-into-kicad/
 Analysis and Design of Integrated Circuits
EE 628 (University of Hawaiʻi at Mānoa)

[REF] Example of a university course targeting the IHP Open PDK https://github.com/bmurmann/EE628 to teach
mixed-signal circuit design using open-source tools and create your own voltmeter chip! This course is being
developed in collaboration with the Microelectronics Commons California-Pacific-Northwest AI Hub.
 Iguana/PULP at IIS ETH Zürich (CH)

Main Details
Application Pulp
Technology 130nm
Fab IHP
Type Research
Package QFN88
Dimensions 6264μm x 6264μm
Gates 3 MGE
Voltage 1.2 V
Clock 60 MHz

Iguana is the first IIS ETHZ attempt at using the IHP 130nm Open PDK. The design is essentially the same
as Cheshire platform using the CVA6 64-bit RISC-V processor originally developed as part of the PULP
team. The design was completed using only open source standard cell libraries, and although an almost
complete backend run was made with the OpenROAD tools, a last minute issue very close to the tape-out
date resulted in a backup design using commercial EDA tools to be taped-out. Read about the design
experience in presentation at the FSiC2023(slides). This design has received generous support from IHP
Leibniz Institute for High Performance Microelectronics.

[REF] https://wiki.f-si.org/index.php?title=Industry-Grade_SystemVerilog_IPs_And_The_Open_Flow:_How_We_Synthesized_Iguana
 Early adopter for OSH: Project HEP
Open Hardware Security Module
● Open Processor
● Open EDA
● Open PDK

Main Details
Application Hardware Security Module
Technology 130nm
Fab IHP
Type Prototype
Package Flip Chip
Dimensions 4610μm x 4580μm
(Vex: 1.3mm²; SRAM: 10.2mm²)
Peripherals UART, SPI, JTAG, GPIO
AES accelerator on the ABP3 bus (masked AES)

German early adopter OSH project

● Start 03/2021
● Initiator for IHP-Open130-G2
● First fully open ASIC TapeOut with IHP-Open130-G2
● Root of Trust extensions for IHP-Open130-G2 planned

Project GIT; riscv.org refering the project; Project website

 SAR – ADC Project at JKU Linz (A)

Design of a 1.2MS/s Charge-Redistribution Non-Binary

SAR-ADC utilizing the Open-Source SKY130 PDK
https://github.com/iic-jku/SKY130_SAR-ADC1

• Transfer to open SG13G2 PDK in progress

• Mixed Signal capabilities of open PDK needed
• Both Design Projects can be used to benchmark
and optimize open PDK and open Tools

[Note] IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip
<https://github.com/iic-jku/iic-osic-tools>
 An open-sourced 1.44-MS/s 703-μW 12-bit
non-binary SAR-ADC 130-nm CMOS at JKU Linz (A)

[REF] Fath, P., Moser, M., Zachl, G. et al. Open-source design of integrated circuits. Elektrotech. Inftech. (2024)
https://doi.org/10.1007/s00502-023-01195-5
 What’s next?
FOSS to empower researchers and designers
FOSS eSim offers similar capabilities and ease of use as
any equivalent proprietary software for schematic creation,
simulation and PCB design, without having to pay a huge
amount of money to procure licenses.
[REF] https://esim.fossee.in/

The SSCS PICO Program: Democratizing IC Design; first

open-source IC design contest. Silicon fabrication using
free open SKY130 PDK on eFabless’ chipIgnite shuttle
runs in 2021 and 2022, GF180MCU in 2023
[REF]https://sscs.ieee.org/about/solid-state-circuits-directions/sscs-pico
-program
FOSS

sponsored by
RISC-V is a free and open ISA enabling for a new era of
processor innovation through open collaboration. Offers a
new level of free, extensible software and hardware
freedom on architecture, paving the way for the years
ahead of computing design and innovation.
[REF https://riscv.org/about/
 What’s next?
IHP Open PDK Roadmap

It is important to leverage community efforts, public funding,

corporate contributions and channel effort to foster common goals
for an FOSS IC design flow based on open PDK

• Initiate cooperation and joint projects with open source community

– no closed PDKs, no NDAs, no restrictive EDA licenses
• Demonstration of design training courses in academic institutions
– Successful open source designs
• Support chip design possibilities for small commercial (SMEs) teams
– Achieve commercial successful projects
What’s next?
Challenges and Opportunities
Things We Need to Work On
• Limited functionality of open-source EDA tools
• Maintenance of tools and repos
• Best practices for team collaboration
• Standards for documentation and validation of “IP”
• Leveraging open-source for analog design automation
“Grand challenge”
– Full analog design automation (for arbitrary circuits)
from requirements to layout is presently not feasible
– We should focus on useful baby steps
• Build large open-source libraries of proven circuit templates
• Build a framework that can capture the intent and design steps of an
experienced designer
• re-use, reproducibility, partial automation BAG, ANAGEN, MOSAIC, …
• Create fast quality assessment tools for circuits and layouts
– Enable “big-data“ approaches, away from “correct by construction“

[REF] Boris Murmann, University of Hawaii; Re-Energizing Analog Design using the Open-Source Ecosystem;
MOS-AK Silicon Valley 2023; DOI: 10.5281/zenodo.10423729
 Acknowledgment
• The IHP PDK Team with Rene Scholz, Open PDK Project Lead
• ETH Zurich + JKU Linz + all the open source community
• German public funded projects:
– VE-HEP (16KIS1339K) https://elektronikforschung.de/projekte/ve-hep-1
– IHP Open130-G2 (16ME0852)
https://www.elektronikforschung.de/projekte/ihp-open130-g2
– FMD-QNC (16ME0831)
https://www.elektronikforschung.de/projekte/fmd-qnc
– FMD-QNC with VDI/VDE (IHP PDK Workshop funding)
 MOS-AK: 2024 Events
● 16th MOS-AK (CMC/IEDM timeframe)
Silicon Valley, Dec.13, 2023
● FOSDEM
Bruxelles (BE) Feb. 3-4, 2024
● MOS-AK/EDTM
Bengaluru, March 3-6, 2024
● 8th Sino MOS-AK
China, Aug. 2024
● 6th MOS-AK/LADEC
Guatemala City (GT) May 8-10, 2024
● FSiC 2024
Paris (Sorbonne) June 19-21, 2024
● Special CM Session, MIXDES
Gdansk (PL) June 27-29, 2024
● 21st MOS-AK at ESSERC
Bruges (BE) Sept. 9-12, 2024
● 17th MOS-AK (CMC/IEDM timeframe)
Silicon Valley, Dec. 2024
contact: wladek@mos-ak.org
Lowering Barriers to Chip Design
using OpenFASoC

Mehdi Saligane
Research Scientist
University of Michigan
mehdi@umich.edu

Dec., 2022
 Background

● DARPA IDEA Program (OpenROAD and FASoC)

● Multi-University and Industry effort
● Member of CHIPS Alliance
CHIPS Alliance Workshop -
October 12, 2021

https://fasoc.engin.umich.edu/
CHIPS Alliance - Analog
- T. Ajayi et al, “Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation”,
Working Group - 2021-05-10
IFIP/IEEE VLSI SOC
- T. Ansell and M. Saligane, "The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : lnvited Paper,"
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-8.
- Q. Zhang et al., "An Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130
nm for Comprehensive Design Space Exploration," in IEEE Solid-State Circuits Letters, vol. 5, pp. 174-177, 2022..
 FASoC SoCs in TSMC 65 and GF12LP
● Multiple tape-outs in TSMC 65, GF12LP, SkyWater 130nm

Temp ● GF12LP - 12nm FinFET

Senses ● GF 8HP - 130nm BiCMOS
First automated SoC ● SKY130 - 130nm Bulk
Fab’d in TSMC65nm
DCDC ARM
SRAM

2.6mm
M0 core 64KB
SRAM

2mm
ADCs

LDOs
BT Tx
PLL

2.6mm 2mm
TSMC65LP SoC (2019-08) GF12LP SoC (2020-10)
 (Open)FASOC Now

● Endorsed framework by CHIPS Alliance

● Analog Work Group
● Now Funded by Google, NIST and others
CHIPS Alliance Workshop -
October 12, 2021

CHIPS Alliance - Analog

https://openfasoc.readthedocs.io/ Working Group - 2021-05-10
- T. Ajayi et al, “Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation”,
IFIP/IEEE VLSI SOC
- T. Ansell and M. Saligane, "The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : lnvited Paper,"
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-8.
- Q. Zhang et al., "An Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130
nm for Comprehensive Design Space Exploration," in IEEE Solid-State Circuits Letters, vol. 5, pp. 174-177, 2022..
 How it works:
Traditional vs Automated Chip Design
 Analog vs. Digital design flow
Automated

Manual/Custom

● Analog design flow

Significant number of manual
and custom steps.

● Digital design (grid-based)

flow
Almost entirely automated.
 Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator
ISSCC-2015

Temperature Sensor D-LDO

Automated

Manual/Custom ISSCC-2017 CICC-2010

DC-DC Converter
PLL

ALIGN Automated Layout Generator

 Initially only proprietary design flow

SAR ADC Block Diagram

Temperature Sensor D-LDO

PLL DC-DC Converter

Automated

Manual/Custom
 Now proprietary or open source design flow

SAR ADC Block Diagram

Temperature Sensor D-LDO

PLL DC-DC Converter

OpenFASoC!

Automated
Automated
Manual/Custom

portable
analog
 New tools and Python-based APIs

https://github.com/idea-fasoc/OpenFASOC
Open Source IC contributions
old tapeouts
 OpenFASOC on MPW-I: 64 sensors +
D-LDO
LDO in SKY130
● Actively contributing to the open source community
3v3 to 1v8
ILOAD: 25mA
● 1st open FASoC flow built on top of OpenROAD tools
○ Focused on the Temp. Sensor Generator
64 sensor mesh
● FASoC testchip in SKY130: (3 Vt flavors)
○ Includes Caravel SoC
○ 64 Temp. Sensor Mesh
○ LDO ported (~ a week)
■ Updated comparator to
strongArm latch
■ 5v native NMOS switch Caravel SoC +
wishbone bus

Test-chip in MPW-I
OpenFASOC on MPW-II: Integrated Temperature
SensorsSensors are embedded inside the OpenTitan SoC and
connected through tilelink

Highly tunable VREF

with trimming bits

Non Default Routing is

use to route the header
cells to the 2nd voltage Sensing elements
domain power ring are sitting on a
second voltage
domain

The temperature sensor generator uses a

fully open source flow
 MPW-I Measurement Results
● 64 sensors array used for low-cost design space exploration
 MPW-I Measurement Results
● Below 1 oC inaccuracy and SOTA results
 MPW-I Measurement Results
● Results Summary and Comparison Table
● Published at the Solid-State Circuits Letters!
 OpenFASOC on MPW-II: 1st Open Source AMS SoC

● Included initial support for voltage domains in OpenROAD

Array of 10
D-LDOs
● Implementation of the OpenTitan SoC using an ECO flow
Voltage Refs. +
to fix hold timing with degrading the FMAX analog buffers

OpenTitan SoC includes

● Temperature Sensor generator is using an end-to-end 16KB, 4 T-sensors and
Open Source flow powered by D-LDO

● Updates to the D-LDO generator:

○ Embedded voltage references
○ Decap cells using MIM cap.
○ Multiple implementations and ILOAD

● https://efabless.com/projects/239
● https://github.com/msaligane/caravan_openfasoc.git Test-chip in MPW-II
 OpenFASOC on MPW-II: D-LDO generator

Unit MIM
Decap cells

Highly tunable VREF

with trimming bits

Voltage Reference with symmetrical placement Array of power switches

evenly placed using .py

Array of D-LDOs
OpenFASOC on MPW-II: D-LDO generator
● Aux cells are swapped to experiment
with different switch structures
● Multi-gain feedback loop is
implemented
 OpenFASOC on MPW-II: OpenTitan SoC
● 1st SoC using AMS components

● The Opentitan SoC contains

○ UART, SPI interfaces
Power connections
○ 16KB of SRAM (OpenRAM)
between LDO and
○ D-LDO is used to power-up all the blocks OpenTitan are done
○ All Peripherals are connected through Tilelink Manually

● Timing has been carefully checked and an ECO flow has been
used to avoid altering the FMAX while fixing hold violations

OpenTitan AMS SoC - Die Photo

NIST’s Nanofabrication accelerator
Taped-out using OpenFASOC
Control Electronics for Quantum Computers
Requirement of Low Operating Power
Cryogenic Test Structures with NIST on MPW-5

● Partnership with NIST:

○ Re-characterization of SKY130 with wide
range temperatures including cryogenic (4K)
○ Automated test structures platform
Cryogenic Test Structures - test interface
Interleaved Placement in OpenROAD
Platform: Sky130hd
Inverter array: 12 x 12

● Uses DEF manipulation using Python but

could be integrated within OpenROAD
Interleaved Placement in OpenROAD
Gdsfactory - automated custom structures
 MIM Cap Generation using Gdsfactory

GDSFACTORY Array creation routine

GDSFACTORY Mesh creation routine
Inputs:
m Multiplicity a,b
Inputs:
Offsets x,y
Mesh dimension n,m
Mesh pitch x,y
Mesh layers
y

n
x
gf.path() gf.move()
gf.add_ref() gf.add_ref()
gf.move()
 Example - Array of Flying MiM caps + Custom Padring

GDSFACTORY Pad-ring place & route routine

Inputs:
Pad ring array spec
Connection definitions (semi-custom)

gf.move() gf.add_ref() * Through Array creation routine

MIM Cap Generation using Gdsfactory

● Computes the grid and places capacitor on grid

● Generates connecting metals (with minimum metal spacing)
● Replicates and connects the structures to pads
 Resultant Test Die

https://github.com/msaligane/openfasoc_cryo_caravel
3 Tapeouts Already! MPW-8 Loading …

MPW-5 MPW-6 MPW-7

GF180 Tape out
MPW-0
MPW0 in GF180

Major Highlights:

● Flash memory test

structures
● Synthesized Gm-C
Filter
● Synthesized Ring
Oscillator
● The first analog
design submitted to
GF180 OpenMPW
(GF12nm and Intel 16nm) FinFET
Tape-outs
 Tape Outs in GF12LP - OpenTitan SoC
● 1st tapeout in GF12LP using OS tools (OpenROAD)
● PD and timing optimization using OpenROAD
● Used a modular flow to smoothly fill-in the gaps
using proprietary tools

● Signoff using PT
○ @ TT|25C|0.8v|funcmax
■ 350MHz

● Temperature sensors
○ TRANGE: -20 to 100oC Opentitan SoC Includes: IBEX, Tilelink
○ Error: +/- 0.2 C (post-PEX)
o bus, UART, SPI, Timers, 32KB RAMs and
4 sensors

Die Photo of FASoC’s 2021 testchip in GF12LP

Including RAMs, LDOs, BLE, CDC and an OpenROAD
based implementation of the Opentitan SoC
 Tape Outs in Intel 16 - OpenTitan SoC
● Tapeout in Intel 16nm using OS tools
● PD and timing optimization using OpenROAD
● Used a modular flow to smoothly fill-in the gaps
using proprietary tools

● Temperature Sensor RTL to GDS flow is fully

Open-Source

Floorplan of Intel 16 tapeout Including Opentitan, Temperature

sensor array and crossbar using OpenROAD
 Tape Outs in Intel 16 - OpenTitan SoC
● OpenTitan SoC contains
○ SPI, GPIO interfaces
○ Ibex CPU
○ 16KB SRAM
○ Main crossbar and peripheral crossbar
○ All peripherals are connected through Tilelink

Frequency Util. Macro Place Macro Cell Pad Area

Channel Place Halo
28MHz 29% 40 40 20 20 2 sites 425x425
Floorplan of in Intel 16 Including RAMs and an
*64% um2 OpenROAD based implementation of the Opentitan SoC
Tape Outs in Intel 16 - Power Numbers
24 Temperature Sensors Array

Temp. Sensor

GPIO

Area = 33.048um x 34.02um

Temperature Sensor Variant A
Header A

Corner TTTT RSSS RFFF

TCONV (ms) 0.1

Energy/Conv
0.77 0.18 3.72
(nJ)

ErrorMAX (°C) 0.13 0.17 0.33

Temperature Sensor Variant B
Header B

Corner TTTT RSSS RFFF

TCONV (ms) 0.1

Energy/Conv
1.40 0.28 6.81
(nJ)

ErrorMAX (°C) 0.62 0.17 0.41

Temperature Sensor Variant C
Header C

Corner TTTT RSSS RFFF

TCONV (ms) 0.1

Energy/Conv
1.59 0.32 7.57
(nJ)

ErrorMAX (°C) 0.35 0.25 0.39

CHIPS Alliance AWG Activities
Techno/Design Loop
New Measured Data, Models, CI
 Technology/Design Feedback Loop
● Compatibility between open-source models versus closed models
● Quality of models (Both closed and Open-source)
● We have to define a Technology/Design feedback loop in the Open-source real

8x
Discrepancies Closed vs Open-Source tools
Frequency Power VVDD Inaccuracy
-31.50% 539.63% -0.82% 780.93%
-8.12% 181.81% -0.85% 0.00%
-2.10% 106.59% -1.58% 323.15%
-0.62% 87.81% -1.78% 228.61%
-0.08% 82.38% -1.70% 192.13%
-0.29% 80.25% -1.09% 0.00%
-0.56% 79.70% -0.72% 117.29%
Preliminary Measurements on Skywater 130nm
 Open-Source MOSFET Modeling – Roadmap

● Envision a set of standard measurements on open-source technologies (such

as SkyWater 130nm)
● Release measured data on GitHub
○ Automatically verify foundry models through dedicated benchmarks
○ Generate new models for analog and RF circuit in the target technology

● Standard measurements and the modeling parameters must be released

● Everything needs to be Automated!

Current version of the Working version of the tools Working version of the Current version of the tools suite
generator suite and PDK generator and PDK

EDA EDA
PDK PDK
Config A tools Config A tools

Central
Database

Tools
Metri suite
and PDK
cA
version
Metric AA Metri
Metri
Metric
Power, Power,
cefficiency Metric AA
cAA Metric
Power,
efficiency metrics efficiency
metrics metrics

Metrics from
Metrics from
“last-best”
“last-best”
version of the
Metrics from version of the
generator
“now-best” generator
Best version version of the
generator List of tools
with the list of version and
working PDK version
configurations Tools suite
and PDK
versions info
Current version of the
generator
Working version of the
tools suite and PDK TempSense LDO DC-DC
generator generator generator

EDA …. ….
PDK
Config A tools

Generator
library

Shared
Database

Metr
Tools
suite and
icPDK
A
Metric
Metric Metr version
APower,
Metr
Power, DSE
A icefficiency
icAA
efficiency metrics
metrics Metrics from
“last-best”
version of
the
generator
Metrics from
“now-best”
Best version version of Publish reports on
with the list of the openfasoc.readthe
working generator
configurations docs.io
CHIPS Alliance AWG Activities
GSoC, Notebook Competition
“Code-a-Chip” Travel Grant Awards at ISSCC'23
● IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
○ https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io
The end!
Bonus slides
 FASoC: Fully-Autonomous SoC Synthesis
● Correct-by-construction SoC design leveraging IP-XACT and Arm
Socrates
● Analog generation tools for xDC, PLL, SRAM, DCDC, temp sense, CP
Amp, ΣΔ ADC
 Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator
ISSCC-2015

Temperature Sensor D-LDO

Automated

Manual/Custom
Uses ISSCC-2017 CICC-2010

automated PLL
DC-DC Converter

Digital
design
flow
 Generated Analog into Digital design flow
FASoC SAR ADC Block Diagram

Generator

ISSCC-2015

Temperature Sensor D-LDO

Automated

Manual/Custom ISSCC-2017 CICC-2010

DC-DC Converter
PLL

FASoC Aux Cells

Trade-offs and Examples
 Performance / Complexity Tradeoff
● FASoC augments digital flow with APR tool placement/routing constraints and
minimizes the (performance loss * complexity)
Analog layout FASoC 2.0 FASoC 1.0
generator Standard Cell only
Minimum
constraints, digital
100% Partial constraints, compensation
constraints digital
compensation loss * complexity

performance
loss
complexity
ADPLL (DCO) - Structured Placement Example
● Patterned placement information generated by python code ⇒
reduce delay mismatch between stages, added Decaps
● Scalable with design parameters
●
●
Decaps
stg0
stg1
.
DCO cells Fine cells . Coarse cells Fine cells
.
stg6

DCO cells

DCO placements with Decap

 D-LDO Power Routing Example
Narrow
Performance loss caused by PnR
Rseries
○ Large Series Resistance caused by wiring Unpredictable
congestion for increased array size Placement
○ Unpredictable wiring due to random Leads to More
placement of power cells Variation

Wide
●
●

DCO cells

DCO placements with Decap Pre-PEX Post-PEX

 D-LDO Power Routing Example
Constraint less Post-PEX Scalable Constraint Post-PEX
R2 = 0.8865 R2 = 0.9993
Narrow
Constraints to improve
performance
○ Technology agnostic fencing to
constraint placements
○ Use power stripes to improve
series R problem
○ Automatic analysis of technology
database file for determining the
stripe metal layers
○ Taped out in BiCMOS and bulk
130nm, TSMC 65LP and GF12LP

Improved
Predictability & Rseries
 Tape Outs in Intel 16 - OpenTitan SoC
I SRAM Ibex D SRAM

data

data
instr
Adaptor S Adaptor Adaptor
M S

Main Crossbar

S M
M

Peripheral Crossbar

GPIO UART I2C SPI

SPI JTAG
OpenFASoC - Portable Transferrable Analog
>10x 130nm 12nm
Planar Bulk FinFet
cheaper!
SKY130 GF12LP
MPW-1 64 temp sensors Temp sensors
D-LDO DC-DC Test IC 1
AMS SoC AMS SoC
MPW-2 D-LDO PLL
More temp sensors
MPW-3 skip
DC-DC
MPW-4 PLL
AMS SoC
MPW-5 More!!!
Same fully open source tools
Same scripting generators
OpenFASoC - Portable Analog
● Analog generators - Power DCDC + LDO, Temperature Sensors, PLLs,
ADCs.
● Example mixed signal SoC integration.
● Silicon proven with increasingly more tape outs, increasingly faster!
● Fully open source flow using fully open source tooling (OpenROAD, Xyce).
● Demonstrating acceleration of velocity and productivity.

SKY130 GF12LP
130nm 12nm
>10x Planar Bulk FinFet

Same fully open source tools

cheaper! Same scripting generators
SAR ADC Common Centroid Placement
› Symmetrical Placement of unit caps
and switches Narrow
Output Spec. CDL PEX
FSAMPLING (MHz) 1
Unit Cap Value (fF) 2.6
SAR ADC Block Diagram
Area (mm2) - 0.04
Power (µW) 6.72 11.2 common-centroid
Effective Number of Bits 7.86 7.75 placement
8bits
strategy
SAR
best-case
ADC

6bits
SAR
ADC
Open Source RoT
Inst
RAM

Peripherals
RISC-V
AXI

Data
RAM
Accelerating Custom Circuits for Sensors
using OpenFASOC

Mehdi Saligane
University of Michigan
Co-Founder & CTO @ Alea Biosciences
mehdi@umich.edu

Dec, 2023
2
 Evolution of Software Dev till the 90s
● Software Dev in the 90s
○ Vendor provided compiler
○ Toolchain incompatibilities
○ OS dependent

3
 Context and Background
● Software Dev in the 90s
○ Vendor provided compiler
○ Toolchain incompatibilities
○ OS dependentike curre
nt
l
Looks r e d ev!
a
hardw

4
 Lowering Costs & Barriers to Chip Design
● Software Dev in the 90s
○ Vendor provided compiler
○ Toolchain incompatibilities
○ OS dependentike curre
nt
l
Looks r e d ev!
a
hardw
Describe your experience with
(tapeout) toolchain in one word
No Response
9%
Neutral Negative
34.0% 56.5%
Survey of ~ 50 Students

5
 Lowering Costs & Barriers to Chip Design
● Software Dev in the 90s
○ Vendor provided compiler
○ Toolchain incompatibilities
○ OS dependentike curre
nt
l
Looks r e d ev!
a
hardw
Describe your experience with
(tapeout) toolchain in one word
No Response
9%
Neutral Negative
34.0% 56.5%
Survey of ~ 50 Students

6
 Lowering Costs & Barriers to Chip Design
● Software Dev in the 90s
○ Vendor provided compiler 70 000 HW vs 830 000 SW
○ Toolchain incompatibilities
nt Eng.
○ OS dependentike curre
l
Looks r e d ev!
a
hardw
Describe your experience with
(tapeout) toolchain in one word
No Response
9%
Neutral Negative
34.0% 56.5%
Survey of ~ 50 Students

7
 Lowering Costs & Barriers to Chip Design
● Software Dev in the 90s
○ Vendor provided compiler
○ Toolchain incompatibilities
○ OS dependentike curre
nt
l
Looks r e d ev!
a
hardw
Describe your experience with
(tapeout) toolchain in one word
No Response
9%
Neutral Negative
34.0% 56.5%
Survey of ~ 50 Students

8
 Lowering Costs & Barriers to Chip Design
● Software Dev in the 90s
○ Vendor provided compiler
○ Toolchain incompatibilities
○ OS dependentike curre
nt
l
Looks r e d ev!
a
hardw
Describe your experience with
(tapeout) toolchain in one word
No Response
9%
Neutral Negative
34.0% 56.5%
Survey of ~ 50 Students

70 000 HW vs 830 000 SW

9
Eng.
 Lowering Costs & Barriers to Chip Design
● Software Dev in the 90s
○ Vendor provided compiler
○ Toolchain incompatibilities
○ OS dependentike curre
nt Is Hardware Development
l
Looks r e d ev! Broken?
a
hardw
Describe your experience with
(tapeout) toolchain in one word
No Response
9%
Neutral Negative
34.0% 56.5%
Survey of ~ 50 Students

10
 Lowering Costs & Barriers to Chip Design
● Is Hardware Development Broken?

Research $
Saved

Source: NIST

11
 Lowering Costs & Barriers to Chip Design
● Is Hardware Development Broken?

Research $
Saved

Source: ISSCC’23 - Plenary

Source: NIST

12
 Lowering Costs & Barriers to Chip Design
● Is Hardware Development Broken?

Research $
Saved

Source: ISSCC’23 - Plenary

- T. Ansell and M. Saligane, "The Missing Pieces of Open Design Enablement: A

Recent History of Google Efforts : lnvited Paper," 2020 IEEE/ACM
International Conference On Computer Aided Design (ICCAD), San Diego, Source: NIST
CA, USA, 2020.
13
 On-Going Projects & Contributions

Open-Source IC & tapeouts

➔ 1st Open Silicon Results
NIST Nanofabrication Accelerator
➔ 1st Open Nanotechnology Platform
➔ Cryogenic CMOS
Low-Power IC Design
➔ Rapid Prototyping for Wearables & Bio Applications
 On-Going Projects & Contributions

Open-Source IC & tapeouts

➔ 1st Open Silicon Results
NIST Nanofabrication Accelerator
➔ 1st Open Nanotechnology Platform
➔ Cryogenic CMOS
Low-Power IC Design
➔ Rapid Prototyping for Wearables & Bio Applications
 Overview of FASOC
Fully Autonomous SoC Synthesis

● DARPA IDEA Program (OpenROAD and FASoC)

● Multi-University and Industry effort
● Multiple tape-outs in TSMC 65, GF12LP, SkyWater 130nm

Temp
Senses
First automated SoC
Fab’d in TSMC65nm DCDC ARM

2.6mm
SRAM
M0 core 64KB
SRAM

2mm
ADC
s
https://fasoc.engin.umich.edu/

LDO
BT Tx

s
PLL

2.6mm 2mm
TSMC65LP SoC (2019-08) GF12LP SoC (2020-10) 16
 Overview of OpenFASOC
Fully Autonomous SoC Synthesis

● DARPA IDEA Program, now funded by Google, NIST and others CHIPS Alliance Workshop
● Multiple tape-outs in TSMC 65, GF12LP, SKY130, GF180MCU, Intel 16 2021-11

OpenPOWER AI Workshop
IBM - 2022-11

GF 12-nm GF 180 Intel 16-nm

CHIPS Alliance Technology Update
2022-12

MPW0
openfasoc.readthedocs.io
SKY130

+ more!
RISCV Alliance Japan
2022-12

MPW1 MPW2 MPW4 MPW5 MPW6 MPW7 MPW8

<3 years, <10 people!

 Automated & Open Nanotechnology Platform
CMOS Integration Critical for Measurements
● New devices and materials are continually
proposed by the academic community
Resistive switching Phase Change Memory Spin Torque Transfer Conductive Bridge
memory (ReRAM) (PCM) (STT - RAM) (CB-RAM)

2D Materials Nanotubes

Source: Brian Hoskins, NIST

Reliable monolithic integration is a

requirement for experimental
prototyping
Open Cryogenic CMOS
 Automated & Open Nanotechnology Platform

The Nanofab Accelerator project aims to

design an active substrate wafer for
novel device research.

This project is a community-driven effort

involving many universities and labs.
New devices are
fabricated on top of our
“active wafer”
Open-Source NanoFab Contributions Gallery
A symmetrical CV / Charge Pumping Measurement Platform

Stimulus Generator Exposed Pads

For Device
Fabrication
Open-Source NanoFab Contributions Gallery
A Array for Memristor Memory
Prototyping
Open-Source NanoFab Contributions Gallery
A Array for Memristor Memory
Prototyping

2T1D Cell for NanoFab

Resistive Memory Device
Open-Source NanoFab Contributions Gallery
A General-Purpose Digital PLL for On-Chip Homodyne Detection
Mass Generation of Cryogenic OPAMPs
Human Designed OPAMP using 4K Mass Generation of OPAMPs Using Our
Open-Source Transistor Models Framework
OpenFASOC’s GLayout Framework

OpenFASoC
Glayout: Programmatic Generators Tools &
Dependencies

Reinforcement Learning
PDK Custom Design
Pcells
Cloud Infrastructure

Abstraction API + Routing

GDSFactory

Common Python API Logic Synthesis

Yosys / ABC

Template Generators (AMS) OpenRoad APR

Power Management Sensors Netgen
Magic
D-LDO PLL SAR ADC SCPA Klayout

Thorough simulation of 10000 opamp takes only a couple of hours!

OpenFASOC’s GLayout Framework

On Cloud, Fully Pythonic Analog Layout & Netlist Generation

Thorough simulation of 10000 opamp takes only a couple of hours!
Mass Generation of Cryogenic OPAMPs

M5 M3,4 M5 C1

M6 M2 M6
Source
Follower
(for testing)

M1

26 Tunable Parameters

SKY130 Layouts GF180 Layouts

Fully parameterized, hierarchical, PDK-independent description of circuit layout

Mass Evaluation of Cryogenic OPAMPs

Automated batch
evaluation of generated
circuits.

The backend is made of

open source simulators:
ngSpice / xyce.

Massively parallelization
utilizing more than 512
CPU cores on the cloud is
now a reality
Automated PMU for Low-K Operation
Measurement Results
Maximum Eff. Point Robust against Temperature Variation

Cryogenic Test Setup

Experiments have shown

constant behavior across a wide
temperature range, down to
cryogenic temperatures.

Power Efficiency & Output Voltage Emulated Closed-Loop Response

Versus Load Current, Clock Freq., and Temperature At Maximum-Power Tracking
Building Confidence in Open Design!
 Building Confidence in Open Design
Start of
Skywater’s Open
MPW Program

MPW1
Dec …. Jun Aug Oct Dec Feb Apr Jun Aug Oct Dec Feb Apr Jun

End of 2021 2022 2024

2020
32
 Building Confidence in Open Design
Start of
Skywater’s Open
MPW Program

SKY130

MPW1 MPW2
Dec …. Jun Aug Oct Dec Feb Apr Jun Aug Oct Dec Feb Apr Jun

End of 2021 2022 2024

2020
33
 Building Confidence in Open Design
Tapeout throughDARPA IDEA Program GF 12-nm

● 1st tapeout in GF12LP using open source

tools

● Signoff using PT
○ @ TT|25C|0.8v|funcmax
350MHz
● Temperature sensors
ADPLL
○ TRANGE: -20 to 100oC SCPA
○ Error: +/- 0.2oC (post-PEX)
SKY130

BLE-TX

MPW1 MPW2 MPW3

Dec …. Jun Aug Oct Dec Feb Apr Jun Aug Oct Dec Feb Apr Jun
○ ADPLL supports 1.8 to 2.7GHz

End of 2021 2022 Feb May

2024
2020 24th 28th

34
 Building Confidence in Open Design
Start of
DARPA IDEA
Nanofab. Accelerator
Skywater’s Open
MPW Program Program program w. NIST

4 Testchips Already!
Big tapeout mid-June
GF 12-nm

SKY130 1st TO 2nd TO 3rd TO 4th TO

NIST’s
Nanofabrication
Tapeout

MPW1 MPW2 MPW3 MPW4 MPW5 MPW6 MPW7 MPW8

Dec …. Jun Aug Oct Dec Feb Apr Jun Aug Oct Dec Feb Apr Jun

End of 2021 2022 Feb May

2024
2020 24th 28th

35
 Building Confidence in Open Design
Start of Nanofab. Globalfoundries
Skywater’s Open DARPA IDEA Accelerator Open MPW
MPW Program Program program w. NIST Program Accelerating Fitbit’s
Custom Silicon Goals!

GF 180 GF 180
GF 12-nm

MPW0

Project w. Fitbit
SKY130 1st TO 2nd TO 3rd TO 4th TO
NIST’s
Nanofabrication
Tapeout

MPW1 MPW2 MPW3 MPW4 MPW5 MPW6 MPW7 MPW8

Dec …. Jun Aug Oct Dec Feb Apr Jun Aug Oct Dec Feb Apr Jun

End of 2021 2022 Feb May

2024
2020 24th 28th

36
 Building Confidence in Open Design
Start of Nanofab. Globalfoundries Intel’s
Skywater’s Open DARPA IDEA Accelerator Open MPW University Shuttle
MPW Program Program program w. NIST Program
Intel 16-nm Intel 16-nm

GF 180 GF 180
GF 12-nm

MPW0

Project w. Fitbit
SKY130 1st TO 2nd TO 3rd TO 4th TO
NIST’s
Nanofabrication
Tapeout
We Need More
MPW1 MPW2 MPW3 MPW4 MPW5 MPW6 MPW7 MPW8
Dec …. Jun Aug Oct Dec Feb Apr Jun Aug Oct Dec Feb Apr Jun Shuttles!
End of 2021 2022 Feb May
2024
2020 24th 28th

37
 Tape Outs in Intel 16 - OpenTitan SoC
● Tapeout in Intel 16nm using open tools
● PD and timing optimization using OpenROAD
● Used a modular flow to smoothly fill-in the
gaps using proprietary tools
● Bundled with temperature sensors generated
using OpenFASoC

Photograph of the Testboard

Floorplan of Intel 16 tapeout Including

Opentitan, Temperature sensor array
and crossbar using OpenROAD
38
 On-Going Projects & Contributions

Open-Source IC & tapeouts

➔ 1st Open Silicon Results
NIST Nanofabrication Accelerator
➔ 1st Open Nanotechnology Platform
➔ Cryogenic CMOS
Low-Power IC Design
➔ Rapid Prototyping for Wearables & Bio Applications
GF180 Laser Induced Graphene Sensor Platform
Carrier PCB with
AFE (WIP)

C-DAC

OPAMP 1

SAR
OPAMP 2
ADC
GF180 Mixed-Signal Sensing
Chip Developed using
Open Source Tools
Custom Polymer-based Laser
Induced Graphene (LIG) Sensor
 CMOS IC for DNA Synthesis and Bio Sensing
Fully addressable electrode array controlled by CMOS
IC to parallelize DNA synthesis

Synthesis Steps
Top Diagram

Phosphoramidite Method
 CMOS IC for DNA Synthesis and Bio Sensing
Beyond DNA synthesis, the CMOS IC proposed could
also perform multiple types of Bio sensing

Eg.
- pH Sensing during Synthesis DNA Origami Scaffold Sensing
- DNA Sequencing
- DNA Origami Scaffold Sensing
- Others possible Current Sensing

Circuit Diagram

pH-Voltage relationship in DNA Sequencing

Quinone Chemistry
CMOS IC for DNA Synthesis - Alea Biosciences Inc.

Voltammogram Graphs of Tap Water/ Vinegar

Pt
electrodes
Area Efficient High Speed ADC
● Implemented in Intel 16nm
● Core area: 0.0036mm2
● Simulated ENOB: 6.5, SNDR: 40.9, SFDR: 55.2, fs=2.5GHz
○ w/ frequency max 1000g transient noise
● FoMw(Walden FoM): 21.2fJ/conv.steps
Cryogenic Quantum Current Generator
● An experimental current
source using quantum
effects in FinFET.
● Ultra high precision and
DECAP
stability. SPI

● Chip will be back this year

Experiment TILE
What is next?
Bridging Gaps between Hardware & Software

Make custom silicon easier to

build, at scale, just like
software
“My god,
$ gcc -OSilicon it’s full of software!”

47
Bridging Gaps between Hardware & Software
Packaging
conda-eda
github.com/hdl/conda-eda
conda install --channel litex-hub \
open_pdks.sky130a \
openlane \
xls “My god,
it’s full of software!”
Reproducible, Reusable
Jupyter Notebook
github.com/chipsalliance/silicon-notebooks/
48
Bridging Gaps between Hardware & Software

● OpenFASOC GitHub Repo is mainly Code and

Documentation

“My god,
it’s full of software!”

49
Bridging Gaps between Hardware & Software

● OpenFASOC GitHub Repo is mainly Code and

Documentation
○ Auditable and Transparent
○ Regression Tests
○ Systematic Metrics Extraction
○ Dashboards “My god,
it’s full of software!”

50
IEEE SSCS TC OSE
Activities
AURA Program

52
53
54
55
Notebook Code a Chip Competition at
ISSCC’23

56
Notebook Code a Chip Competition at VLSI’23

57
“Code-a-Chip” Notebook Competition at
ISSCC’24
● IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
○ https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io

58
180 Attendees!! Record attendance
among all workshops at VLSI Symposium

59
Reproducible, Reusable Results using Notebooks & Open PDKs
● Selected by the US Consulate in Japan to organize workshops and training for the
Japanese Workforce in Kyushu Area
○ Partnering with local Universities

60
The End!
Traditional vs Automated
Analog Design
 Analog vs. Digital design flow
Automated

Manual/Custom

● Analog design flow

Significant number of manual
and custom steps.

● Digital design (grid-based)

flow
Almost entirely automated.
63
 Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator
ISSCC-2015

Temperature Sensor D-LDO

Automated

Manual/Custom ISSCC-2017 CICC-2010

DC-DC Converter
PLL

64
 Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator
ISSCC-2015

Temperature Sensor D-LDO

Automated

Manual/Custom ISSCC-2017 CICC-2010

DC-DC Converter
PLL

65
 Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator
ISSCC-2015

Temperature Sensor D-LDO

Automated

Manual/Custom ISSCC-2017 CICC-2010

DC-DC Converter
PLL

ALIGN Automated Layout Generator

66
 Initially only proprietary design flow
SAR ADC Block Diagram

Temperature Sensor D-LDO

PLL DC-DC Converter

Automated

Manual/Custom

67