UNIT-III

I/O INTERFACE
Introduction:

Any application of a microprocessor based system requires the transfer of data

between external circuitry to the microprocessor and microprocessor to the external circuitry.
User can give information to the microprocessor based system using keyboard and user can
see the result or output information from the microprocessor based system with the help of
display device. The transfer of data between keyboard and microprocessor, and
microprocessor and display device is called input/output data transfer or I/O data transfer.
This data transfer is done with the help of I/O ports.

Input port:

It is used to read data from the input device such as keyboard. The simplest form of
input port is a buffer. The input device is connected to the microprocessor through buffer,
as shown in the fig.1. This buffer is a tri-state buffer and its output is available only when
enable signal is active. When microprocessor wants to read data from the input device
(keyboard), the control signals from the microprocessor activates the buffer by asserting
enable input of the buffer. Once the buffer is enabled, data from the input device is available
on the data bus. Microprocessor reads this data by initiating read command.

Output port:
 It is used to send data to the output device such as display from the
microprocessor. The simplest form of output port is a latch. The output device is connected
to the microprocessor through latch, as shown in the fig.2. When microprocessor wants to
send data to the output device is puts the data on the data bus and activates the clock signal
of the latch, latching the data from the data bus at the output of latch. It is then available at the
output of latch for the output device.

Serial and Parallel Transmission:

In telecommunications, serial transmission is the sequential transmission of signal

elements of a group representing a character or other entity of data. Digital serial
transmissions are bits sent over a single wire, frequency or optical path sequentially.
Because it requires less signal processing and less chance for error than parallel
transmission, the transfer rate of each individual path may be faster. This can be used
over longer distances as a check digit or parity bit can be sent along it easily.
In telecommunications, parallel transmission is the simultaneous transmission of the
signal elements of a character or other entity of data. In digital communications, parallel
transmission is the simultaneous transmission of related signal elements over two or more
separate paths. Multiple electrical wires are used which can transmit multiple bits
simultaneously, which allows for higher data transfer rates than can be achieved with
serial transmission. This method is used internally within the computer, for example the
internal buses, and sometimes externally for such things as printers, The major issue with this
is "skewing" because the wires in parallel data transmission have slightly different
properties (not intentionally) so some bits may arrive before others, which may corrupt the
message. A parity bit can help to reduce this. However, electrical wire parallel data
transmission is therefore less reliable for long distances because corrupt transmissions are far
more likely.
Interrupt driven I/O:

In this technique, a CPU automatically executes one of a collection of special

routines whenever certain condition exists within a program or a processor system. Example
CPU gives response to devices such as keyboard, sensor and other components when they
request for service. When the CPU is asked to communicate with devices, it services the
devices. Example each time you type a character on a keyboard, a keyboard service routine
is called. It transfers the character you typed from the keyboard I/O port into the processor
and then to a data buffer in memory.
The interrupt driven I/O technique allows the CPU to execute its main program and
only stop to service I/O device when it is told to do so by the I/O system as shown in fig.3.
This method provides an external asynchronous input that would inform the processor that it
should complete whatever instruction that is currently being executed and fetch a new
routine that will service the requesting device. Once this servicing is completed, the
processor would resume exactly where it left off.
 An analogy to the interrupt concept is in the classroom, where the professor serves as
CPU and the students as I/O ports. The classroom scenario for this interrupt analogy will be
such that the professor is busy in writing on the blackboard and delivering his lecture.
The student raises his finger when he wants to ask a question (student requesting for
service). The professor then completes his sentence and acknowledges student‟s request by
saying “YES” (professor acknowledges the interrupt request). After acknowledgement from
the professor, student asks the question and professor gives answer to the question
(professor services the interrupt). After that professor continues its remaining lecture form
where it was left.

PIO 8255:

The parallel input-output port chip 8255 is also called as programmableperipheral

input-output port. The Intel‟s 8255 are designed for use with Intel‟s 8-bit, 16-bit and
higher capability microprocessors. It has 24 input/output lineswhich may be individually
programmed in two groups of twelve lines each, orthree groups of eight lines.
The two groups of I/O pins are named as Group A and Group B. Each of thesetwo
groups contains a subgroup of eight I/O lines called as 8-bit port and anothersubgroup of four
lines or a 4-bit port. Thus Group A contains an 8-bit port Aalong with a 4-bit port C upper.

The port A lines are identified by symbols PA0-PA7 while the port C lines are
identified as PC4-PC7 similarly. Group B contains an 8-bit port B, containing lines PB0- PB7
and a 4-bit port C with lower bits PC0-PC3. The port C upper and port C lower can be used
in combination as an 8-bit port C. Both the port Cs is assigned the same address. Thus one
may have either three 8-bit I/O ports or two 8-bit and two 4-bit I/O ports from 8255. All of
these ports can function independently either as input or as output ports. This can be achieved
by programming the bits of an internal register of 8255 called as control word register
(CWR). The internal block diagram and the pin configuration of 8255 are shown in figs.

The 8-bit data bus buffer is controlled by the read/write control logic. The read/write
control logic manages all of the internal and external transfer of both data and control words.
RD, WR, A1, A0 and RESET are the inputs, provided by the microprocessor to
READ/WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to
interface the 8255 internal data bus with the external system data bus. This buffer receives
or transmits data upon the execution of input or output instructions by the microprocessor.
The control words or status information is also transferred through the buffer.

Pin Diagram of 8255A

The pin configuration of 8255 is shown in fig.

 The port A lines are identified by symbols PA0-PA7 while the port C lines are
 Identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing
lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and
port C lower can be used in combination as an 8-bit port C.

 Both the port C is assigned the same address. Thus one may have either three
8-bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can
function independently either as input or as output ports. This can be achieved
by programming the bits of an internal register of 8255 called as control word
 register (CWR).
 The 8-bit data bus buffer is controlled by the read/write control logic. The read/write
control logic manages all of the internal and external transfers of both data and
control words.
 RD,WR, A1, A0 and RESET are the inputs provided by the microprocessor to the
READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is
used to interface the 8255 internal data bus with the external system data bus.
 This buffer receives or transmits data upon the execution of input or output
instructions by the microprocessor. The control words or status information is also
transferred through the buffer.

The signal description of 8255 is briefly presented as follows:

 PA7-PA0: These are eight port A lines that acts as either latched output or buffered
input lines depending upon the control word loaded into the control word
register.
 PC7-PC4: Upper nibble of port C lines. They may act as either output latches or
input buffers lines.
 This port also can be used for generation of handshake lines in mode1 or mode2.
 PC3-PC0: These are the lower port C lines; other details are the same as PC7-
PC4 lines.
 PB0-PB7: These are the eight port B lines which are used as latched output lines or
buffered input lines in the same way as port A.
 RD: This is the input line driven by the microprocessor and should be low to
indicate read operation to 8255.
 WR: This is an input line driven by the microprocessor. A low on this line
indicates write operation.
 CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to
RD and WR signals, otherwise RD and WR signal are neglected.
 D0-D7: These are the data bus lines those carry data or control word to/from the
microprocessor.
 RESET: Logic high on this line clears the control word register of 8255. All ports are
set as input ports by default after reset.
 A1-A0: These are the address input lines and are driven by the microprocessor.
 These lines A1-A0 with RD, WR and CS from the following operations for 8255.
These address lines are used for addressing any one of the four registers, i.e.
three ports and a control word register as given in table below.

In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0
and A1 pins of 8255 are connected with A1 and A2 respectively.
Modes of Operation of 8255

 These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset
mode (BSR).
 In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only
port C (PC0-PC7) can be used to set or reset its individual port bits.
 Under the I/O mode of operation, further there are three modes of operation of
8255, so as to support different types of applications, mode 0, mode 1 and mode 2.
 BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on
D0 of the control word. The bit to be set or reset is selected by bit select flags D3, D2
and D1 of the CWR as given in table.

I/O Modes:

a) Mode 0 (Basic I/O mode): This mode is also called as basic input/output Mode. This
mode provides simple input and output capabilities using each of the threeports. Data can be
simply read from and written to the input and output portsrespectively, after appropriate
initialization.
The salient features of this mode are as listed below:

1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) are
available. The two 4-bit ports can be combined used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configurations are
possible.

 All these modes can be selected by programming a register internal to 8255known as

CWR.
 The control word register has two formats. The first format is valid for I/O modes
of operation, i.e. modes 0, mode 1 and mode 2 while the second format is valid for
bit set/reset (BSR) mode of operation.

These formats are shown in following fig.

b) Mode 1: (S t r o b e d input/output mode) in this mode the handshaking control the
input and output action of the specified port. Port C lines PC0-PC2, provide strobe or
handshake lines for port B. This group which includes port B and PC0-PC2 is called as
group B for Strobed data input/output. Port C lines PC3-PC5 provides strobe lines for port
A. This group including port A and PC3-PC5 from group A. Thus port C is utilized for
generating handshake signals.

The salient features of mode 1 are listed as follows:

1. Two groups – group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs and outputs
both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B
andPC3-PC5 are used to generate control signals for port A. the lines PC6, PC7
may be used as independent data lines.
The control signals for both the groups in input and output modes are explained as
follows:

Input control signal definitions (mode 1):

• STB (Strobe input) – If this lines falls to logic low level, the data available at 8-
bit input port is loaded into input latches.
• IBF (Input buffer full) – If this signal rises to logic 1, it indicates that data has
been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low
on STB and is reset by the rising edge of RD input.
• INTR (Interrupt request) – This active high output signal can be used to
interrupt the CPU whenever an input device requests the service. INTR is set by a
high STB pin and a high at IBF pin. INTE is an internal flag that can be
controlled by the bit set/reset mode of either PC4 (INTEA) or PC2 (INTEB) as
shown in fig.
• INTR is reset by a falling edge of RD input. Thus an external input device can be
request the service of the processor by putting the data on the bus and
sending the strobe signal.

Output control signal definitions (mode 1):

• OBF (Output buffer full) – This status signal, whenever falls to low, indicates
that CPU has written data to the specified output port. The OBF flip- flop will
beset by a rising edge of WR signal and reset by a low going edge at the ACK
input.
• ACK (Acknowledge input) – ACK signal acts as an acknowledgement to be given
by an output device. ACK signal, whenever low, informs the CPU that the data
transferred by the CPU to the output device through the port is received by the
output device.
• INTR (Interrupt request) – Thus an output signal that can be used to interrupt
the CPU when an output device acknowledges the data received from the
CPU.INTR is set when ACK, OBF and INTE are 1. It is reset by a

Falling edge on WR input. The INTEA and INTEB flags are controlled by the bit set-
reset mode ofPC6 and PC2 respectively.
c) Mode 2 (Strobed bidirectional I/O): This mode of operation of 8255 is also called as
strobed bidirectional I/O. This mode of operation provides 8255 with additional features for
communicating with a peripheral device on an 8-bit data bus. Handshaking signals are
provided to maintain proper data flow and synchronization between the data transmitter
and receiver. The interrupt generation and other functions are similar to mode 1.
In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The Rd and WR
signals decide whether the 8255 is going to operate as an input port or output port.

The Salient features of Mode 2 of 8255 are listed as follows:

1. The single 8-bit port in group A is available.

2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.
3. Three I/O lines are available at port C.( PC2 – PC0 )
4. Inputs and outputs are both latched.

5. The 5-bit control port C (PC3-PC7) is used for generating / accepting

handshake signals for the 8-bit data transfer on port A.

Control signal definitions in mode 2:

 INTR – (Interrupt request) As in mode 1, this control signal is active high and
is used to interrupt the microprocessor to ask for transfer of the next data byte
to/from it. This signal is used for input (read) as well as output (write) operations.
 Control Signals for Output operations:
 OBF (Output buffer full) – This signal, when falls to low level, indicates that
the CPU has written data to port A.
 ACK (Acknowledge) This control input, when falls to logic low level,
Acknowledges that the previous data byte is received by the destination and
next byte may be sent by the processor. This signal enables the internal tristate
buffers to send the next data byte on port A.
 INTE1 ( A flag associated with OBF ) This can be controlled by bit set/resetmode
with PC6.

Control signals for input operations:

 STB (Strobe input)a low on this line is used to strobe in the data into the input
Latches of 8255.
 IBF (Input buffer full) when the data is loaded into input buffer, this signal rises to
logic „1‟. This can be used as an acknowledge that the data has been received by
the receiver.
 The waveforms in fig show the operation in Mode 2 for output as well as input
port.
 Note: WR must occur before ACK and STB must be activated before RD.

 The following fig shows a schematic diagram containing an 8-bit bidirectional

 port, 5-bit control port and the relation of INTR with the control pins. Port B can
either be set to Mode 0 or 1 with port A( Group A ) is in Mode 2.
 Mode 2 is not available for port B. The following fig shows the control word.
 The INTR goes high only if IBF, INTE2, STB and RD go high or OBF,
 INTE1, ACK and WR go high. The port C can be read to know the status of the
peripheral device, in terms of the control signals, using the normal I/O
instructions.
Interfacing Analog to Digital Data Converters:

 In most of the cases, the PIO 8255 is used for interfacing the analog to digital
converters with microprocessor.
 We have already studied 8255 interfacing with 8086 as an I/O port, in previous
section. This section we will only emphasize the interfacing techniques of analog to
digital converters with 8255.
 The analog to digital converters is treated as an input device by the microprocessor
that sends an initializing signal to the ADC to start the analogy to digital data
conversation process. The start of conversation signal is a pulse of a specific
duration.
 The process of analog to digital conversion is a slow
 Process and the microprocessor have to wait for the digital data till the conversion is
over. After the conversion is over, the ADC sends end of conversion EOC signal to
inform the microprocessor that the conversion is over and the result is ready at the
output buffer of the ADC. The set asks of issuing an SOC pulse to ADC, reading
EOC signal from the ADC and reading the digital output of the ADC are carried out
by the CPU using 8255 I/O ports.
 The time taken by the ADC from the active edge of SOC pulse till the active edge of
EOC signal is called as the conversion delay of the ADC.
 It may range anywhere from a few microseconds in caseof fast ADC to even a few
hundred milliseconds in case of slow ADCs.
 The available ADC in the market use different conversion techniques for
conversion of analog signal to digitals. Successive approximation techniques and
dual slope integration techniques are the most popular techniques used in the
integrated ADC chip.
 General algorithm for ADC interfacing contains the following steps:
 Ensure the stability of analog input, applied to the ADC.
 Issue start of conversion pulse to ADC
 Read end of conversion signal to mark the end of conversion processes.
 Read digital data output of the ADC as equivalent digital output.
 Analog input voltage must be constant at the input of the ADC right from the start of
conversion till the end of the conversion to get correct results. This may be
ensured by as ample and hold circuit which samples the analog signal and holds it
constant for specific time duration. The microprocessor may issue a hold signal to the
sample and hold circuit.
 If the applied input changes before the complete conversion process is over, the
digital equivalent of the analog input calculated by the ADC may not be correct.

ADC 0808/0809:

 The analog to digital converter chips 0808 and 0809 are 8-bit CMOS,
successive approximation converters. This technique is one of the fast
techniques for analog to digital conversion. The conversion delay is 100µs at
a clock frequency of 640 KHz, which is quite low as compared to other
converters. These converters do not need any external zero or full scale
adjustments as they are already taken care of by internal circuits.
 These converters internally have a 3:8 analog multiplexer so that at a time
eight different analog conversion by using address lines - ADD A, ADD B,
ADD C, as shown. Using these address inputs, multichannel data
 acquisition system can be designed using a single ADC. The CPU may
drive these lines using output port lines in case of multichannel
applications. In case of single input applications, these may be hardwired to
select the proper input.
 There are unipolar analog to digital converters, i.e. they are able to convert
only positive analog input voltage to their digital equivalent. These chips do
not contain any internal sample and hold circuit.
 If one needs a sample and hold circuit for the conversion of fast signal
into equivalent digital quantities, it has to be externally connected at each
of the analog inputs.

Fig (1) and Fig (2) show the block diagrams and pin diagrams for ADC 0808/0809.

Table.1

Analog I/P Address lines

selected C B A
I/P 0 0 0 0
I/P 1 0 0 1
I/P 2 0 1 0
I/P 3 0 1 1
I/P 4 1 0 0
I/P 5 1 0 1
I/P 6 1 1 0
I/P 7 1 1 1

Fig.1 Block Diagram of ADC 0808/0809

Fig.2 Pin Diagram of ADC 0808/0809

Some Electrical Specifications Of The ADC 0808/0809 Are Given In Table.2.

Table.2

The Timing Diagram Of Different Signals Of Adc0808 Is Shown In Fig.3

 Fig.3 Timing Diagram Of ADC 0808.

Interfacing ADC0808 with 8086

Interfacing Digital To Analog Converters:

The digital to analog converters convert binary numbers into their analog
equivalent voltages. The DAC find applications in areas like digitally controlled gains,
motor speed controls, programmable gain amplifiers, etc.

DAC0800 8-bit Digital to Analog Converter

 The DAC 0800 is a monolithic 8-bit DAC manufactured by National Semiconductor.

 It has settling time around 100ms and can operate on a range of power supply voltages
i.e. from 4.5V to +18V.
 Usually the supply V+ is 5V or +12V.
 The V-pin can be kept at a minimum of -12V.

Pin Diagram of DAC 0800

Interfacing DAC0800 with 8086 Ad

7523 8-Bit Multiplying DAC:
 Intersil‟s AD 7523 is a 16 pin DIP, multiplying digital to analog converter,
containing R-2R ladder(R=10KΩ) for digital to analog conversion along with
single pole double through NMOS switches to connect the digital inputs to the
ladder.

Pin Diagram of AD7523

 The supply range extends from +5V to +15V , while Vref may be anywhere
 between -10V to +10V. The maximum analog output voltage will be +10V,
when all the digital inputs are at logic high state. Usually a Zener is connected
between OUT1 and OUT2 to save the DAC from negative transients.
 An operational amplifier is used as a current to voltage converter at the output
of AD 7523 to convert the current output of AD7523 to a proportional output
voltage.

 It also offers additional drive capability to the DAC output. An external feedback
resistor acts to control the gain. One may not connect any external feedback
resistor, if no gain control is required.

Interfacing AD7523 with 8086 Stepper

Motor Interfacing:
 A stepper motor is a device used to obtain an accurate position control of rotating
shafts. It employs rotation of its shaft in terms of steps, rather than continuous
rotation as in case of AC or DC motors. To rotate the shaft of the stepper motor, a
sequence of pulses is needed to be applied to the windings of the stepper motor, in a
proper sequence.
 The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to its number of internal teeth on its rotor. The stator teeth and the
rotor teeth lock with each other to fix a position of the shaft.
 With a pulse applied to the winding input, the rotor rotates by one teeth position or an
angle x. The angle x may be calculated as:

X=3600/no. of rotor teeth

 After the rotation of the shaft through angel x, the rotor locks itself with the next
tooth in the sequence on the internal surface of stator.
 The internal schematic of a typical stepper motor with four windings is shown in
fig.1.
 The stepper motors have been designed to work with digital circuits. Binary
level pulses of 0-5V are required at its winding inputs to obtain the rotation of
shafts. The sequence of the pulses can be decided, depending upon the required
motion of the shaft.
  Fig.2 shows a typical winding arrangement of the stepper motor.
 Fig.3 shows conceptual positioning of the rotor teeth on the surface of rotor, for a
six teeth rotor.

Fig.1 Internal schematic of a four winding stepper motor

Fig.2 Winding arrangement of a stepper motor.

Fig.3 Stepper motor rotor

 The circuit for interfacing a winding Wn with an I/O port is given in fig.4. Each of the
windings of a stepper motor needs this circuit for its interfacing with the output
port. A typical stepper motor may have parameters like torque 3 Kg-cm, operating
voltage 12V, current rating 0.2 A and a step angle 1.80 i.e. 200 steps/revolution
(number of rotor teeth).
  A simple schematic for rotating the shaft of a stepper motor is called a wave
scheme. In this scheme, the windings Wa, Wb, Wc and Wd are applied with the
required voltages pulses, in a cyclic fashion. By reversing the sequence of excitation,
the direction of rotation of the stepper motor shaft may be reversed.
 Table.1 shows the excitation sequences for clockwise and anticlockwise rotations.
Another popular scheme for rotation of a stepper motor shaft applies pulses to two
successive windings at a time but these are shifted only by one position at a time. This
scheme for rotation of stepper motor shaft is shown in table2.

Fig.4 interfacing stepper motor winding.

Table.1 Excitation sequence of a stepper motor using wave switching scheme.

Motion step A B C D
1 1 0 0 0
2 0 1 0 0
Clock 3 0 0 1 0
Wise Direction 4 0 0 0 1
5 1 0 0 0
1 1 0 0 0
2 0 0 0 1
Anti clock
wise 3 0 0 1 0
Direction 4 0 1 0 0
5 1 0 0 0
 Table.2 An alternative scheme for rotating stepper motor shaft

Motion step A B C D
1 0 0 1 1
2 0 1 1 0
Clock wise 3 1 1 0 0
Direction 4 1 0 0 1
5 0 0 1 1
1 0 0 1 1
2 1 0 0 1
Anti clock
wise 3 1 1 0 0
Direction 4 0 1 1 0
5 0 0 0 0

Keyboard Interfacing

 In most keyboards, the key switches are connected in a matrix of Rows and
Columns.
 Getting meaningful data from a keyboard requires three major tasks:
1. e t e c t a k e y p r e s s
2. D e b o u n c e t h e k e y p r e s s .
3. Encode the keypress (produce a standard code for the pressed
key).
 Logic „0‟ is read by the microprocessor when the key is pressed.

Key Debounce:
Whenever a mechanical push-bottom is pressed or released once,the mechanical
components of the key do not change the positionsmoothly; rather it generates a transient
response. These may be interpreted as the multiple pressures and responded accordingly.
  The rows of the matrix are connected to four output Port lines, &columns are
connected to four input Port lines.
 When no keys are pressed, the column lines are held high by the pull-up resistors
connected to +5v.
 Pressing a key connects a row & a column.
 To detect if any key is pressed is to output 0‟s to all rows & then check columns to
see it a pressed key has connected a low (zero) to a column.
 Once the columns are found to be all high, the program enters another loop, which
waits until a low appears on one of the columns i.e indicating a key press.
 A simple 20/10 m sec delay is executed to debounce task.
 After the debounce time, another check is made to see if the key is still pressed. If
the columns are now all high, then no key is pressed & the initial detection was
caused by a noise pulse.
 To avoid this problem, two schemes are suggested:
1. Use of Bistable multivibrator at the output of the key to debounce it.
2. The microprocessor has to wait for the transient period (at least
for 10 ms), so that the transient response settles down and reaches a steady
state.
 If any of the columns are low now, then the assumption is made that it was a valid
key press.

 The final task is to determine the row & column of the pressed key &convert this
information to Hex-code for the pressed key.
 The 4-bit code from I/P port & the 4-bit code from O/P port (row &column) are
converted to Hex-code.
Interfacing 4x4 keyboard

Display Interface
Interfacing multiplexed 7-segment display
8259 PIC
Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5
hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086
microprocessors respectively. But by connecting Intel 8259 with these
microprocessors, we can increase their interrupt handling capability. Intel 8259
combines the multi-interrupt input sources into a single interrupt output.
Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example,
Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085
microprocessor from 5 to 8 interrupt levels.
Features of Intel 8259 PIC are as follows:
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt
level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by
cascading further 8259 PICs.
5. Clock cycle is not required.

Pin Diagram of 8259 – We can see through above diagram that there are total
28 pins in Intel 8259 PIC where Vcc : 5V Power supply and Gnd : ground. Other
pins use are explained below. Block Diagram of 8259 PIC microprocessor –
 The
Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write
Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver and 3
registers- ISR, IRR, IMR.
1. Data bus buffer – This Block is used as a mediator between 8259 and
8085/8086 microprocessor by acting as a buffer. It takes the control word
from the 8085 (let say) microprocessor and transfer it to the control logic of
8259 microprocessor. After selection of Interrupt by 8259 microprocessor
(based on priority of the interrupt), it transfer the opcode of the selected
Interrupt and address of the Interrupt service sub routine to the other
connected microprocessor. The data bus buffer consists of 8 bits
represented as D0-D7 in the block diagram. Thus, shows that a maximum of
8 bits data can be transferred at a time.
2. Read/Write logic – This block works only when the value of pin CS is low
(as this pin is active low). This block is responsible for the flow of data
depending upon the inputs of RD and WR. These two pins are active low
pins used for read and write operations.
3. Control logic – It is the center of the PIC and controls the functioning of
every block. It has pin INTR which is connected with other microprocessor
for taking interrupt request and pin INT for giving the output. If 8259 is
enabled, and the other microprocessor Interrupt flag is high then this causes
 the value of the output INT pin high and in this way 8259 responds to the
request made by other microprocessor.
4. Interrupt request register (IRR) – It stores all the interrupt level which are
requesting for Interrupt services.
5. Interrupt service register (ISR) – It stores the interrupt level which are
currently being executed.
6. Interrupt mask register (IMR) – It stores the interrupt level which have to
be masked by storing the masking bits of the interrupt level.
7. Priority resolver – It examines all the three registers and set the priority of
interrupts and according to the priority of the interrupts, interrupt with highest
priority is set in ISR register. Also, it reset the interrupt level which is already
been serviced in IRR.
8. Cascade buffer – To increase the Interrupt handling capability, we can
further cascade more number of pins by using cascade buffer. So, during
increment of interrupt capability, CSA lines are used to control multiple
interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master
mode else in slave mode. In Non Buffered mode, SP/EN pin is used to specify
whether 8259 work as master or slave and in Buffered mode, SP/EN pin is used
as an output to enable data bus.

Advantages:

Interrupt Management: The 8259 PIC is designed to handle interrupts

efficiently and effectively, allowing for faster and more reliable processing of
interrupts in a system.
Flexibility: The 8259 PIC is programmable, meaning that it can be customized
to suit the specific needs of a given system, including the number and type of
interrupts that need to be managed.
Compatibility: The 8259 PIC is compatible with a wide range of
microprocessors, making it a popular choice for managing interrupts in many
different systems.
Multiple Interrupt Inputs: The 8259 PIC can manage up to 8 interrupt inputs,
allowing for the management of complex systems with multiple devices.
Ease of Use: The 8259 PIC includes simple interface pins and registers,
making it relatively easy to use and program.

Disadvantages:

Cost: While the 8259 PIC is relatively affordable, it does add cost to a system,
particularly if multiple PICs are required.
Limited Number of Interrupts: The 8259 PIC can manage up to 8 interrupt
inputs, which may be insufficient for some applications.
Complex Programming: Although the interface pins and registers of the 8259
PIC are relatively simple, programming the 8259 can be complex, requiring
careful attention to interrupt prioritization and other parameters.
Limited Functionality: While the 8259 PIC is a useful peripheral fo

8251 USART
8251 universal synchronous asynchronous receiver transmitter (USART) acts
as a mediator between microprocessor and peripheral to transmit serial data
into parallel form and vice versa.
1. It takes data serially from peripheral (outside devices) and converts into
parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into
serial form.
4. After converting data into serial form, it transmits it to outside device
(peripheral).
Block Diagram of 8251 USART –

It contains the
following blocks:
1. Data bus buffer – This block helps in interfacing the internal data bus of
8251 to the system data bus. The data transmission is possible between
8251 and CPU by the data bus buffer block.
2. Read/Write control logic – It is a control block for overall device. It controls
the overall working by selecting the operation to be done. The operation
selection depends upon input signals
as:

In this way, this unit selects one of the three registers- data buffer register,
control register, status register.
3. Modem control (modulator/demodulator) – A device converts analog
signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-
low pins of Modem.
 DSR: Data Set Ready signal is an input signal.
 DTR: Data terminal Ready is an output signal.
 CTS: It is an input signal which controls the data transmit circuit. RTS: It
is an output signal which is used to set the status RTS.
4. Transmit buffer – This block is used for parallel to serial converter that
receives a parallel byte for conversion into serial signal and further
transmission onto the common channel.
 TXD: It is an output signal, if its value is one, means transmitter will
transmit the data.
5. Transmit control – This block is used to control the data transmission with
the help of following pins:
 TXRDY: It means transmitter is ready to transmit data character.
  TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
 TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
6. Receive buffer – This block acts as a buffer for the received data.
 RXD: An input signal which receives the data.
7. Receive control – This block controls the receiving data.
 RXRDY: An input signal indicates that it is ready to receive the data.
 RXC: An active-low input signal which controls the data transmission rate
of received data.
 SYNDET/BD: An input or output terminal. External synchronous mode-
input terminal and asynchronous mode-output terminal.

Advantages:

Versatility: The 8251 USART can be used for both synchronous and
asynchronous communication, making it a versatile peripheral.
Error detection: The USART includes built-in error detection features, such as
parity checking, which help to ensure the accuracy of transmitted data.
Flow control: The USART includes flow control features, which allow for the
regulation of data transmission and reception, preventing data loss and
overloading.
Compatibility: The 8251 USART is compatible with a wide range of
microprocessors, making it a popular choice for serial communication in many
different systems.
Ease of use: The USART includes simple interface pins and registers, making
it relatively easy to use and program.

Disadvantages:

Limited speed: The 8251 USART has a relatively low maximum data transfer
rate of 115.2 kbps, which may be insufficient for some applications.
Limited buffer size: The USART has a small internal buffer size, which may
result in data loss if data is not read from the buffer in a timely manner.
Complex programming: Although the interface pins and registers of the
USART are relatively simple, programming the USART can be complex,
requiring careful attention to timing and other parameters.
Cost: While the 8251 USART is relatively affordable, it does add cost to a
system, particularly if multiple USARTs are required.
Limited functionality: While the 8251 USART is a useful peripheral for serial
communication, it does not include more advanced features, such as DMA
(direct memory access) or advanced error correction.