General DFT:
1) Why DFT needs to be done / what is the purpose of DFT? **
Ans-->To Find the manufacturing Defects in Chip.
2) What is DPPM/Yield - What is your DPPM?
Ans--> GPU/CPU -- 800; Automotive - as close to 0 (practically < 50).
3) What is the advantage/disadvantage of DFT?
Ans-->Advantages- To Find Manufacturing Defects in Chip from Fab/Foundry. By Using Fault
Dominance & Fault Collapsing, Number of Patterns can be Reduced.
Disadvantage-Area Overhead Increases.
4) Where in ASIC/Chip design flow, DFT comes into picture?
Ans-->After Synthesis (RTL-Gate Level Netlist).
ATPG:
1) Why transition coverage is low compared with stuck at? what is the difference between stuck
at and transition model? **
Ans-->1) Fault Model itself is complex.
2)Do not NEED Coverage on Resets, SE pins of Flop.
3)We Do not cover cross-clock (Asynchronous logic) in Transition.
4) We Do not cover False Paths, MCPs.
1b) on silicon what manufacturing issue will lead to stuck at defect / transition defect ?
Ans-->stuck at -- some node is tied to gnd/vdd (99.2).
transition - resistive defects (87.5).
2) I have a transition pattern set that has 95% coverage. How much stuck at coverage I will get if
I fault grade it to stuck at? *
Ans-->Fault Grading atspeed with respect to Stuck at will be done. Normally, Transition
Coverage has some Stuck at Coverage also,so stuck at coverage will be greater than 95%.
Set_pattern -external atspeed.stil
Set_fault_model stuck
Run_sim
Run_atpg
Fault Grading from Transition to Stuck at will be done.
3) what are different ways of at speed pattern generation?
Ans--> (LOC/LOS) **
4) what are advantages/disadvantages of LOC/LOS? *
Ans-->Advantages of LOC:-
1)No requirement like SE to be fast. No need of at speed scan enable.
Disadvantages of LOC:-
1)Less Controllability
2)Higher Pattern Count, controllability is less.
