aoslTNTERFAoEEXAMpLES 391

The following is an explanation of the four entries in the table.

troller, in a way (i) Mode 0
but also to set the (a) With A at 0 (i.e., ground), T5 is on, which turns on T2; the left side of the
motor is at ground. When A is at 0, it also means that T6 is off. Since there
is no path for current through R3 and R4, there is no voltage drop across
them, which in turn means that the base of T1 is at 12V. Hence T1 is off.
(b) The right-hand side of the circuit is a mirror image of the left. Therefore,
with B at 0, T4 is on and T3 is off. Hence the right side of the motor is also
at ground. The motor is off.
ff6
(ii) Mode 1
(a) A is still at 0, which means T1 is still off and T2 is still on; the left side of
the motor is at ground.
(b) With B at 5V (i.e., logic 1 on the port pin, which is being used for B), T7 is
off, which means that T4 is off. However, T8 is on, which generates a path
for the current through T8 to ground and also through R9 to the base ofT3.
There is a certain amount of voltage drop across R9, but the base of T3 is
close enough to ground for T3 to turn on; the right side of the motor is at
L2v.
(c) Therefore, the motor is on and as the left side of the motor is grounded and
the right side is connected to 12V, it would rotate in the opposite rotation.
DC motor (iii) Mode 2
7
(a) This is the mirror image of mode 1, resulting in T1 being on, T2 ofl T3 off,
run the motor in one
and T4 on. Hence the left side of the motor is at lzY and the right side is at
T3 are turned off.
ground. The motor runs forward.
To reverse the
other two transistors
(iv) Mode 3
(a) As in mode 2, with A at 5 V, the left side of rhe motor is at l2V.
side of the motor is
(b) As in mode 1, with B at 5 V, the right side of rhe motor is at l2V.
runs in the opposite
(c) Therefore, the motor is off.
the motor is off.
to 12V and the
12.1 () MICROCONTROLLER APPLICATION EHMPLE-STOPWATCH
are connected to the
Figure 12.19 shows the complete circuit diagram of a stopwatch. The circuit
be on at the same basically consists of four sets of seven-segment LEDs connected through the BCD
short circuit between to the seven-segment display code converter. This code converter (IC 7448) can
same is true for T3 also act as a driver for the display segments. The other circuit arrangements are
A and B, is given in for the power on, reset, and clock signals. The circuit with R and C has 0V, when
the power is off. When the power is switched on, the capacitor starts charging
pins and gradually rises towards the supply voltage of 5 V. This applies a logic high
voltage of 5 V, which gradually decreases towards 0V at the RST pin. The RST is
the active high reset signal and has to be applied for at least 24 clockperiods. The
RC combination and the time constant ensure that the active high reset signal is
applied for at least 24 clockperiods. The microcontroller chip has a built-in clock
(T? T3 ON)
oscillator. So it is enough to connect the crystal to the XTAL1 and XTAL2 pins.
(T,, T4 ON) The connection diagram for this is given in Fig. 12.19.
The circuit consists of four seven-segment displays. For displaying numerals
392 MtcRopRocESSoRSANDMrcRocoNrRoLLERS

7148 BCD to
Seven-segment
dscoder
abcdef g abcdef g
I
I

P1.0
P1.1
P1.2
P1.3
Pl.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXo) P3.1
(rNTo) P3.2
1ffieor P2.7
l;u
(T0)P3.4 P2.6 Switch
(IUP3.s P2.5
(wR) P3.6 P2A
P2.3
P2.2
P2.1
P2.0

initialized to displ
Fig. 12.19 Circuit diagram for timerlstopwatch operation
LSB of porr 2. If r
starting the timer I
in the four displays, we have to connect the pins of two ports to the display code keeps looping in tt
converter. Here, the port pins of P0 and Pl are used. The BCD data of the display
display is increme
is given to the port pins. pon pins by writin
For stopwatch operation, an additional switch is needed to switch on and off as long as the su irr
counting in the stopwatch. A separate push-to-on switch is connected to the LSB
The hardqare.
of port 2. The voltage on this pin can be sensed to control the counting and display
additional I'eatures
ip the seven-segment displays.
stop the stopwatch
The program for stopwatch operation involves a timer register, which is
incremented at regular intervals. The interval can be programmed to be either
12,11 MTCROCON
(1/10)'h of a second or I second. with the interval of (1/10)th of a second and a
TMFFIC LI
4-digit display, the hardware arrangement can be used to count up to 999.9
seconds. with an interval of 1 second, the hardware ,urangement can count up Figure 12.21 shou
ta 9,999 seconds. The timer register can be programmed to generate an interrupt The follorvin_e a
after every interval. rre tiee left rurns ir
The flowchart for the stopwatch example is given in Fig. 12.20.The program .l-i"-ir,'in in Figures i
involves first initializing the timer to the required time interval. The display is also ,: traffic signals._
 805.1 INTERFACE EX{V9.ES 393

Write TMOD, TCON, and timer values into the timer registel
oulput data to initialize ihe dlsplay

Write the new data to

the port registers

Fig. 12.20 Flowchart for stopwatch operation

initialized to display all zeros. Then the status of the switch is sensed from the
LSB of port2. If the switch is pressed, the program moves to the next step, i.e.,
r*atch operation
starting the timer and giving data output to the displays. Otherwise, the program
oi tu'o ports to the disPlaY code keeps looping in the status check on P2.0. After every timer overflow, the data for
x The BCD data of the disPlaY display is incremented and converted into BCD form. New data is given to the
port pins by writing them to the port registers. Data in the display is incremented
:. needed to switch on and off as long as the switch on P2.0 is pressed.
rlch is connected to the LSB
-'.r The hardware, flowchart, and program can be improved further to include
..;ntrol the counting and display additional features suchas resetting the display, using separate switches to start and
stop the stopwatch, and using a press switch to switch on and off the stopwatch.
r:r a timer register, which is
r-., be programmed to be either 12.1 1 MICROCONTROLLER APPLICATION EXAMPLE-
.i ,.f (I/10)'h of a second and a TRAFFIC LIGHT CONTROL
:e used to count up to 999.9
Figure 12.21 shows the basic traffic control signals at a four-road junction.
lr J.re arrangement can count up
The following assumptions are made for designing the traffic light control. There
rrnrmed to generate an interruPt
are free left turns in all the four directions. Traffic is allowed in the four sequencrs
shown in Figures 12.22 (a)-I2.22 (d). Each sequence again has two combination'
r',rn in Fig. 12.20. The Program
of traffic signals-one for red and green and the other for red. green. and rellor''
r::rc interval. The display is also
 8051 INTERFACE EXAV>-!S I}7

in different directions. This program is written using the look-up table concept. So
the same program can be used if LEDs are connected through the 8255 PPI pon
pins.

START: f40V R0. /104H lnitialize R0 for four sequences.

I'4OV DPTR, #LTD-DATA Use the data pointer to point to the LED

di spl ay data.
L00P: M0VX A, @DPTR Get the hex data to be given to port 0.
MOV PO, A Give it to port 0.
lNC DPTR Point to the next data.
I4OVX A, @DPTR Get the data for port 1.
MOV P1,A 0utput it to port 1.
LCALL DELAYl Call the r"equired time de1ay.
INC DPTR Point to the next data.
MOVX A, @DPTR Get the hex data to be given to port 0.
MOV PO,A Give it to port 0.
INC DPTR Poi nt to the next data.
I.4OVX A. @DPTR Get the data for port 1.
MOV P1, A 0utput it to port 1.
LCALL DELAYZ CalI the nequired tjme delay for the yelIow
agram for traffic lights
I i sht.
I are used for the lights in the east
INC DPTR Point to the next data.
outh direction.
DJNZ RO, LOOP Decrement counl; if it is not zero. loop for
: port pins for the sequences shown
the next sequence.
KTAL2, and RST in Fig. 12.23 can
SJI"]P START Loop again for contjnuous sequencin,o.
pins and clock inputs are connected
LED_DATA: DB 0C, 09,
14, 09, ?1, 09. 21.
r Eaffic light conkol 0A,09,0c,09,14.
49, ?1, 0A, 21 Table for the hex values fcr por*,s.
I NR TYG WY VUR port 0 Port 1 END Termi nate program executi on.
L4 P0.3 P0.2 P0.l pg.6 Data Data
This program can be rewritten using the SETB and CLRB instructions, as all
I l0 O OCH 09H the port pins are bit-addressable. However, the program becomes lengthy as each
0 10 0 14H 09H LED has to be individually controlled.
0 00 I zlH 09H
1 2,12 MICROCONTROLLER APPLICATION EXAMPLE-THERMOMETER
0 00 I 2IH OAH

I 00 1 09H OCH Temperature measurement is one of the most common tasks in industries. The
thermistor (temperature-sensitive resistor) is an electrical component capable
1 00 1 09H 14H
of measuring temperature variations, relying on the change in its resistance
I 00 1 09H 2tH u'ith changing temperature. Once calibrated against the thermistor equation, it
1 O OAH ztH is possible to electronically determine the temperature around the thermistor by
measuring the change in voltage across it, as its resistance changes.
ntroller-based traffic light control is Thermistors operate in a limited temperature range (typically -80 "C to 150 "C).
r change the operation of the traffic The significant advantages of the thermistor as a tool for temperature measurement
lity of different delays for the traffic are as follorvs:
398 MrcRopRocESSoRSANDMlcRocoNTRorLERS

(i) A large output signal that results in better precision

(ii) Greater stability. providing accurate performance for longer periods of time
+
(iii) Higher accuracy than thermocouples in mid-range temperatures
i
Most thermistors have a negative temperature coefflcient (I.{TC), meaning that I

the resistance goes up as the temperature goes down. of all passive temperature rr
I ln
measurement sensors, thermistors have the highest sensitivity (resistance change per
degree of temperature L_l
change). Thermistors I

do not have a linear

,--t-\
I
mperature/resistance
te
curve. The nonlinear
curve of
\t','
TtEmistor
resistance
against temperature
is given in Fig. L2.24. -t-
The figure shows the
I
normalized resistance
variation with reference
-
to resistance at25"C.
-20 -10 0 10 20 30 40 50 60 70 80 90 100
$
The Steinhart-Hart Temp€rature (qC)
Fig.12.25
equation is widely linear output voltage in r
used t0 approximate Fi1.12.24 Resistance variation of thermistor with temperature ihe desired range of temp
the temperature, I, of a bridge circuit.
thermistor, as a cubic function of the logarithm of its resistance, Rr It is written Figure 12.26 shorr .
as
measurement using a ther
l=n*
Tt
blnR,+c(lnR.)r .\DC 080.1is used in this
The commonly used prn<
where c, b, and c are physical constants depending on the system. Within the
;rrnr erted into its digital e
small ternperature range of 30 'C-100'C, further linear approximation can be done
:he -\DC chip. The end o
as follows:
:he end of conversion. dr
lnRIUT
=lnR +Io i Read signal to the RD
-,,nr erted into displar d.t
of The softuarc part rrl I
R. = R, *, (?) :le p5:
.i, Clear the di:plai.
Figure 12.25 shows a simple circuit that could be used to allow a microprocessor ii r Give rhe Stan Con
to measure the temperature using a thermistor. A resistor (R,) pulls the thermistor riir (5g.1 for end trf c
up to a reference voltage. This is typically the same as the ADC reference. So v.", ,:r , Read data fiorn t}r.
would be 5 v, if the ADC reference were 5 v. This thermistor used in the circuit r , Conven to the con
,r l
has a nominal resistance value of 10ko at 25 nc, md varies from 330ko at -40"c, Displa)' the rempel
down to 2000 at 150oc, a range of 1650:1. Such a huge dynamic range in the Thrs algonthm use< tt
output resistance can make measurement difficult. :::;ient using intem.tp:i.
It is possible to perform a 'good enough' linearization by adding some very :.r in lnlerrupt input ,rf th
inexpensive circuitry. one way is to incorporate the thermistor into a wheatstone :- read and displar tem;
bridge, as shown in Fig. 12.26.However, this arrangement provides an essentially The crrcurl arrangem€
 EO51 INTERFACE EMMPLES 399

Freclslon
rrrJnce for longer periods of time
id-range temperatures

;,xfficient (NTC), meaning that

t ',r n. Of all passive temperature

I .en sitivity (resistance change per

Vo to ADC inpul

Thermistor

2C 30 40 50 60 70 80 90 100
Fig. 12.25 Simple circuit to measure temperature using thermistor
Tempelature (eC)

linear output voltage in response to small changes in resistance. The linearity in

ianation of thermistor with temperature the desired range of temperature can be achieved by changing the value of R in the
bridge circuit.
i-f rts resistance, R.. lt is written Figure 12.26 shows the complete interfacing arrangement for temperature
measurement using a therrnistor and an ADC with the 8051 microcontroller. The
ADC 0804 is used in this circuit. This is an ADC chip with a single analog input.
The commonly used pins alone are shown in the figure. The analog input can be
ending on the systerr. Within the converted into its digital equivalent by providing a Start Conversion (SC) signal to
hnear approximation can be done the ADC chip. The end of conversion can be sensed on a separate port pin. After
the end of conversion, the data on the DBO-DB7 lines can be read by applying
a Read signal to the RD pin of the ADC chip. The digital data received can be
converted into display data and given to the LCD screen.
The software part of this temperature measurement routine has the following
steps:
(i) Clear the display.
'r**
used to allow a rnicroprocessor
(ii) Give the Start Conversion signal.
\ rcsistor (R,) pulls the thermistor
(iii) Check for end of conversion.
Lme as the ADC reference. So V,",
(iv) Read data from the ADC.
[hrr thermistor used in the circuit
(v) Convert to the corresponding display temperature using the look-up table.
and r,aries from 330kO at -40 "C,
(vi) Display the temperature.
uch a huge dynamic range in the This algorithm uses the simple VO interface. The program can be made more
Ir. efficient using interrupts. The end of conversion (EOC) signal can be connected
nearization by adding some very to an intemrpt input of the processor. At the end of every conversion, the program
' the thermistor into a Wheatstone can read and display temperature, and initiate the conversion process once agarn.
rensement provides an essentially The circuit arrangement shown in Fig. 12.26 can be used for measurern€nl rrf
400 MTcRopRocESSoRSAND MtcRoc0NTRoLLERS

7
P1 0 00
a
P1.1 D1
I
P1.2 D2
10
P1.3 D3
11 LCD
P1.4 D4
8051 12
P1.5 D5 Fig.
P1.6 D6
14 fast mode and 10-b
E R/W RS GND Vo
P1.7 D7
V.. and more address s1

P?.0
6 4 1 3l z I2C bus, with speed'

P2.1
* existing and future
cc
P2.2
12.13.1Details of F

*%^ In the I2C bus. tv

information betu'er
D87 memory connected
Port 3 lines
CLKIN
R JL and can operate eil
flash memory) uit
Analog lN
as an LCD driver
DBO
ADCOSO4
+\
sF-r
r'R he considered as r
?2.3 c^
,Y Table 12.9. The ti
P2.4 Conversion complete bus. A master is tf
P2.5 RD the clock signals t,
addressed by the n

Tat
Fig.12.26 Circuit diagram for temperature measurement using microcontroller
Term Dt
any physical quantity. To measure quantities other than temperature, instead of
the thermistor and bridge alrangement, a circuit should be provided to convert the
)laster fi
tcr
physical quantity into a voltage.
Slave Tl
12,13 RTC INTERFACING USING I'C STANDARD Transmitter Tl

There are a number of peripheral integrated circuits (ICs) in modern electronic Receiver Tl
systems that have to communicate with one another and with the outside wodd.
To simplify the circuit design, Philips developed a simple bidirectional two- It is the respon
wire. serial data (SDA) and serial clock (SCL) bus for inter-IC control. This is I:C bus. Each mas
called I:C bus. The I2C bus supports chips manufactured by any IC fabrication I{ bus. Bus clock
process (NMOS, CMOS, and bipolar) and also the extremely broad range of I2C- br a slave that is r

compatible chips from Philips and other suppliers. It has become the worldwide ihe clock line in tl
industry standard proprietary control bus. Figure 12.27 shows the interconnection rrming diagram oi
of various devices using the I2C bus. rrf data from and t
The basic I2C bus, with a data transferrate ofup to 100 Kbits/s andT-bit addressing, 12,13.1.1 Sfarf an
was introduced twenty years ago. However, as data transfer rates and application \nr data transt-er
functionality rapidly increased, the I2C bus specification was enhanced to include :ne data transler
 8051 TNTERFACE EXAUP.ES 393

Write TMOD, TCoN, and limer values into the timer register
Output data to initialize the display

Write the new data to

the port registers

Fi1.12.20 Flowchart for stopwatch operation

initialized to display all zeros. Then the status of the switch is sensed from the
LSB of port2.If the switch is pressed, the program moves to the next step, i.e.,
tscwatch operation
starting the timer and giving data output to the displays. Otherwise, the program
L\i two ports to the display code keeps looping in the status check on P2.0. After every timer overflow, the data for
r.l The BCD data of the display display is incremented and convefted into BCD form. New data is given to the
port pins by writing them to the port registers. Data in the display is incremented
h i. needed to switch on and off as long as the switch on P2.0 is pressed.
r i,,i itch is connected to the LSB The hardware, flowchart, and program can be improved further to include
r --r-rntrol the counting and display additional features such as resetting the display, using separate switches to start and
stop the stopwatch, and using a press switch to switch on and off the stopwatch.
i'.es a timer register, which is
:.rn be programmed to be either 12.1 1 MICROCONTROLLER APPLICATION EXAMPLE-
r rl oi (1/10)'h of a second and a TRAFFIC LIGHT CONTROL
r bc used to count uP to 999"9
Figure 12.21 shows the basic traffic control signals at a fbur-road junction.
l'x are arrangement can count up
The following assumptions are made for designing the traffic light control. There
r^.rmmed to generate an interuPt
are free left tums in all the four directions. Traffic is allowed in the four sequence q
shown in Figures L2.22 (a)-L2.22 (d). Each sequence again has two combination.
Err cn in Fig. 12.20. The program
of traffic signals----oneforredandgreenandtheotherforred. green. and relltlu,
I :rme interval. The display is also
394 MtcRoPRocESSoRSANDMIcRoc0NTRoLLERS

Figures 12.22 (aY12.22 (d) shows the traffic signals that are on' For example, in
Fi;. D.Z2 (a), the geen light (WG) in the west direction is on and the red light is
on in all the other three directions. All other lights are off and they are not
shown in
Fie. r?.?2 (a). \.1

()
- ,/
<-----
I I

ONR I

I CNv
I CHe I

w WRWYWG

occ COO
EG EY ER
E

Fig 1

SGC
SYC [- it
sRo I

:
I
I --\'
I

I
,1-
i
I
r_
!\&
Fig.12.21 Traffic light controls at four road junction

Trafflc light control using a microcontroller can be done easily with parallel ports'
The port pins can be connected to each light, LED, or group of LEDs through SR

a proper driver circuit. The data in the parallel ports can be changed using the
p*gru-, for turning on and off the lights. Figure 12.23 shows the connection
aiugru* for all the lights, which are assumed to be LEDs in this example. The port
pins of port 0 and port 1 are used. The least significant three bits of port 0 are used
Fig '
ior the west direction. The port 0 pins 3, 4, and 5 are used for the north direction'

Fig.12.22 (a) Traffic light control sequence 1

 8051 INTERFACE E)(iJ,rp!rc 395

snals that are on. For example, in

drrection is on and the red light is
-i are off and they are not shown in

-.iL)
GEYER

n four road junction

t tc done easily with parallel ports.

LED, or group of LEDs through
el ports can be changed using the
isure 12.23 shows the connection
, he LEDs in this example. The port

nlticarrt three bits of port 0 are used

I -i are used for the north direction. Fig. 12.22 (c) Traffic light control sequence 3

L---l :-- I

r-] wQ
WY
r-l
I -a
r-)E l/' r) E

ER Ipn
t^
s0lU
I

.l
Fig. 12.22 (d) Traffic light control sequence 4

r::,sequence 1
396 MTcRopRocESSoRSANDMtcRocoNTRoLLERS

in different direcr
the same prograr
pins.

START: l40V R

I1|]V DPTR.

t00P: MOVX i, .
r'10v P0 , A

] IIC DPTR
i.'c\/Y A,
@DP--
,,,i1/ Dt I

-ALL DELAY.
..,C DPTR
'.'_,, A, @DPlr

.,
. , DPTR

. .\. (vur -
" Dl A

' nal r 1
Fig.12.23 Hardware connection diagram for traffic lights
Similarly, the least significant three bits of port 1 are used for the lights in the east
direction and pins 3,4, and 5 are used for the south direction.
- .'- i0, LC--
Table 12.8 shows the data to be given to the port pins for the sequences shown
in Fig. l2.22.The other pins such as XTALI, XTALZ, and RST in Fig. 12.23 can
be connected as shown in Fig. 12.19. The reset pins and clock inputs are connected ,..,: START
:_- - -_- ,-.a.!!!. nD
to the corresponding circuit. l. 10

Table 12.8 Data for port pins for traffic light control : -c

SG SY SR EG EY ER NG NY NR WG
:,2-,'-:. _
WY wR 0
Port Port 1
Sequence
p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.5 p0.4 p0.3 p0.2 p0.1 p6.g Data Data
This program
00100100110 O OCH O9H
:.port pins are t
Sequence 1
00100101010 0 14H 09H I ED has to be inc
00100110000 I zTH O9H
Sequence 2 12,12 MtCRoCot
00101010000 I zIH OAH
00110000100 1 O9H OCH ;rrnpcrature mea
Sequence 3
:..3:mi\tor (temF
01010000100 1 09H t4H ': n:eesuring ten
I 0000100 00 1 09H 21H :.:: ;hanging ter
Sequence 4
I 0000100 0t O OAH 21H r 3-,ii1frlg to ele.
-siirnng the cha
One of the advantages of this type of microcontroller-based traffic light control is I::ermrstors t'rp
the ease of programming and the flexibility to change the operation of the traffic --:,: .:5tnCant ad'
lights. Another advantage is the programmability of different delays for the traffic --; f. ilrl^!)\\!l
 8051 INTERFACE EXAV}.:S 3!}7

in different directions. This program is written using the look-up table concept. Scr
the same program can be used if LEDs are connected through the 8255 PPI port
pins.

START: M0V R0, ll04H Ini ti al i ze R0 for four sequences.

MOV DPTR, /ILID-DATA Use the data pointer to point to lhe LED

di spl ay data.
L00P: MOVX A, @DPTR Get the hex data to be given t0 port 0.
MOV PO, A Give jt to port 0.
INC DPTR Point to the next data.
I'4OVX A, @DPTR Get the data for port 1.
1.10v P1 , A 0utput it to port 1.
LCALL DELAYl Call the requined time delay.
INC DPTR Point to the next data.
MOVX A, @DPTR Get the hex data to be given t0 por"t 0.
Gi ve t to port 0.
.i
t40v P0 , A
lNC DPTR Point to the next data.
MOVX A, @DPTR Get the data fon port 1.
MOV P1, A 0utput it to port 1.
agram for traffic lights
LCALL DELAYZ Call the required time delay for the yellow
I i ght.
I are used for the lights in the east
lNC DPTR Point to the next data.
outh direction.
DJNZ RO, LOOP Decrement count: if it is not zer0, loop for
pon pins for the sequences shown
(TAL2, and RST in Fig. 12.23 can the next sequence.
SJMP START Loop agai n f or ccnt i"uoi.rs secuenci ng .

pins and clock inputs are connected

LED_DATA: DB 0C, 09,
14, 09 , 21, 09 , 21..
r traffic light control 0A,09,0c,09,14,
09, ?1, aA,21 Table for the hex values fcr ports.
I I{R WG WY WR 0
Port Port t END Terminate prognam execution.
L/t P0.3 P0.2 P0.l P0.0 Data Data
This program can be rewritten using the SETB and CLRB instructions, as all
110 0 OCH O9H the port pins are bit-addressable. However, the program becomes lengthy as each
010 0 14H 09H LED has to be individually controlled.
000 I ztH 09H
1 2.1 2 MICROCONTROLLER APPLICATION EXAMPLE-THERMOMETER
000 1 zLH OAH
100 1 O9H OCH Temperature measurement is one of the most common tasks in industries.. The
thermistor (temperature-sensitive resistor) is an electrical component capable
100 1 09H 14H of measuring temperature variations, relying on the change in its resistance
100 I 09H zrH with changing temperature. Once calibrated against the thermistor equation, it
101 0 OAH 2IH is possible to electronically determine the temperature around the thermistor by
measuring the change in voltage across it, as its resistance changes.
rtroller-based traffic light control is Thermistors operate in a limited temperature range (typically -80 oC to 150 "C).
r change the operation of the trafflc The significant advantages of the thermistor as a tool for temperature measurement
ity of different delays for the traffic are as follows:
400 MTcRopRocESSoRSAND MtcRoc0NTR0LLERS

7
P1 0 DO
o
P1.1 D1
I
Pl.2 D2
10
P1.3 D3
11 LCD
Pl.4 M
8051 12
P1.5 D5 Fig.
IJ
D6
fast mode and lGt
P'1.6
14

E RiW RS GND Vo
P1.7 D7
V.. and more address s;

P2.0
6 5 4 1 3l z IrC bus, with speed
P2.1
* existing and future
cc
P2.2
12.13.1Details of F

*Vr* In the I2C bus. tv

information betu'et
D87 memory connected
Port 3 lines
CLKIN
R JL and can operate eit
flash memory) uit
DBO
Analog lN

N
J as an LCD driver
ADCOSO4
+R, rR be considered as r
?2.3 e^
uY Table 12.9. The u
P2.4 Conversion complete bus. A master is tt
P2.5 RD the clock signals t,
addressed by the n

Ta!
Fig. 12.26 Circuit diagram for temperature measurement using microcontroller
Term Ix
any physical quantity. To measure quantities other than temperature, instead of
the thermistor and bridge affangement, a circuit should be provided to convert the
Master Tt
tel
physical quantity into a voltage.
Slave TI
12,13 RTC INTERFACING USING I'C STANDARD Transmitter Tl
There are a number of peripheral integrated circuits (ICs) in modern electronic Receiver Tl
systems that have to communicate with one another and with the outside wofld'
To simplify the circuit design, Philips developed a simple bidirectional two- It is the respon
wire. serial data (SDA) and serial clock (SCL) bus for inter-IC control. This is I:C bus. Each mas
called I:C bus. The I2C bus supports chips manufactured by any IC fabrication I{ bus. Bus clock
'nr a slave that is r
process (NMOS, CMOS, and bipolar) and also the extremely broad range of I2C-
compatible chips from Philips and other suppliers. It has become the worldwide rhe clock line in tl
industry standard proprietary control bus. Figure 12.27 shows the interconnection ruming diagram of
of various devices using the I2C bus. urf data from and t

The basic I2C bus, with a data transfer rate of up to 100 Kbits/s and 7-bit addressing, 12.13.1.1 Starf an,
was introduced twenty years ago. However, as data transfer rates and application \ny data transt'er
functionality rapidly increased, the I2C bus specification was enhanced to include :ne data transtcr
 8051 INTERFACE EXAMPLES 401

Fig.'12.27 lnterconnection of various devices using l'?C bus

fast mode and i0-bit addressing, thereby satisfying the demand for higher speeds
and more address space. More recently, the high speed mode has been added in the
I2C bus, with speeds of up to 3.4 Mbits/s, which ensures that the I:C bus can support
existing and future high speed serial transfer rates for different applications.

12.13.1Details of l2C Bus

In the I2C bus, two wires-serial data (SDA) and serial clock (SCL)--{arry
information between devices such as the microcontroller, the LCD driver, and the
memory connected to the I2C bus. Each device is recognized by a unique address
and can operate either as a transmitter (such as a microcontrotler, EEPROM' and
flash memory) with the capability to send and receive data or as a receiver (such
as an LCD driver). In addition to transmitters and receivers, devices can also
be considered as masters or slaves when performing data transfers, as shown in
Table I2.9. The table indicates the description of various terms used in the I2C
bus. A master is the device that initiates a data transfer on the bus and generates
the clock signals to permit that data transfer. During this time, any device that is
addressed by the master is considered a slave.

Table 12.9 Description of terms associated with the l'zC bus

rasurement using microcontroller
Term Desoiption
other than temperature, instead of
Master The device that initiates a data transfer, generates clock signals, and
rt should be provided to convert the
terminates a data transfer

Slave The device addressed by a master

ARD Transmitter The device that sends data to the bus

:ircuits (ICs) in modern electronic Receiver The device that receives data from the bus
nother and with the outside wodd.
loped a simple bidirectional two- It is the responsibility of the master device to generate the clock signals on the
-r bus for inter-IC control. This is I:C bus. Each master generates its own clock signals when transferring data on the
anufactured by any IC fabrication I:C bus. Bus clock signals from a master can only be altered when they are stretched
r the extremely broad range of I2C- by a slave that is operating slowly and holding down the clock line (i.e., keeping
hers. It has become the woddwide the clock line in the low state) or by another master when arbitration occurs. The
timing diagram of the various conditions in the I2C bus, and the reading and writing
're 12.27 shows the interconnection
of data frorn and to the bus are explained in Sections I2.I3.l.l-12.13.1.6.
p to 100 Kbits/s and 7-bit addressing, 12.13.1.1 Sfarf and Sfop Condifions
r data transfer rates and application
.\ny data transfer in the I2C bus must be initiated with a start (S) condition. .\fter
--ification was enhanced to include rhe data transfer is completed, it must be terminated by a stop (P) condition.
 402 MrcRopRocEssoRS AND MtcRocoNTRoLLERS

Figure 12.28 shows the timing diagram for the start and stop condirions. A high-
to-low transition on rhe SDA line when SCL is high defines a start condition. A
low-to-high rransirion on the SDA line when scl- is high defines a stop condition.
The start and stop conditions are always generated by the master. Th6 bus is
considered to be busy after the start condition is generated. The bus is considered
to be free again, a certain time after the stop condition is generated.

START or
repeated STMT
condilbn
Fi1.12.28 Start (S) and stop (p) conditions in t2C bus
The bus stays busy if a 'repeated start' (Sr) is generated instead of a stop
condition. In this respect, the start (S) and repeated sta( (Sr) conditions are
12.13.1.4 Ackno
functionally identical. Detection of start and stop conditions by the devices
connected to the I2c bus is simple if they incorporate the necessary interfacing Data transf er u r
hardware. However, microcontrollers with no such interface have to sample the related clock pu
SDA line at least twice per clock period to sense the transition. -rne to the high
Jou n the SDA lr
12.13.1.2 Data Validig Condition
Frg. 12.31. The
The data bit on the SDA line (high or low) must be stable during the high period :eieiver that hai
of the clock. The state of the data line can change only when the clock signal on
the SCL line is low, as shown inFig. 12.29.

h€
iSDA) ril
soA
Ca
iSDA) 16

q
't
Data line stabie;
dah vatid

Fi9.12.29 Data bit transfer in the lzC bus

Fig. 1
12.13.1.3 Data Transfer in Byte Format
::-: br.te ha-r bet
The number of bytes that can be transmitted per data transfer in the I2c bus is
.r'n the data tra
unrestricted. Each byte has to be followed by an Acknowledge (A) signal from
L:i:3r that ii actr
the slave. Data is transferred with the most significant bit (MSB) first, as shown
in .: :.lra ranster tc
Fig. 12.30. If a slave cannot receive or transmit another complete byte of data
.:. te last brre *
since it is performing some other function (e.g., servicing an internal or extemal
intenupt), it can hold the clock line SCI- in the low state to force the master into a --: SD.\ line ro a
wait state. Data transfer then continues when the slave is ready for another byte of r2.13.1.5 Writing
data, wirh the slave releasing SCL to the high state. f ;-:e il.-:l <hc
,:i: l,'a :1.:ri f
 8051 INTERFACE ax.Arrt)-ES 403

lan and stop conditions. A high-

hrgh defines a start condition. A
l- is high defines a stop condition.
:rated by the master. The bus is
; generated. The bus is considered
rdition is generated.
Clock line held lorv while
interupts are serviced .
SDA
1nr-

scL
\J'\,-ti$i
ACK l---i
STOP or
repeated START
condition

:cnditions in l2C bus

Fig. 12.30 Data transfer in byte format in the l2C bus
ir r is generated instead of a stoP
cpeated start (Sr) conditions are 12.13.1.4 Acknowtedge (A) and Not'acknowledge fi)
I stop conditions by the devices
Data transfer with acknowledge is mandatory in the I2C bus' The acknowledge-
Drporate the necessary interfacing related clock pulse is generated by the master. The transmifter releases the SDA
such interface have to samPle the line to the high state during the acknowledge clock pulse. The receiver must pull
r the transition. down the SDA line to the low state during the acknowledge clock pulse, as shou'n
in
Fig. 12.31. The set-up and hold times must also be taken into account' Usually. a

receiver that has been addressed must generate an Acknowledge (A) signal after
st be stable during the high period
nre only when the clock signal on

{sDA)

----\_ (SDA)

f
Clock pulse for
ackno\,rledgemsnt

r ,n the lZC bus the l'C nus

Fig. 12.31 Acknowledge (A) and Nolacknowledge 141 in

each byte has been received. The master can then generate either a stop condition
to
prcr data transfer in the I2C bus is abort the data transfer or a repeated start condition to start a new data transf'er' lf a

(A) signal from master that is acting as a receiver is involved in a data transfer, it must signal the end
an Acknowledge
of data transfer to the slave transmitter by generating a Not-acknowledge signal
(A)
rrticant bit (MSB) first, as shown in
mit another complete byte of data on the last byte that was clocked out of the slave. The slave transmitter must release
r.. servicing an internal or external the SDA line to allow the master to generate a stop or repeated start condition'
' low state to force the master into a 12.19.1.5 Writing Data to Slave Receiver by Master Transrnifrer
hc slave is ready for anotherbyte of
Figure 12.32 shows the format of the I2C frame when a master transmitter writes
\tate. of data tiorn
data to a slave receiver. The shaded portion indicates the transfer
404 MrcRopRocESsoRSANDMrcRocoNTRoLLERS

the master to the slave and the lf the master wanr

unshaded portion indicates register in the slave suc
the transfer of data from the Data transfened (in J as follows:
0 (Write)
slave to the master, which is bytes + Acknowledge)
(i) The master send
A = Acknowledge (SDA low)
the Acknowledgement signal ffi From master to slave
A = Nolacknowledge (SDA high) (ii) The master sen(
from the slave. The read/write I From slave to master S = START condilioo (which is 0) app
P = STOP mndition
(R/W) bit is made 0 when signal.
the master writes data to the
Fig. 12.32 Master transmitter sending data to slave (iii) The master send
slave, receiver in l2C bus slave from wher
The following sequence is slave sends the .
used while a master transmitter writes data to a slave receiver: (iv) The master send
(i) The master sends the start (S) condition. (v) The master agar
(ii) The master sends the 7-bit slave address, with the read/write (R/W) bit bit, which is set
(which is 0) appended as the LSB. For example, if the master wanrs to write (vi) The slave sends,
in an EEPROM memory (slave) with the 7-bit address 40H (i.e., 1000000 Acknowledge sir
in binary), the read/write R/ W- bit is appended as the LSB to this 7-bit from the slave tl
address to get the resultant byte 80H (i.e., 10000000 in binary) and ir is sent (vii) The master send
to the slave.
(iii) The slave sends the Acknowledge (A) signal. When data is being
(iv) The master sends data bytes one by one to the slave and the slave sends as an analog-to-digital r
Acknowledge signal (A) for every byte transferred. For the last byte sent by sequence of operations
lhe master. the slave replies with a Not-acknowledge signal (A). (i) The master send
(v) The master sends the stop condition to end the data transfer.
(ii) The master sen(
' (which is l) app
Note: In the case of slaves such as EEPROM and RTC, which have sub-adgresses signal.
orpointers (i.e., address of internalts$stersE$ffilocations within the slave), (iii) The slave sends
after sending the slave address, the first data byte that is sent by the master is the an Acknowledge
sub-address of a specific location or intemal register within the slave from where read frorn the sla
the successive data bytes from the master will be written in the sl.ave. The sub- the master sends
address is used to initialize the internal address pointer in the slave to point to a
Not-acknowledg
particular location or register. signal (A).
12.13.1.6 Reading Data from Slave Transmitter by Master Receiver (iv) The master sendr
while data is being read from a slave transmitter by a master receiver on the I2C stop (P) conditio
bus. there are two different cases depending upon whether the addressed slave end the data tran
has sub-addresses or not. The sub-address is usually needed to access data from This is shown in Fig. l.
a serial EEPROM, RTC, etc. Figure 12.33 shows the transfer of data between a
master receiver and a slave transmitter that has sub-addresses. 12.13.2 8051 Subroutin
We can implement the
subroutines (written in a
various functions involr
u (wnte) 1 (Read) Data transfened (in
uy,Jr'-.,i.i-rig.l
the 805 I are assumed r,

of the I2C bus.

fl I From master to slave ! From slave to master SUB denotes sub-address
: rc,rts Lrsed fo. I:,_ :

Fig' 12.33 Master receiver reading data from slave transmitter having sub-addresses
:lA EOU P0.6 : I.=
:'L
--! Enlr Dn a
LUU tU./ . -^-'=
|
 8051 INTERFACE EXAIq.ES .05
c- ',,

If
W
the master wants to read data bytes from a specific location or internal
register in the slave successively, the sequence of operations done by the master is
L Data translened (in J as follows:
o rw'ritet
bytes + Acknowledge) (i) The master sends the start (S) condition.
bslrw A=Acknowledge($DAlow)
(ii) The master sends the 7-bit slave address, with the read/write (R/W-) bit
A = Not-acknowlodge (SDA high)
) irtsiot S = $TART mndition (which is 0) appended as the LSB. The slave sends the Acknowledge (A)
P = STOP condition
signal.
fuster transmitter sending data to slave
(iii) The master sends the sub-address of a particular location or register in the
receiver in l2C bus slave from where it wants to read data. This is called dummy write. The
slave sends the Acknowledge (A) signal.
a slave receiver: (iv) The master sends a repeated start condition (Sr).
(v) The master again sends the 7-bit slave address, with the read/write (R/W-)
ess. with the read,/write (R/W-) bit bit, which is set to 1 now, to indicate read operation.
xample, if the master wants to write (vi) The slave sends data bytes one by one to the master and the master sends an
r 7-bit address 40H (i.e., 1000000 Acknowledge signal (A) after each byte read. [f it is the last byte to be read
appended as the LSB to this 7-bit from the slave then the master sends a Not-acknowledge signal (A).
.. l0000000inbinary) anditis sent (vii) The master sends a stop (P) condition to end the data transfer,

When data is being read from a slave transmitter with no sub-addresses (such
ignal.
as an analog-to-digital converter) by a master receiver in the I2C bus, the following
l€ to the slave and the slave sends
sequence of operations has to be performed:
transferred. For the last byte sent by
acknowledge signal (A).
(i) The master sends the start (S) condition.
cnd the data transfer.
(ii) The master sends the 7-bit slave address, with the read/write (R/W) bit
(which is 1) appended as the LSB. The slave sends the Acknowledge (A)
rnd RTC, which have sub-adf,resses signal.
Gfrffilocations within the slave), (iii) The slave sends data bytes one by one to the master and the master sends
r! te that is sent by the master is the an Acknowledge signal (A) after each byte read. If it is the last byte to be
egister within the slave from where read from the slave,
ll be written in the slave. The sub- the master sends a
ss pointer in the slave to point to a Not-acknowledge
Data transfoned (in
signal (A).
t by Master Receiver (iv) The master sends a ffi Frommaslertoslave f] Fromslavelomaster
stop (P) condition to
ner by a master receiver on the I2C
end the data transfer" Fig.12.34 Master receiver reading data from slave
upon whether the addressed slave
transmifter having no sub-addresses
u*ually needed to access data from This is shown inFig. L2.34.
pu s the transfer of data between a
12.13.2 8051 Subroutines used to lmplement l2C Bus
s sub-addresses.
We can implement the I2C bus by using any two pins of the 8051. The 8051

W r rl.rat
L Datatransfened(in
byt6s + acknowledge)
]
subroutines (written in assembly language programs), which are used to implement
various functions involved in the I2C bus are given here. Port pins P0.6 and P0.7 of
the 8051 are assumed to be used as the SDA line and the SCL line, respectivelr'.
of the I2C bus.
t1@s suLaddrgss
; Ports used for I2C bus
pe ransmitter having sub-addresses
SDA EOU P0.6 ; The symbol SDA corresponds to pin P0.6.
SCL EOU P0.7 ; The symbol SCL conresponds to pin P0.7.
406 MTcRopRocESSoRSAND MTcRocoNTRoLLERS

; Ini ti al i zi ng the i:C bus RET

I2C-]N]T: ; Sending tn: ',
SETB SDA ; Set SDA to 1. I2C_NACK:
STTB SCL ; Set SCL to 1. SETB SDA
RET ; Return SETB SCL
; Cneati ng the start condiiion CLR SCL
12C_-slarl: RIT
SEiB SCL ; Set SCL to 1. ; Rece i vi ng de::
CLR SDA ; Set SDA to 0. J 2C-RECE] VE:
CLR SCL ; Set SCL to 0. '.10v R6. #08
RET ; Return REP2:
; CreatinE lhe nestart condition ..R
SCL
I 2C_REsta rt ):rB SCL
CLR SCL Set SCL to 0.. .].J C, SDA
SETB SDA Set SDA to 1. :^A
SETB SCL Set SCL to 1.
CLR SDA Set SDA to 0. .,2 R6. REP2
RTT Ret u rn
; Creati ng the stop condition SCL
I ZC_s top : SDA
CLR SCL Set SCL to 0.
CLR SDA Set SDA to 0.
SETB SCL Set SCL to 1.
12.13.3 DSl307-
S[18. SDA Set SDA to 1. The DS1307 sen
RtT Retu rn l{,s er. binary co<
; Sending data n registen A of the 8051 (master) to a slave -,cked general-pr
]2C SEND: .:. i:C bidirectior
f40\/ R6, #08 Load the number of bits in A (i.e.,8) in R6. ::r. date. month.
REP: i.- \'ear 2100. I
CLR SCL Set SCL to 0. ..:th feu,er than -1

RLC A Rotate A left through the canr"y to transfer one bjt : :ner the 2.1-hou:
in A to the carry, starting from lhe l4SB. :-r pin diagram
vn\/ qrl^ f Move the bit in the carr^y flag to SDA. -<-..e circuit that
5:r3 SCL Set SCL to 1. ) ..::.heS to the I

DiriZ ri, REP Decrement R6 and go to REP, if R6 is not 0 (to :':.lected to it.
transmit the next bit). , - .e the DS1-1(
CLR SC. Set SCL to 0. ..i,- has a progra
SITB SDA Set SDA to 1. - . :..:rmes less th:
REI Ret u rn -: .'.cillator run:
; Sending the Ac know.l edge si gnal . . - .,r'ole in plasr
I2C-ACK: -' .re rSOt forrr
C LR SI]A Set SDA to 0. I-.c iunctional
SETB SCL Set SCL to 1. -. -.:.:.:ins an oi,
CLR SCL Set SCL to 0. -. :a, ,-: h,anen -b
SETB SDA Set SDA to 1. - -.:: : ::fer. nruitrl
, : -:. anJ ;crnir(
 8051 TNTERFACE =-XdtPj: {07

RET ; Return,
; Sending the Not-acknowl edge si gnal
1 2C_NACK:
SETB SDA Set SDA to 1.
SETB SCL Set SCL to 1.
CLR SCL Set SCL to 0.
RET Ret u rn
; Rece i vi ng data from a slave to negister A of the 8051 (master)
12C_RECEIVE:
[10v R6, /108 Load the number of bits in A (i'e" B) in R6.

REP2:
CLR SCL Set SCL to 0.
SETB SCL Set SCL to 1.
MOV C. SDA Move the bit SDA to-the ea.rry flag'
RLC A Rotate A I eft thr"ough {h. .u.ty, to rece.i ve one bi t
from the carry, star"ting from the l4SB.
DJNZ R6, RtP2 Decrement R6 and qo to REP2, if R6 is not 0 (to
receive the next bit).
CLR SCL Set SCL to 0.
SETB SDA Set SDA to 1.
RET Ret u nn

12.13.3 0S1307-SeriallzC Real.time Clock lC

The DS1307 serial real-time clock (RTC) is a product of MAXIM and is a low
power, binary coded decimal (BCD) clocl:/calendar IC. It has 56 bytes of battery-
-lster) to a slave backed general-purpose SRAM. Address and data are transferred serially through
an I2C bidirectional bus. The clock/calendar provides seconds, minutes, hours,
(i.e., B) in day, date, month, and year information with leap yeaf compensation valid up to
" A R6.
the year 2100. The end of the month date is automatically adjusted for months
with fewer than 31 days, including corections for leap year. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator. Figure 12.35 shows
'a cdrry to transfer one bit
the pin diagram of DS1307 (plastic DIP). The DS1307 has a built-in power-
i''q from the MSB.
... flag to sense circuit that detects power failures and automatically
SDA.
switches to the backup supply provided by the battery x't vr.
ii:, if connected to it. The timekeeping operation continues
R6 is not 0 (to x2 SQWOUT
while the DS1307 opeiates from the backup supply. It scL
also has a programmable square-wave output signal and GND SDA

consumes less than 500 nA in battery-backup mode, with

Fig. 12.35 Pin diagram
the oscillator running. The DS1307 has eight pins and is
of DS1307
available in plastic dual in-line package (DIP) and small
outline (SO) form.
The functional block diagram is shown in Fig. 12.36.
It contains an oscillator circuit, power control circuit, I2C interface circuit. ::
-
bytes of battery-backed SRAM, clock, calendar and control registers. h''i:i ::
user buffer, multiplexer/buffer to control a MOSFET for generating a sQuari
'.i;" i
output. and control logic.
 8051 INTERFACE 107
=T.ryD-:S

RET ; Return,
; Sending the Not-acknowl edge si gnal
I ZC_NAC K :
SETB SDA Set SDA to 1.
SETB SCL Set SCL to 1.
CLR SCL Set SCL to 0.
RET Ret u rn
; Receiving data from a slave to register" A of the 8051 (master)
I2C_RECElVE:
r40\/ R6, ,108 Load the number of bits in A (i'e', B) in R6.

REP2:
CLR SCL Set SCL to 0.
SETB SCL Set SCL to 1.
I4OV C, SDA Move the bit SDA to-the eariY flag.
RLC A Rotate A Ieft thnough {h. ca.ry' to receive one bit
from the carry, star"ting from the MSB.
DJNZ R6, RTP2 Decrement R6 and go to REPZ, if R5 is not 0 (to
receive the next bit).
CLR SCL Set SCL to 0.
SETB SDA Set SDA to 1.
DFT Ret u nn

12.13.3 0S1307-Seriall2C Real-time Clock lC

The DS1307 serial real-time clock (RTC) is a product of MAXIM and is a low
power, binary coded decimal (BCD) clock/calendar IC. It has 56 bytes of battery-
backed general-purpose SRAM. Address and data are transferred serially through
-aster) to a slave
anI2C bidirectional bus. The clockJcalendar provides seconds, minutes, hours,
, (i.e., 8) in R6. day, date, month, and year information with leap year compensation valid up to
A
the year 2100. The end of the month date is automatically adjusted for months
with fewer than 31 days, including cofiections for leap year'. The clock operates in
"€ ;arry to transfen one bit either the 24-hour or l2-hour format with AM/PM indicator. Figure 12.35 shows
rhe pin diagram of DS1307 (plastic DIP). The DS1307 has a built-in power-
:'"; from the MSB.
... sense circuit that detects power failures and automatically
f I ag to SDA.
switches to the backup supply provided by the battery x1 v",
connected to it. The timekeeping operation continues x2 SQWOUT
while the DS1307 operates from the backup supply. It }UL

also has a programmable square-wave output signal and GND SDA

consumes less than 500 nA in battery-backup mode, with

Fig. 12.35 Pin diagram
the oscillator running. The DS1307 has eight pins and is
of DS1 307
available in plastic dual in-line package (DIP) and small
outline (SO) form.
The functional block diagram is shown in Fig. 12.36.
It contains an oscillator circuit, power control circuit, I2C interface circutl. {^
bytes of battery-backed SRAM, clock, calendar and control registers.
-bric' - -
user butfer, multiplexer/buffer to control a MOSFET for generating a SQUi.:ie '. : . :
output. and control logic.
408 MTcRopRocESSoRSANDMtcRocoNTRoLLERS

pin is open-drain and

1 Hzl4.096 kHz/8.192 kHz/32.766 kHz
with either V". or V..
V... If nor
voltage on
V""-This is the p
normal limits (a minrr
of 5V), the device is
a backuprsupply is cr
writing are inhibited. l
the lower input voltag

12.13.3.2 Detaited Da
The DS1307 operates
implementing a start c
is 1i01000 (in binan
Subsequent registers
executed. When V..
access in progress anr
device will not be rec
being written to the de'
Fig. 12.36 Functionat btock diagram of DS1307 V"o, the device switcl
12.13.3.1 Pin Details of D51307 the device switches frr
and recognizes inputs ,

The pin details of DS1307 are as follows:

Xl and X2-These two pins provide connections for the standard 32.i6gkHz Oscillator Circuit
qtnrtz crystal. The internal oscillaror circuitry of the DS1307 is designed for The DS1307 uses an e
operation with a crystal having a specified load capacitance (c,_) of 12.5 pF. X1 is require any external re
the input to the internal oscillator and can optionally be connected to an external load capacitance (C.)
32.768kH2 oscillator. The output of the internal oscillator (X2) is floated if an of the oscillator circuir
external oscillator is connected to Xl. that the start-up time is
vu^r-This pin is the backup supply input for a standard 3 v tithium cell or dependent upon the act
any other energy source. The battery voltage must be held between the minimum ihe capacitive load of,
(2 v) and maximum limits (3.5 v) for proper operation (typical value is 3 v). If a .'nstal was trimmed. .
backup supply is not required, v"o, must be grounded. The nominal power-fail ,'aused by temperature
trip point (v.r) voltage at which access to the RTC and user RAM is denied, is ;ircuit may result in thi
set by the internal circuitry as r.25 times vuor. A lithium battery with 4grnAh or
RTC and RAM Addr,
Sreater will provide backup supply for the DS1307 for more than 10 years in the
The time and calendar
absence of power at+25"C.
SDA-This pin is the serial data input/output for the I2C serial interface. The :rtes in the DS1307. I
sDA pin is open-drain and requires an externar pull-up resistor. The pull-up :.nd RAM registers in r
voltage can be up to 5.5 V, regardless of the voltage on V"". .cations 00H-07H. Tl
scl--This pin is the serial clock input for the I2c interface and is used to -rFH. During a multi-b
synchronize data movement on the serial interface. The pull-up voltage can be up :: the end of the RAM
to 5.5V, regardless of the voltage on V"". :eginning of the clocl
sQwour-This xe rype of information
is a square wave/output driver pin. when enabled (i.e., when
the SQWE bit in the control register is set to 1), the sew/oUT pin outpurs one of rinimum and maximur
four square wave frequencies (1 Hz, 4kHz,8kHz, and 32kHz). The SewoUT
 8051 INTERFACE EXAMPLES 409

pin is open-drain and requires an external pull-up resistor. SQWOUT operates

with either V"" or Vror. The pull-up voltage can be up to 5.5 V, regardless of the
voltage on V"". If not used, this pin can be left floating.
V..-This is the primary power supply pin. When a voltage is applied within
normal limits (a minimum of 4.5V to a maximum of 5.5V, with a typical value
of 5V), the device is fully accessible and data can be written and read. When
a backup supply is connected to the device and V.. is below V.., reading and'
writing are inhibited. However, the timekeeping function continues unaffected by
the lower input voltage.
12.13.3.2 Detailed Description of D51307
The DS1307 operates as a slave device on the I2C bus. Access is obtained by
implementing a start condition and providing a device identification code, which
is 1101000 (in binary form) for the DS1307, followed by a register address.
Subsequent registers can be accessed sequentially until a stop condition is
executed. When V"" falls below 1.25 times of Vro' the device terminates the
access in progress and resets the address counter in the DS1307. Inputs to the
device will not be recognized at this time, so as to prevent erroneous data from
being written to the device from an out-of-tolerance system. When V"" falls below
gram of DS1307 Vro' the device switches to a low current battery-backup mode. Upon power-up,
the device switches from battery to V." when V"" is greater than (Vro, + 0.2V)
and recognizes inputs when V.. is greater than 1.25 times Vuor.

ctions for the standard 32.768kH2

Oscillator Circuit
y' of the DS1307 is designed for The DS1307 uses an external 32.768kH2 crystal. The oscillator circuit does not
capacitance (C,_) of 12.5 PF' X1 is
require any external resistors or capacitors to operate. The crystal should have a
onally be connected to an external load capacitance (C.) of 12.5pF. Figure 12.36 shows the functional schematic
nal oscillator (X2) is floated if an of the oscillator circuit. Using a crystal with the specified characteristics ensures
that the start-up time is usually less than one second. The accuracy of the clock is
for a standard 3V lithium cell or dependent upon the accuracy of the crystal and the accuracy of the match between
rust be held between the minimum
the capacitive load of the oscillator circuit and the capacitive load for which the
peration (typical value is 3 V). If a crystal was trimmed. Additional error will be added by crystal frequency drift
rrounded. The nominal Power-fail caused by temperature shifts. External circuit noise coupled into the oscillator
RTC and user RAM is denied, is circuit may result in the clock running fast.
.A lithium battery with 48mAh or RTC and RAM Address Map
1307 for more than 10 Years in the The time and calendar information is obtained by reading the appropriate register
bytes in the DS1307. Table 12.10 shows the address map for the RTC registers
,ut for the I2C serial interface. The and RAM registers in the DS1307. The RTC registers are located in the address
rnal pull-up resistor. The pull-up locations 00H--07H. The RAM registers are located in address locations 08H-
lltage on V"". 3FH. During a multi-byte access, when the address pointer reaches 3FH, which
rr the I2C interface and is used to is the end of the RAM space, it wraps around to the location 00H, which is the
face. The pull-uP voltage can be uP beginning of the clock space. The Function column in Table 12.10 indicates
the type of information present in the registers and the Range column indicates the
lriver pin. When enabled (i.e., when minimum and maximum values that can be stored in the registers.
t. the SQWOUT pin outputs one of
kHz, and 32k}lz). The SQWOUT
410 MICROPROCESSORSAND i/iCROCONTROLLERS

Table 12.10 Timekeeper registers is written. Write tran

the divider chain is
Address 7
Bit Bil 6 Bit 5 Bit 4 Bit3 Bit2 Bitl Bit0 Function Range registers must be u'ri
00H CH 10 seconds Seconds Seconds 00-59
Control Register
OlH 0 l0 minutes Minutes Minutes 00-59
The DS13O7 control
t2 l0 hour '
t-12 pin. The bits in the c(
02H 0 24 PM/ 10 hour Hours Hours +AIWPM
register are shown in
00-23
AM
03H00 00Day Day 01-07 I_eir? -Eir6 -l
04H00
05H000
10 Date
10 month
Date
Month
Date
Month
01-31
0L-12
lourlo .i

06H l0 year Year Year 00-99

O7H OUT O 0 sQwE 0 0 RS1 RSO Control The different bits in t
08H- RAM OOH-FFH OUT-The outpr.
3FH 56x8 u hen the square wa\
0. the logic level on
Note: '0' in the table implies that the bit will be read as 0.
as shown in Table 1l
Clock and Calendar tr pically set to 0.
Time and calendar information is obtained by reading the appropriate register Square wave en,
bytes in DS1307. Table 12.10 shows the registers in the DS1307. The time and ,.-rscillator output to
calendar are set or initialized by writing the appropriate register bytes. The contents iquare wave output d
of the time and calendar registers are in BCD format. The day-of-week (DOW) :egister, as shown in
register increments at midnight. Values that correspond to the day of week are -' lock registers updatt
user-deflned, but must be sequential (i.e., if 1 equals Sunday, 2 equals Monday, .t power to the DS 1:
and so on). Illogical time and date entries resuit in undefined operations. Bit 7
of register 0, which is at address 00H, is the clock halt (CH) bit. When this bit Table

is set to 1, the oscillator is disabled. When CH is cleared to 0, the oscillator is RS1 RSO
enabled. On first application of power to the DS1307, the time and date registers
are typically reset to 01/01/00 01 00:00:00 (which corresponds to month/datelyear
00
day-of-week hour:minute:second). The CH bit in the seconds register will be set OI
to 1. clue to which the oscillator is disabled. The clock can be halted whenever the 10
timekeeping tunctions are not required. This minimizes the battery current. 11
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours XX
register at address 02H is defined as the l2-hour or 24-hour mode-select bit. When XX
it is high, the 12-hour mode is selected. ln the 12-hour mode, bit 5 is fhe AM/PM
bit. rvith logic high used to represent PM. In the 24-hour mode, bit 5 is the second Rate select (RS l:
l0-hour b\t (20-23 hours). The hour value must be re-entered whenever the 12124- -:nut when the squa
hour mode bit is changed. ,, .'' e tiequencies thi

When reading from or writing into the time and date registers, user buffers i.' .i er to the DS 1301
(i.e., secondary registers) are used to prevent errors when the internal registers
'2.13.3.3 Data Trans;
update. During this process, the secondary registers are synchronized to the
intemal registers on any I2C start condition. The time information is read from
l:.: DSl307 can ol
- ::: l-i \l'ritten into tl
these secondary registers while the clock continues to run. This eliminates the
need to re-read the registers, in case the internal registers update during a read.
:-.initter mode (dr"
' -,r. :: a microcontr,
The internal divider chain in the DS1307 is reset whenever the seconds register
 8051 INTERFAC€ E\{Pi! a'l t

is written. Write transfers occur on the I2C acknowledge from the DSl3Oi Orx^e
ep€r registers
the divider chain is reset, to avoid rollover issues, the remaining time and date
B[2 Bttl Bit0 Func'tion Range registers must be written within one second.
Seconds Seconds 00-59
Control Register
Minutes Minutes 00-59
The DS1307 control register is used to control the operation of the SQW/OLT
t--12 pin. The bits in the control register and the function of different bits in the control
Hours +AIWPM
Hours register are shown inFig.12.37.
00-23

Day Day 01-07 Bit 7 Bit 6 Bir 5 Bit4 Bir 3 B[2 Bit 1 Bir 0

Date Date 01-31 OUT 0 0 SQWE 0 0 RS1 RS0

Month Month 01-12

Fig. 12.37 DS1307 conkol register bits
Year Year 00-99
O RSl RSO Control The different bits in the DS1307 control register and their functions are as follows:
RAM OOH-FFH OUT-The output control bit controls the output level of the SQWOUT pin
56x8 when the square wave output is disabled by clearing the SQWE bit. If SQWE is
0, the logic level on the SQWOUT pin is 0 if OUT is 0, and it is 1 if OUT is 1,
read as 0.
as shown in Table 12.i1. On initial application of power to the DS1307, this bit is
typically set to 0.
d by reading the appropriate register Square wave enable (SQWE)-This bit, when set to logic 1, enables the
in the DS1307. The time and oscillator output to be available at the SQWOUT pin. The frequency of the
=gisters
appropriate register bytes' The contents rl . square wave output depends upon the value of the RSO and RS1 bits in the control
ICD fonnat. The day-of-week (DOW) register, as shown in Table 12.11. With the square wave output set to 1 Hz, the
lut correspond to the day of week are clock registers update on the falling edge of the square wave. On initial application
if I equals SunclaY, 2 equals MondaY, of power to the DS1307, this bit is typically set to 0.
s result in undefined operations' Bit 7
Table 12.11 Function of different bits in the control register
rhe clock halt (CH) bit. When this bit
:n CH is cleared to 0, the oscillator is RSI RS0 SQWOUToutput SSWE 0ur
he DS1307, the time and date registers 0 0 lHz 1 X
r rr hich corresponds to month/datelyear
0 1 4.096kH2 1 X
lH bit in the seconds register will be set
0 8.t9ZkLtz I X
I The clock can be halted whenever the
1

his minimizes the battery current' I 1 32.768kH2 I x

our or 24-hour mode' Bit 6 of the hours x x 0 0 0

l-hour or 24-hour mode-select bit' When x x 1 0 I

r rhe l2-hour mode, bit 5 is the AM/PM
In the 24-hour mode, bit 5 is the second Rate select (RS1:RS0)-These bits control the frequency of the square wave
: must be re-entered whenever the 12124' output when the square wave output has been enabled. Table 12.11 lists the square
wave frequencies that can be selected with the RS bits. On initial application of
he time and date registers, user buffers power to the DS1307, these bits are typically set to 1.
event errors when the internal registers 12.13.3.3 Data Transfer between Master and D51307
dary registers are synchronized to the
The DS1307 can operate in two modes-slave receiver mode (during which
iion. The time information is read from
data is written into the DS1307 by a master such as a microcontroller) and slare
:k continues to run. This eliminates the
tqansmitter mode (during which data can be read from the DS1307 by' a master
' internal registers update during a rcad'
- is reset whenever the seconds register such as a microcontroller). The two modes are discussed in detail in this secliL'n.
412 MrcRopRocESsoRSAND MTcRocoNTRoLLERS

Slave Receiver Mode (Write Mode) slave address, the DS1.

In this mode, a master transmitter such as a microcontroller sends data bytes to the The DS1307 then begi
DS1307. which acts as the slave receiver. Serial data and serial clock are received address is given by the
through the SDA and SCL pins, respectively, of the DS1307. After each byte is before the initiation of
received from the master, an Acknowledge bit (A) is transmitted by the DS1307. stored in the register px
The start and stop conditions are recognized as the beginning and end ofthe serial each byte is read. The I
transfer. Figure 12.38 shows the data transfer in this mode. The slave address byte a read.
is the first byte received after the master generates the start condition. The slave When the DSl307 r
address byte contains the DS1307's7-bit address, which is 1101000, followed by the master receiver u a
the direction bit (R/W), which is 0 for a write. After receiving and decoding the register or RAM locatit
slave address byte, the DS1307 outputs an Acknowledge signal (A) on the SDA bir (which is set to 0).
pin. Next, the master transmits a word address (i.e., sub-address) to the DS1307. slave, as shown in Fig.
This sets the register pointer on the DS1307, with the DS1307 acknowledging the address or pointer) of t
transfer. The master can then transmit zero or more bytes of data, with the DS 1307 reading has to be done i
acknowledging each byte received. The register pointer automatically incremenrs the slave. Then, after a
after each data byte is written. The master will generate a stop condition to slave address and the t I
terminate the data write. and receives the Acknc
data bytes one by one t'
Slave address Rnfr Word address (n) Data (n) Data (n+1) Data (n+X)
slave and generates.an
bvte is received, the rrrl
S = Start Q From master to slave slave terminates the trs
Data transfened
A = Acknowledge (ACK)
StoP (X+1) bytes + Acknowledge) shows the complete det
P=
I From slave tc master

Fig. 12.38 Data transfer in slave receiver mode-write mode

Slave address Rfr
Slave Transmitter Mode (Read Mode)
In this mode, any master receiver such as a microcontroller receives data bytes
from the DS1307, which acts as the slave transmitter. The diagram indicating the
data transfer in this mode is shown in Fig. 12.39.The first byte is received and
handled as in the slave receiver mode, except that the direction bit (R/W) is ser to
1 to indicate read operation. The DS1307 transmits serial data on the SDA pin,
S = Start
while the serial clock is input on the SCL pin. The start and stop conditions are Sr = RepeaM Start
A = Acknowledge (ACK)
recognized as the beginning and end of a serial transfer. The slave address byte is
! = stop
the flrst byte received after the start condition is generated by the master. The slave A = Not acknowledge (NACI

address byte contains the DS 1307's 7 -btt address, which is 1 101000, followed by
the direction bit (R/W), which is 1 for a read. After receiving and decoding the
Fig.
Slave address RiW Data (n) Data (n + 1) Data (n + 2) Data (n + X)
Figure 12.41 shows the r

FxxxxxiTFilTI ,i the 8051 act as the S

:re pull-up resistance rl
S = Start
A = Acknowledge (ACK)
fl From master to slave
Data transfened
.quare wave (if needed

! = stoP f] From slave to master

(X+1) bytes + Acknowledge) ln. Using the 8051 sul
A = Not-acknowledge (NACK) .r ith the sequence men'

::.rnsferred between the

Fig. 12.39 Data transfer in slave transmitter mode-read mode
 8051 TNTERFA;: a13
=(\rPj:
slave address, the DS1307 outputs an Acknowledge signal (A) on rhe SD.\ prn
nicrocontroller sends data bytes to the The DS1307 then begins to transmit the data, starting from the register uht'rt
:nal data and serial clock are received address is given by the register pointer. If the register pointer is not urinen rnrr.
lr. of the DS1307. After each byte is before the initiation of a read mode, the flrst address that is read is the last one
brt (A) is transmitted by the DS1307. stored in the register pointer. The register pointer automatically increments after
as the beginning and end of the serial each byte is read. The DS1307 must receive a Not-acknowledge signal (A) to end
:r in this mode. The slave address byte a read.
:nerates the start condition. The slave When the DS1307 is operating in the slave transmitter mode (read mode). if
idress, which is 1101000, followed by the master receiver wants to access the data bytes starting at a specific internal
ite. After receiving and decoding the register or RAM location in the slave, after sending the slave address and (R/W.1
.l,cknowledge signal (A) on the SDA bit (which is set to 0), the master receives an Acknowledge signal (A) from the
ess (i.e., sub-address) to the DS1307. slave, as shown in Fig.12.40. The master then sends the word address (i.e., sub-
. sith the DS1307 acknowledging rhe address or pointer) of the specific internal register or RAM location from where
tr more bytes of data, with the DS1307 reading has to be done in the slave, and receives the Acknowledge signal (A) from
ister pointer automatically increments the slave. Then, after a repeated start (Sr) condition, the master again sends the
er will generate a stop condition to slave address and the (R/W) bit (which is ser to 1 now to indicate read operation)
and receives the Acknowledge signal (A) from the slave. Then the master reads
data bytes one by one from the desired internal registers or RAM locations of the

;[ffi;l fw;ffi
Data (n+1) Data (n+X)
slave and generates an Acknowledge signal for each byte received. After the last
byte is received, the master sends a Not-acknowledge signal to the slave and the
t Dula transfened
slave terminates the transfer. The master sends the stop condition. Figure 12.40
, (X*1) b(es + Acknoudedge) shows the complete details of this data transfer.

receiver mode-write mode

Slave address R/ifr Wod address (n) Slave addles's

a microcontroller receives data bytes

ansmitter. The diagram indicating the
11.39. The first byte is received and
)r rhar rhe direction bit tfvWl is set ro
ransmits serial data on the SDA pin,
S = Stad ffi From master lo slave
lrn. The start and stop conditions are Sr: Repeated Start
oata transfered
(X+1) bytes + Acknowledge)
nal transfer. The slave address byte is A = Acknowledge (ACK) f] Fom slave 1o master

r is generated by the master. The slave

l"sta
A = Not-acknowledge (NACK)

dress. which is 1101000, followed by

ad. After receiving and decoding the
Fig. 12.40 Data read-slave receive and transmit
Date (n + 2) Data (n + X)
Figure 12.41 shows the interfacing of the 8051 with the DS 1307. pins p0.6 and p0.7
FlrxxxxxxxlM fxxxxxxuTffiffiltr of the 8051 act as the SDA and SCL, respectively, of the I2C bus. R* represenrs
the pull-up resistance that is to be connected to the SDA and SCL pins. To get a
t D.ta transtored square wave (if needed), another pull-up resistance is connected to the SQWOUT
-
f
(X+1) bytes + Acknowtedge) pin. Using the 8051 subroutines written in an assembly language program, along
with the sequence rnentioned for data read and write in the DS1307, data can be
transferred between the 8051 and DS1307.
arsmitter mode-read mode
 414 MtcR0pRocESSCRs Ar.tD tvlcRocoNTRoLLERS

I 32 768 kHz
ui'
t- -l
l uty5Ld
) I
I

R". n,, f li lL
l----_i
(
I irllrl
_r__
I

----l _ _t I
I
I
I

l
.il
I Yt \2
l
l-
I
I i l
p0.7 I
I
J
I

-l
I --] t""'
o., ,),*,orr l-
8os1 l

I
I

i
I
I

l --
poo L I _-]roo
I

v* I-_ -
;-_-'_l
I

t olo _[-l
I
1

I
I -r-
I
.l

+
Fi1.12.41 lnteriacing 8051 with DS1307

'fhe nuruber of uo ports in a rnicr.c.nt.oiler

can be increasecr by interfacing the
prugrannriable per.ipheral inrerface chip (g2-55) with g051.
the
D.iti'erent vo
devices such as LEDs, seven-segment displays,
LCDs, ADCs, and DACs
ca, bc interraced with the 8051 microcontrorler, either
clirectly or through the g255.
G 4. DAC inrcrlaced with a microcontrolre'can be
used for ge,erating many waveforms.
3 z\ tttuitipiexed display can be used tn recluce the hardwar.e and thus reduce power
.'\:risillilpricji. I iris is achieved at the cost of softw,are
oYerhead.
stepper inotor or a DC motor can be precisery controned,
'\ ifinterfaced and controlled
ii :; i ng: a rnicrog0r11011sr.

-'; riii'-i.c')nirollei'can be used for many industrial and

domestic applications such as
trrt l;' ii;:Jit cro'il'or, temperature control, weighing machine control,
and lighting contror.
l'h': -r:aders can deverop many more apptrications, using
combinations- of interfaces
.l1..11rre1l ir this chapter.

f,**.**o*.***#t
l f)iscuss in derair rhe interfacing of the stepper motor
with the g0-5 r.
2. What is the need lbr the g255 in a microcontroller_based
system?
3. Explain the interfacing of push b,tton switches and
t.EDs with the g051
microcontroller.