| sve Silicoo it 2 VLSI Training company tht offers ide range of corporate and professions) Wanthg 1 ends thn fers SystemVieilg based advanced verification courses and holds the Maven Silicon Evelvad in VLSI Tectoolopes, Mn CESK Maver Silioe & Be caly trining company FRiteteniting 250+ engreesspeyerr é Wits dirinking process nologies, ever 3 Seoenely complies end cobeal pert of axy SoC design tod > Seapesics bre Gest VLSI engines wbo ave excessively Gran anly fer chip venSeation. Usually 70% of the engineers in any jerrk on RTL design, STA and Analog ete So there are _eruion of {P to « single chip, verification has become “consomes 60% ofthe design cycle, most of the VLSI product ox services company Jenty of job opportunities for fresh VLSI eagineer= ceeping this fat in our mind. You cas depend on the renaming 30% ef the eopinecrs IC wariication. We at Maven Silicoa bave designed the courses ‘Povtructare tolearn the VLSI technologies and get job inthe top semiconductor industries indasties. He hts worked as Verification Consultant he worked very closely with various ASIC and FPGA i million gate designs, ‘who are Rigby billed in ASI er eopertiec and word class training in Oe CEO, Swakume PR bes 19 yeas of experience in engineering nd semiconductor Cibctop EDA compenies Synopeys, Cadence end Mentor Graphics. During this tenure Gangs boeacs tu beiped the to use the EDA solutions effectively, forthe suecessfl tpe-onts of GOD | FIVE REASONS TO MUSE ON MAVEN SILICON INCLUDES, | 1 syrtemiertiog besed Advanced Verification aves Siico #8 he taining ocate edifics capinecrs on the advanced ASIC Yare SPE Soilopa and SyseaVeilog. Ia aidtion 1 these advanced | Reese berries Bena | Baler Retain. Weaioe ASIC & FBGA dein fom. 914 & CMOS | eoeemeoale | 2 Coarse Delivered by ndastry Experts : composed of aévanced VLSI design and PiLSlcnginecrs can deliver AIMaven ‘end pode you 00 bow to exhance As cose: och = VLSLRN are sa Saxtien technologies only experienced ‘Sime, indemry experts share their experience your shlls 0 VESTindasrics. Seperier Tralalag Methodology ) Up Ugo qw -w-h~ ‘At Mevex Sticon, the experienced engineers who work inthe top semiconductor Mm MES, Soe thee cqpeicnce with you and demonstrate how the caacpts OF i Tament Only 30% of 580 hours of VLSIRN course & for labs, mini projects and final ‘wlewcric chonly wih various VLSI preuctand services compasies snd idea he pe rodeos who successfully complets ous trining, Progras. renowned semiconductor igh opportunities fort a Fe Bie veadeas beve been successfully placed io companies { provides pres! opyarnties to copineers 10 ‘work on verification platform like advanced ASIC verification technologies end EDA Partner - Mentor Graphics ign Automation. Its innivative L_ challenges. in Mentor Graphics is leader in Electronic O P| products and sohmons hep pagineers conquer design Seerringly daunting word of boardana diipdesin vweww.maven-silicon.com vores nentorcom i | eeaghies, please vi Toknow ne about MentorSo bitom ore Brn pat ‘uy SILICON System Verilo g www.maven-silicon.com 2Tico N maw ‘Eb Maven Silicon Cenfidential —_——_____—_—_ sl All the presentations, books, documents [hard copies and soft copies] and projects that you are using and developing as part of the training course are the proprietary work of Maven Silicon and is fully protected under copyright and trade secret laws. You may not view, use, disclose, copy, or distribute the materials or any information except pursuant to a valid written license from Maven Silicon www.maven-silicon.com 299 course Objectives , y _—_ + Leam how to build the class based verification environment using SystemVerilog TB features + Learn how to build the regression test suite + Leam how to generate the functional coverage wuvw wz w w www.maven-silicon.com wy d T v . v é i b L Course Agenda Day O Tasks and functions O LABI - Data Types O SystemVerilog Overview ~wwwewew we O Data Ty wae Interfaces O Struct and Enums 3 « OQ Clocking Block O. Memories » QO LAB2-Interface y ’ | www.maven-silicon.comFRAVER, Course Agenda Continued.. ———__—_—_ ee Day 3 Day 4 DQ OOPS Basies 5 ayanses OOP: 0) LADS = Bsa200P 3 Resale TB Environment OQ TBaArchitecture irtual Methods i OQ LAB4~ Advanced OOP www.maven-silicon.com 5 7 d nA ME sia Course Agenda Continued.. — Day O Threads Q Mailbox, Semaphore O Events Q LAB6 -Threads, Mailbox O Randomization O Constraints Q_ LABS~ Randomization www.maven-silicon.comr Course Agenda Continued. iDa: > Build env components OQ Generator OQ BEM Q Monitor O Reference Model Q Virtual Interface Q_ LAB? - Transactions O LABS - Transactors www.maven-silicon.com ARAVER, Functional Coverage Scoreboard Environment oooo Regression Testcase Q LABS - Functional Coverage(Scoreboard) © LABIO- Environment ANAVER, L SILICON Ba CT) CIC aEHDL Limita fi ey ver? + HDL Limitations - Verilog/VHDL — « paomoty Son vat * Static- Consumes Memory —> » yordenbe = can Coll 9! eet “a! vartablet , + Randomization — Constraints TS kricle Hho data * Code Coverage - RTL Measure w.r.t Design Intent missing i * Functional Coverage Missing a * Reusability — Reuse without breaking the already working code “ www.maven-silicon.com c A VER SystemVerilog HDVL ——_ + Aset of extensions to Verilog-2001. + An unified language for design and verification. + A language which supports all the verification methodologies = Constrained Randorn Coverage Driven Verification « Assertion Based verification = Functional Coverage «A language which supports Object Oriented Programming www.maven-silicon.comPep da PSL— Assertion Based Verification 1pcy ee wag: * VERA ~ Randomization and Constraints notte Elnih Spe sete sie wire ree modus poet Eetrpay force Terr eal rare = Some (Orbe Wet che mang packed sears diane Ba = me YD'memny oa CMAVER, SV Sources , a * SystemVerilog is an IEEE sandard language, based on Verilog 2001 * SystemVerilog extensions come from a number of sources including: * C& C+ ~ Data Types and Object Oriented Programming * VHDL ~ enum, packages + DPI from Synopsys ' : 7 1 peqvomtng tyhunitewe Preqiening Tatahae www maven-silicon.comSystemVerilog References —_————_ AIEEE LRM + Text books and quick references + Writing Testbenches in SystemVerilog, Janick Bergeron + SystemVerilog for Verification, Chris Spear * www.verificationacademy.com ‘www.maven-silicon.com 13 CG STL ICO Nd Bl Lei aU tteData Types - Verilog 2001 ——_—_—_—_—_—_—_—__—_—__ wa Giles —> + Four values 0, 1, X and Z + Two main groups of data types ~ nets and r + Register data (ypes - reg, integer, time and real + Store a value from one assignment to the next + Are assigned a value in a procedural block (initiaValways) req [15:0] databus; // 16-bit 4-state unsigned reg typo integer countl, count2; // 32-bit {-state signed types real real_va: 7/ real number Towne? alone ui sah) 4 System ertlog —aloast wath fo difind nas cal +ypos www.maven-silicon.com 15 | Verilog 2001 Data Type edie snd logic (ovepne Op yee TEES | www.maven-silicon.com 16ARAVER SystemVerilog Datatypes ———_————_ ry + Logie: 4-state data type (similar to reg) 0,1, 2 daft t (ontinoron) used eHhen as Jeg ot ulive + Two State data types + Enum: Declares a variable that can have a list of values ‘ xy - Gab valu % automat! aly + ‘Typedef: User defined Data type onvakd fo a 2- Mok Vvolup, yaoand z will be Conve + Struct and Class to xen www.maven-sil f tT uf ¥ v EF nd ‘Logic - SV Data Type Onlinds = Alogic has equivalent functionality to reg ued ve «Logic datatype canbe used anywhere thatthe reg and net data types are traditionally used, except inout ports The logic data type is synthesizable and it can be used to define both Combinational and Sequential logics + Confusion in Verilog HDL ~ reg data type can be used for both «Combinational and Sequential but in hardware reg Register] refers to sequential www.maven-silicon.com 18» Logic - Example — modele legic_cest 0; paraneter logic g: qb. & cl ) initial begin elk =o /1 Procedural ansignnent forever 4 (cxewe/2) elk = sera; | 8 (negedse elk) end ~ ession qb ~ ~qi // Continuous assignment SEE DUT Iq. ay clk. catia; endrodule : logic test www.maven-silicon.com 19 wedale of logic (cutpur dagic youre input logic «in. b int sesiga yout ~ eis 1) Biss «| ecmodule : opie a. br ) logic tndoat. or_out; moat at (end ovt. wee © Corot. be se: | ww maven-silicon.com 20STUICO NS 2-State Data Types 4 - 4 Shoe A 2 vay + bit is the Basic 2-state scalar type “recat + byte is an 8-bit signed integer 2-state type x 4 x azn ouaignt + shortint is a 16-bit signed integer 2-state type dakatye ( i csavenhd + int is a 32-bit signed integer 2-state type + longint is a 64-bit signed integer 2-state type + When a value is assigned to an object of any of these types, x orz 1 values are converted to 0. 2 3E END dastgaea Integer should Ix te bite algnea Iatages x To wakb hen = be date tone improves simutotion pertoenarce | Qiocrlf j ‘int on rt onal www.maven-silicon.com jek. deceid 2 dake dalakype becawe fk mies gor fo onknowe tate Struct ee [Cotecton a To dion ee) a dakctypa) + Struct — Collection of data - Static + Array of different data types eq 8 yy. + Synthesizable 55) ood + Subset of Class — Use class for TB (ot — gr paststyee tip — ble atruct {bit [ pixel-r = 8°d25; pixel-g = 8°255; pixel-b = 87311; bdisploy (“7p ", pryarl: lor, gy bs) pixel; www.maven-silicon.com 7MAVEN Stevea nN) User-Defined Types 1! ——______ + Typedef used to define a user defined data type yt coals uses ob en dala type tpliee bit(a1:2) ford wordt ordi, word?! Syaladype Samsung_pixel r=25 11 user defined structures 5-0 typedef struct [bit [ pixel_st samsung pixel; 0) r- ge br) pixel_oez b=0 pixel st sony pixel; pensung_pixel.s - 8°25; Sony_pixel 0 pony_paxel.g ~ 6°238; 35 struct [bit (92) Ee, gy bi) pixels pixelp = 2° www.mayen-silicon.com 23 RAY eh Type Conversion Conversion between data types cane be done in 2 ways. 1. Static Casting int i; a real r; ink t= y inint’(16.8-0.1); veal Ye r= real’ (42/8 Liersabe cans ] 2. Dynamic casting: using Scast It allows to check for out of bound values. It can be used as a function or as a task www.maven-silicon.com 24Enumerated Types (neq dala type) are declais A + enum - enumeration data type (list of values) “bd a¢ fale oe ve ag tate som (sts wendy writes bed wll fom pista) befor dedi ¢ o rteas hye wre es had use typedef enum | red, green, blue, yellew } colors_e; colors_e ¢ = c.first; forever begin Sdisplay( “$2 : Sd\n", c-name. ©); Af(¢ — c.last ) break; qateput - G stale Greg Pat = 2 stake www.maven-silicon.com) 25 AK ¥ c sia Enumerated Types ——_—<—————————_ 4 Default values can be given to constants. Ex: typedef enue {red, green, blues4, yeLlov-7, white} color_e; color_e colgr; + In built methods available are 1. first () //retuns 1* element 2. last () //returns last element 3, next () // retums next element 4, prey () // returns previous element 5. next (N )// retums Nth next element 6 prev (N) // returns Nth previous element dvdm - © do * tute wowernedel: sv" ) \www.maven-silicon.com iFRAVER, Enumerated Types : Example typedef enor {red,green,blue,yellov, ite) color e; caler_e color; Sakic cosy ist | ‘ Siti ekg ee; initial wat ack: ve fees Ae esin *, Ly sh case's colored; Aaah 5 92 nal la}, @ TPS stach cabling (1); Jf Static casting: to type checking i /I Dynaeic cast using Scast as task: gives error as 5 is out off bound valle. olor,5) } ff Scast used as a function Sisplay!*casting failure”); end roy ) | www. maven-silicon.com 27 » *Variable length — grows automatically *+Memory is dynamically allocated *{} — Used for concatenation 11 Bisplay: ieee Built-in functions: toupper, ; tolower, putc, getc, substr 7 rh “tot! 11 Ceeete texpor ay Lon Spapeinel (42 5 on [posse eee || jeter Us Onin I) priate 4", B Conpusla)): siait tt sp tongasd 8) Vostotot i) M1 "texe-23200" WI Siaplay: E2-P sessage): = “ytPackages ——_——____ + User-defined Packages (ae _ 71 clobel variable = Define type definitions, ime on cansactions: functions and global inetode “mes | variables for re-use endpackage + nes_package | throughout the design sadite men.tests = Good for functions like import sex_packes \ printing error messages, isleset reading/writing a bus, etc. regis eonene ene = net) = Good for reusable ‘end eavorun (}; Environments Test cases import the package endnedule : nen_test www.maven-silicon.com 29 | .Summary - Data Types —— + Enumerations (enum) * 2-state datatypes (bit, int, shortint, Jongint, byte) * Allows for more abstract modeling and is compatible with SystemC and C/C++ Removes “X” and “Z” states, which is compatible with cycle simulators or emulators * Struct and Enum + User-defined datatypes (typedef) * Allows users to define a type that is used throughout the design + Strings + Packages + Tesicases import the reusable environments www.maven-silicon.com 30| j } 1 | | | ANAVEN = unpacks a4 !- bit fvolauay y{210] bit [20] Eso] avsy 5) pood was d u r « EF 1 Packed Arrays ———_____—__ // 4 bytes pecked into 32-bits bit [3:0] [7:0] byte packed; sa vh(byte_packed, // show 211 32-bits byte_pecked{2)- IJ Mose significant byte byte _packed(2][7}}; // Most significent bit bye 3] | fpsreisia (Of 7/6'514'3/2' 1/0} 71615] 4131211101 7/6 514] 3]21710 byte packed www.maven-silicon.com 32FRAVER, SILIC OM byzes (0) = o1(2) ~ 5 {6} (1) {6 les ~ bytes {O)7 US copy packed values (3h byiesto1_] }7léls|4!3{2/ 10 7lels[47s(2i4]0f7. bytesi1] | [7461544)3/2/1/0]7/6|5/4/3/211 pyesia)_| (zletslaizizis{of7i6[5i4)3/214 33 wwewemaverrsiliconcom . L STLIC OM Dynamic Arrays : ——_——__———_ + Variable Size single dimension memory - size changes dynamically ‘Syntax - ype na: during run time L Tae deh), 202007 inieiel pegis dat = wew[S]s 7 1] Kiiccate § elesents foreach ( dai(3]) 1) rnitielitieg set (§] = 35 a2 = det 11 copying Gai - new{2¢] (dat): // Allocate 29 dal = new 1) attoce’ der delere (0; 1 Delete a end | www.maven-silicon.com 3- an mention ko wears, | A TE | Tae deel poe Wine dalk te mony . ea a Logic [7-0] mem_mode! [suing}; ‘Standard exey Assodative array } ™ = KT See www. maven-silicon.com Stereo aAssociative array example ooo module test() Aloy initial Th oany he a . P begins ale ye BIE Pawo neem [bd [sree)) Ant wweml int}; 7 No a3 35 a > “ S At (memexists()) Sisplay (“entry exists in the array Sd *,mem(5)); else sdisplay(*no entry"); sdasplay(*\n Sd ¢ number of entraes in array *.mem.nur ) end endacdule 44 output - entry exists an the array 60 46 4s nuaber of entries in arr: Wwwmaven-silicon.com onpacktd adiay Array Methods “Felowg ae + Array Methods can be used only with unpacked arrays {i «Fixed, Dynamic, Queue and Associative Arrays a) 2a mis 8 Isat ie a ta Elid fast ne 277 aS Pas rrr aio Wwww.maven-silicon.comAAVER Summary - Arrays , $$ <$§__ —_ + Dynamic Arrays + intdyn{] + Small memory sizes— 1K to IM bytes + Associative Arrays + intassocfindex type] + Big memory sizes -> IM bytes 7 + Queues > dusk rwnling Hg Be ot he mamoyy + intque[$) mgr con tino uly + Emulate first-in first-out(FIFO), last-in first-out(LIFO memories + Memories when data size grows and shrinks often toy to add we gyre fo amottan qveud ovis 2,3 § = 9561 92= D5 saemavensilicon.com 39 foreach tats 4) wank (40) f if : ¥ EI uJ Summary - Array MethodsC SFLICON wt Forction- dee, pohin wlup_, ral Sere re aed al. dount ta‘uir value Sama wamary walic - Compile Ara futeratc - dusing Aon hint ah weno c TAVER, Verilog Tasks and Functions * Tasks: + May contain timing: @(...), fidelay, wait « Portscan be input, output, : ena orinout Gndtask: write sam Can optionally have no ports rag [31:0] newbuas integer iy + Functions: «No timing is allowed ~ must execute in zero-time «Can only have input ports— and must have at least one newbus = bus; swapbytes > (newbus) : end endfunction + suapbytes ee —| icon.com 42 www.maven:~~ wwe ww ww -w C AVER, Enhancements in SV ———————_E- + SystemVerilog adds the following enhancements to Verilog 2001 tasks and functions: Multiple statements in a task/function don’t require begin/end block + Function output and inout ports + Functions can return a “void” type + Retuming from a task/function before reaching the end (return) ~ + Passing arguments by reference (ref) and by value. + Task/function arguments passed by name instead of order + Default task and function arguments values are allowed www.maver-silicon.com 43 d T ¥ ¥ ¥ Ef b Void Functions eT + SystemVerilog allows functions to be declared without a return value * SystemVerilog aliows function arguments to be declared with the same directional specifics as tasks (input, output, inout) Functton tot sunmation(taput (3:6}x, input [5:0]y, outpot [5:0]2): summation = x+y: Bn 2 > sunmation: endtunceton function veld display: ‘Sdtsplay(-Sum 15 20d end doubled value ts xed", sun, double): endfenction J {Kevocatton of veld tunctlon doesn't require an asstgnnent tntetat beste sun = sunmatten(a.b double); // tradtttonal function stsclayO: 11 vols functton end www.maven-silicon.com 44Return Statement ——$@@]|§_@ _— * SystemVerilog supports the return statement for tasks and functions: + return expr ; exits a function and retums a value through (expr) + return ; exits from a task or void function without continuing to the end [Fonction tateger malt(ine stot bye AF (C3520) | 1(beH0)) begin ' Sélsplay(“Dont nuletoly with ZeR0"); F cetarn “hx: Sélsplay(“attenpe nade for multtplytag with zero ts fatled™): 7/ Wt WiLL not be dtsplayed end ask print_status(int errors): tte ant; ‘uf ((errors==8)) codfenceton Sélsplay(“ne errors have been reported"): return: Séisplay (“everything seens to be working fine"); end else Selsplay("the ne. of errors te "Od", errors): frdesk 45 www.maven-silicon.com Ue STEL OO RS Passing Arguments - + Asguments can also be passed by name as well as by position. + Task and function arguments can be given default values, + This permits the call to the task or function to omit argument values. * In Verilog-2001 pass-by-value is the only mechanism for passing arguments to subroutines. + Each argument is copied into the subroutine area. + Ifthe subroutine is automatic — the subroutine keeps a local copy. + Ifthe arguments are changed within the subroutine, the changes are not visible outside the subroutine. + When the arguments are large, it can be undesirable to copy the arguments. ‘www.maven-silicon.comSTLICO * Itis useful to pass function and task arguments by name instead of by position. = Analogous to port connection by name where position is not required + This functionality was added to SystemVeriiog to augment the default argument assignment capabi = includes default values 570. ke deca = 1)e endtask ceed ocetion of the task with default ergusents and name pessing teger vel = 22; ees (518). 88s reed (i dy dace: ne WI equivalent to 12, 0. ewes . www.maven-silicon.coni 47 * SystemVerilog allows default values to be specified for function and task arguments. + If an argument is not specified when the task or function is called the defaults are used. * An error occurs if you try to use a default when the default is not specified. // default orgunent values in task definition task read (int j= 6, int k. int date = i)7 endtesk ; read // invocation of the task with default arguments Anteger val = 21; // 22-bit integer val read ( , 5); W/ equivalent to (3, , 1) read (2, val); Jf equivelent to (2, 22, 1) read iG U/ equivalent to (3, ©, 7) read // ROR ~ because k ip not definedPassing Arguments by Value + Default argument passing in | "= top: Verilog 2001: byte packeti(i202: * No change in snitial int b= exe packet ); SystemVerilog = Variables or constants can be passed into the task or function. t www.maven-silicon.com (RAVER 49 Passing Arguments by, Ref) module top; ovenOu by byte packet1[1000:1]; Pa initial int k = cre( packetl ); function eutosetic int crc( xref byte packet (1000:1] ), for( int j= 1; j <= 1000; j++ ) begin cre *™ packet (j]7 end endfunction endmodule =< www.maven-silicon com f ' ¥ ¥ EF b 50we abe ulteg idop spt d f \ ¥ EF bh Verilog Interface Signals ————___ae Verilog Limitations Low level of abstration for communication between modules Limited reusability — hard coded paths = Easy to change interface * Verbose - cumbersome Any smail change in the signal name at interface level needs change at multiple places www.maven-silicon.com 52ARAVER, SystemVerilog Interfaces * Interface — Static Component * Encapsulates communication between hardware blocks = Bundle of signals Reduce the amount of code and promote reuse = Supports always, initial, task, function, assertion, covergroup = Synthesizable www.maven-silicon.com 53 Interface Syntax —_—— interface i_nens [( interface ports )]; [parameters] interface_defi: 3 endinterface [ = i_name } interface men_bes (clk); “1 port of the interface 1 parameters // input to the interface V1 incexface objects endint. www.ma ven-silicon.com BSSemon Ree eee mum: Verilog — Port Connections [modute nen_ace Logie (1:0) mode, logic (7:0) addr, Anout wire (7:0) data, eutpot Bit gut. ray module cpu_nod ( input bit oli inowt wire (7) output bit req, Logie | Logie | in bit reqs clky 0] date, gat. xdy, www.maven-silicon,com 55 Cnsre fen, module top? logic reqs gnt, tact, rdy; logic elk = 3; Logie (1:0) mode Logie 17:0) addr date; men_nod mor (req. clX, stort. ddr. data, got, dy) epi_med cpu (elk, got. rdy, data, req, start, addr, mode); Interface Instantiation V1 Interface Definition interface sinple_bus; logic req gntz addr; date; endnodule 17 Top-Level Testbench nodule top; logic elk = oy simple_bus bush 01; mes_tod men (clk, busa) epu_ned epu (elk, bush); + top zodvle coe aed ( ‘module mez mod ( input elk, input clh, simple_bus bus sizple_bus bus ui h endbodule : cpa_nod ondvodule : nem nod www.maven-silicon.com 56// Top-Level Testbench zodule top; logic clk = 0; simple bus busA (cli 4 menHod mem (bus); cpullod cpu (bus); 17 Toterface Definition Anterface simple_bun (input It clock); legic req, gnti Logie (7:0) addr: wire (7:0) date ondinterface : simple bus endnodule : top podule cpu_mod ( module meh mod simple'bus bus simple bs Ms - Sgosedye (bus-clock) endmodule : epu_nod www.maven-silicon.com 57 ane ‘ ¥ € Ah Interface Modports _—\————_ rm Modport Permits customization of an interface for different modules ‘+ Provide direction information for module ports «Specifies which signals in th terface are accessible to a module 7] Interface Definition interface simple bus (input bit clock); logic req, gat; logic [7:0] addr; wire [7:0] data; modport mem ( input req, addr, output gnt); modport cpu ( output req, addr, input gat); endinterface : simple bus www.maven-silicon.com 58Using Modports nodule testhen: Logie elk = sizple bus (el; mes_nod nen ( bus ); epu_nod cpu ( bus ); endnodule : testbench ——__ [module men sod ( simple bes.mes bus}? | endrodute ? nex mod www.maven-silico. n.com 59 Interface References Sr module me aod ( ispet elk. imple bes bus J: ses (0:31 = write ~ (bes.gat 66 (bes.made 1) J: eosigs bus.dite = read ? rdate : ‘bry alvazs & tposedge elt) (reed) date ~ nea[bus-adte]; else if (write) 77 Yatectace GFinition interface sisple bes; logic req, staxt, gat, réy; logic [3:0] mode; losie 17 wire [7 endinterface : ixple bos c RAN 1 EA, www maven-silicon.com 60 i i |Tasks and Functions * Tasks and functions can be defined within an interface. = In SystemVerilog they are called interface “methods” «Declarations use the same syntax and statements as in a module definition = Call the “method” from modules connected to the interface using an interface reference. I/ sizple bus interface instance) simple bus bus (.*); | ID ealling write task fea gat stare, edyz elk) | tus.weite (pe_addr, pe_data www.maven-silicon.com 61 Verilog Event Scheduler Previoss time slot www.maven-silicon.com ro nent tine stot RAVER 62previous time slot FRAVER www.maven-silicon.com 63 + Provides race-free operation + Your testbench will always drive the signals at the right time! + Setup and Hold time for the DUV can be modeled Clocking Block i $< a Benefits: Same TB can be used for both RTL and Netlist simulation Functionality: An interface can contain multiple clocking blocks There is one clock per clocking block Only for testbench Default is “default input #1 output #0;” www.maven-silicon.com 64‘lock + Input Skew - TB saff\ks + One clock cycle delay from DUT output to TB input = Output Skew ~TB drives the DUT inputs at the clock edge «No delay from test bench output to DUT input + When you are using interfaces with a clocking block: default input #1 output #0 UT outputs before the clock edge www.maven-silicon.com c Srerco ns Clocking Block - Modelling www.maven-silicon.com anf v Ef b 66(MAVEN, STUICO zi Clocking Block - Syntax ——— gna Access ynchronous eo Aton dy 07 quent <1) 9 MY drive Antectace art if (ispot Mt ell); module tee Logic grant. request, reset: dr itidee cloaking de_ch #(posedge ell}; valve = dv if-dy_ebogeant; | {7 sample impor grant: output request: fendclecking: dr_cb endinterfnce: arb if Bde it-dy_cb; // continue on ponedge of arb_if clk repent (2) #dy_if-dy_cbi // Wait for 3 posedges ! All drives must non-blocking assignment www.maven-silicon.com 67 i top.sv \ www.maven-silicon.com 68ANAVER erco nm) DFF Interface y7tntartace fnterface dft_2¢ (input clk) Logic do, di, vol, rat, a: parometer thold * 2, rst tuatup © 43 C1 Anput Skew.» Taetup N J) output skow » thold eb O(posedge clk); woet dapat wteetup) ovtpat #( thot): ioprtcar . output do; sj, putput di; my) ‘ output sol output rot: endclockiag . modport DUV (input dd, di, sel, rat, clk, output qs modport TEST (clocking cb); www.maven-silicon.com 69 ARAVER, TRosding irouk a a cotlat modpart ify (Ced89 iinperts | 48 Iya. Mel dank tere! Fie thet www.maven-silicon.com a0DFF DUT PRAYER, Logic d: | 1 “always @ (+) 1 begin Tst caeclduy_if-s6t) Nee ee { | Or d= dov.at do; li:d = duv_if.di; do | default : d = duv af .do; d1— | endcase 7 sel jo end | always @ (posedge duv_if clk) |.” begin SLE clk——_ EF" (duv_af.rse) ———__— duv. T4.g = 1°60; else Guy ita «di; end jendmodule www.mayen-silicon.com a) ang Tal EF | module testcase (dff_if.TEST test_it); //applying stinulus initial begin @(test_if.cb); test_if.sync_reset; i test_if.sync_reset; | test if -sync_reset; test_{f .load_do(1'b1); test if sync_reset; test_if .load_d1(1‘'bi); test if. load_de(1‘bo test if .load_d1(1"bo); test_if.sync_reset; #180 Sstop; | end | endmodule: testcaseSTE eon) Top — DFF and SV TB _———————__BEE- ° module topt; bit clk; parameter cycle = 100; dff_if ouvir (clk); Clas DUV_RTL (OUV_IF); testcase TEST — (OUV_IF); Z{clock generation always begin #(cycle/2); clk = 1*bo; #(cycle/2); clk = 1'b1; end lendmodule www.maven-silicon.com 73 sreie gh) Typical TB Enww w se —w- we ay ~ we ANAVER, SILICON — Summary Interfaces simplify design block communication and raise the level of abstraction. Tasks and functions can also be defined inside an interface. Modports — defines the subset and directions of ports Clocking Blocks used only in TB - sampling, and driving the DUV signals www.maven-silicon.com 78 Verification PlanDual Port RAM - DUV . “ patour a OATALIN ,__| aan 2 wR_AooR 2 ——~ +] ouotrortnam — $= ap anon soos x64 er ,— wate _— ox Dual port RAM can be written and read simultaneously. This special type of RAM has two unidirectional data ports ~ an input pon for writing data and an output port for reading data Each port has its own data and address buses. The write port has @ signal called WRITE to allow vwriting the data, The read port has a signal called READ to enable the data output, Both reading and writing data occur on the rising clock edge www.maven-silicon.com 77 pestul ANAVER| Environment/TB Infrastructure Environment Interface —> Mailbox 78 www.maven-silicon.com+ Features = Reset = Read + Random Read - Reading the empty location * Random Read — Reading the same locations consecutively = Write + Random Write — Writing into the same locations consecutively = Read+ Write + Read+Write - on the same memory location www.maven-silicon.com 79 | Verification Plan —$—_ * Strategies © Reset ‘* Write zeros into the memory © Read ‘+ Random read — reading the valid data + SB: Compare the data only during read operation + Receiver : Collect the read address end data_out and create transaction + Random Read - Reading the empty location + SB: Message: NO random data writien ‘+ Random Read ~ Reading the same locations consecutively © Write + Random Write - Writing into the same locations consecutively + Memory Mode! = Model: A reference model for memory is implemented using associative array + Read+Write + Read+Write - on the same memory location + Not allowed - Define a constraint in Transaction www.maven-silicon.com 80(NAVER, UicoNn Verification Plan —____—_ * Transaction + Base Class ~ Random : Read and Write Acdilresses, Input Data ivead and Wnte contro signals + Extended Classes: + TCI: Data & Address - Weighted Random, TC2: Address - RandC, TC3: Directed * Transactors * Generator ~ generates random transaction * Driver — Drives address, data_in and control signals for Read and Wnte operations * Receiver — Collects the read address and data_out and composes received transaction + SB - Compares the transactions and generates coverage * Coverage Model + Data = [MIN, MID, MAX] + Address: [MIN, MID, MAX] * Address X Dita + Address X Data X Write + Address X Data X Read + Address X Data X Write X Reads * Callbacks ‘+ SB: Callback trigger the coverage mode! 81 www.maven-silicon.com C STO NA OOPs BasicsOverview of Classes a u \ v & f b $a + SystemVerilog provides an object-oriented class data abstraction * Objects can be dynamically created, deleted, assigned and accessed by object handles + Object handles provide a pointer-like infin bom dle = wud + OOP - Collection of interacting objects + Class + Object * Inheritance + Polymorphism www.maven-silicon.com 83 Properties / Methods $$$! ae * Acclass consists of two items: + Data which are referred to as class properties/members + Tasks/Functions which are referred to as class methods celal int balance: // class property or menber function int summary; 11 cless nethod return balance; endfunction task deposit (input int pey); // class method balaace = balance + pays endtask endclass www.maven-silicon.com 84Instance / Object Creation —_ * Aclass is NOT a stand alone design unit such as a module + Acclass defines a data type * All classes are dynamic and require the user to: * Create a variable to be used as a object handle + Create an object of that class 11 create variable for object ‘/ create variable for object M1 handle, create object and assign] |// handi=, create object and azzign 71 handle in? steps 17 handle in step class account_c; // class datatype class account_c; // class datatype int balance; function ‘int summa return ba function int sum return ba! endfunction endfunction endelass endelass SS ncccenec ‘scue.S,=‘nem www.maven-silicon.com 85 TS ceoal FPP a depaG qobeeayl) 77 olpoee wath anew) em Gee bepin Ye depsrttteoe) 7 wommy {-whthdaw (300)," new); fb % bundign od TAAVER, Constructor claw conmtorty® + $$ * Class objects are created with the new method (function) y2-0fi aloe te + Every class has a default constructor new method here * Constructor ~ new function + Returns the address of the memory [POINTER] to handle + _ Initializes all the properties (default/use defined values} ‘class account: int bal function new (inpur int open_bal = balance = opes_bel; endfunction :new 17 no return type endelass : eccount_e account_c ecnt_h = new www.maven-silicon com 86 Gl FaPKabes | a9 + Allocates memory aschadfeee Constructor eo EE Initialize a u . v ef nN the class properties in the constructor when the object is created [module testa; edule teat2y less transaction: cage Transaction: chis-dat = det; ase = 3; endfunction endfunction endcless endeless ‘Preasaction trans_h; initial initial, trans_h = new(); endacdule eadzodule bit [31:0] are, dst; RSs! 11201 wee, aoe 7 funetion new (int are, ine does) ; fumetion newt); shis.sre = are; // Disanbiguate ‘Transaction teans_h; trans h * pews); M1 dst ses default Wwww.maven-silicon.com 87 ! Null object handles d 7 u : vy EF bh _ Uninitialized object handles are set to null by default Uninitialized objects are detected by comparing the handle to null Accessing a property of an uninitialized object results in a runtime error. class account_er endcless : account_c secount_e acnt_h; if (ecnt_h — mul) acat_h = nes endtask : account_status task account_status (account_e acnt_h); www.maven-silicon.com 88Accessing Members int obj; class transection; prjsytifendetass | int data; asa sub h = new(); trans_n2 nodule test; tisnsaction trens_hi, trans_h2; trans hl = nev; teena_h2 ~ new trans h1;———— vans_n2 Secagiue ORE 1, Qacket 2 data mory _Www.maven-silicon.com 95 | Example - Shallow _ Account A Balance=Rs: 5000/- | Account B Account C linked to account A linked to account A B.A. Balance= B. A. Balance-2500; Sdisplay! “td”, B. A. Balance); Bdisplay( “%d”, C. A. Balance) www,maven-silicon.com 96Deep Copy ————————_E- Account A Balance=Rs: 5000/- Account A. Balance=Rs: 5000/- Account C linked to account A Account B linked to account A B .A. Balance= B. A. Balance-2500; “ Sdisplay( “%d”, B. A. Balance); Bdisplay( “sd”, c. A. Balance); 97 Deep Copy —_—_______mE- + Deep copy - Both data and objects in the parent class are copied ‘* User defined copy method should be used www.maven-silicon.com 98 ae ae ae ae ae a a a a ae a a “a aa aa 2Deep Copy - Example funetion aud apy (I copy Hews copy +ebj = this.obj; fendtunetion + copy endslaas :aub lars trans int dntaz sub sub_h t new dd; function transaction copy ( copy ~ now (1: copy-data = this-data; copy.sub_h * sub_h-copy; endfunotion ~: copy endolass : transaction module testy transaction trans hi, trans h2; vans_h1 aie | dta=4 objeS trans h2 dota ‘obj=10 www.maven-silicon.com MAY! TELE DW 99 Summary: Basic OOPS f T u ‘ v EF h EE * Class is an encapsulation of properties and methods. + Instance ofa class is called object. * Object is pointed by a handle. * Object is created by a class constructor new( ); + Handle assignment is just a handle copy but not a actual copy. + Shallow copy copies the properties but not the objects. + Deep copy copies both properties and objects. www. inaven-silicon.com 100NAVEN, silicon lig) De STL LEO NS Transaction Class —_—_—______=- Members: - Header - Payload - Parity Methods: - display_packet( ) calculate_parity() compare_packets() www.maven-silicon.com 102- — RAVER, OOP inheritance BIG Paster Seal Packer x Parent Class Packet \ \ \. www. maven-siliconcom 103 | Transaction Objects-Packets ~ °'''"°' _ ll - 10 Big Stimulus 1 Packets \ \ \ a www.maven-silicon.zom $04Testcases and TB Env ete oo www.maven-silicon.com 105 Inheritance RAVER, STLIC OM + Creating child classes (Derived Class] from parent class [Base Class} + Addnew Properties «Add new Methods + Change the behavior of exiting methods + Reusability — Existing classes from previous project + Accelerates verification + TB uses existing classes which have been used extensively and validated — Less Debug + TB methodologies -OVM, UVM, VMM + Base Class Library ~ Common code + Customization/Implementation - derived classes defined by user + New versions of TB components + Driver injects errors into DUV www.maven-silicon.comEMAVER, Inheritance _—_______.- + Adding properties into to an existing class class ©) Feg (51:0) sxe, dat, data(10741, exer | transaction i endelas: | sre |[ast data |[eze |; z —F—_— [elass bad_trensaction extends transaction; \ensenae SFT bad basection) « lenses | [bedere | www.maven-silicon.com 107 f t ¥ ‘ y Ef h Keyword: Super ——$$_—_—__ + The super keyword is used within a derived class to refer to overridden members of parent class as shown in this example: class account_c: Ant balence=0; // overriden by subclass balance property function int summary; return balence; class linked accoust extends account_c; int balance; // overrides parent cles function int summary ; // cleas method return belence + super-belance; endclass : linked sccount www.maven-silicon.com 108Cees Tet eo ND — + The super keyword is used within a derived class to refer to overridden members of parent class as shown in this example: Super.new class account_er int balance; module top; function new (int pay)? i balance-pay: Linked_account Lin_h; endfunction: new jf 2) IK 7 x class linked account mae account_c: Tan_e rman (S00rs function new (int Value! = Paeseante = dit_h endsootider vee endelass: Linked_account 109 www.maven-silicon.com Static Properties ——_——_———————_ mm + Class properties can be declared static. = Static property is common and shared across all objects or . , . . Te \SF = Static class properties can be used without creating an object ey class packet; generator gen(4]; geetic int 16 = ope foreach (gent it) Inc aid = 0 e gen[i} endfunet transaction tr_by transaction tr by initial _ begis initial creste(tr bl; begin Sdisplay("d" ee headde) ¢ create (teh); sed Scisplay ed", end www. maven-silicon.com 2nt c T s \ ie fh a ye the Overriding Methods vot Sacer ie fouh fax acces ve me tr od ———_E- + OOP Rule Any extended class object can be assigned to base class handle, vise-versa not possible ' + What happens when extended object is referenced by a base handle? transaction trans_hi bad_trans bad_h; ' trana_h ~ new() i bad_h = new(); ( class transactii task send| I prive endtask : send endclass : transaction [-——~ | trans_h-send(); class bad_trans exten tion} aah task send ()7 Geonschoaendth ( // Orives odd Parity. — endtak sed x cid eral an ace both AEH oF endclass : odd parity Gild methods ® Plepyhes- \ www.maven-silicon.com Fuvelion & tak intick ine clas by —— Faw Polymorphism _| D tehave parent aie * Virtual — lookup method at runtime, not compile { + The object’s type is used to find the right method = Automatic Methods - run time memory allocation class transaction; virtual task send(); meats . : transaction trans_h; 11 Drives Good a texans h = new(); endtask : send trans_h.send(); endclass : transection rest2 . txansaction trans_hs class bad trans extends transaction; bad trans bad hi 0 us i ' virtual task send();——] bad_h = new); // Drives Bad Parity [———__| txans_hm bad_h: endtask : send txans_h-send() ; encclass www.maven-silicon.com oNEnvironment/TB Infrastructure —_—_________»- TESTS (3 Package Environment| www.maven-silicon.com ANAVER STUIeUN) = Interface Mailbox 5 Testcases and TB Env UW Test! | endmodule www.maven-silicon.com c AVERPolymorphism —————_- Jendclass: ariver ] class base_c: Fonction ne(0ase_¢ basen): | virtual function votd send (7 ‘seng_aata(base | enstunet ion | 1/ prives even Parity | ondfunction + send virtual Function seng_data(base_c base_n) endelass : base_¢ base_hesend(); ~ ‘ensunction claaz ecl_c exterids base_cz virtual function void send()7 1/ vrixes odd Parity neath endfunction : snd T nextB0): endelaas : ecl_e Ox elass ec2_¢ extends base_cz oe mew(EC1): virtual function void send()s 1/ prixes odd Parity with doley endfunction : send endeless : 2c? smaveravepesigp son = 7 $cast + Scast - checks object type and copies + OOP Rule: Only extended class objects can be assigned to base class handle + Extended Class Objects can be assigned to another extended class handles + Scast— base class handle which is already having extended class object is assigned to another extended class handle ‘elaes Pransection? reg [31:0] are, dots virtual furetion void cale_exe(); ‘ondfunotion endelass : transaction class Bedtr extends transaction; bit bad_eres ‘reansection tr} tadts bt he b2} beh = neni; 1] Alceare extended object teh > bt he 1 Aasign to base handle te hecele cect); // Calculate CRC bah * exh W/ Error! Not allowed virnuel fumetion votd cats exe() Be teh); // allow sssige endelass = Bad_ex eib2_hy te BID /I Check f Legal www.maven-silicon.com -Virtual Classes STUIC ON Lprved wh by be Cetakd amy object KGk eh be ned Ty cele Mig bon rt * Create code that can be sha red across multiple projects Build testbenches that have a common look and feel ‘Two constructs that help build a shareable base class ,» off&C! Caaf) + Virtual Class — ean be extended but not instantised directly + Pure Virtual methods ~ prototype without a body + Aclass extended from virtual class can be in: virtual methods have bodies islantialed only if all + Pure virtual methods can be declared only in a fon Vivioad cleus we can! cAtale am abject « www. maven-silicon.com, ristes) clas packet; PAL (3120) arr{0:9); leah i pum virtual fanetten wold Gividar pht_one(}1 Network eo bans; packet by seal —_—— { banal ciepe trad oT ae tne) west Tova ented funehton veld°al thdee phu,one(y4 106 otenin packets it (1810) wer z (001)) visueal funotson vod divider pat, SHEN (OVemuper. wEELO) (150)5 HIG) [3500)) fo) eet, 11 HOlemuper arr{0 (1910) HO) (74016) mer As ieaypars are(O) (Gs orto) (M24); eitunttony divider yt-onn anstunertony dhvider prt ona andelaniy thi . andohanns 1904 we anaven-vilicon.com 120Parameterized Classes —_—_—_—_——____mnE-- s or data types * Generic class * Objects can be instantiated to have different array + Avoids writing similar code for each size or type * Allows a single specification to be used for objects that are fundamentally different and not interchangeable /Tvarenoterize » clase . olasn vector Hint azo ~ 1); 73 TO WKe af in Morhpl fle (edsevoy ay tT ‘ endetese nt? Clues Jo have. [Shan //instonces of thia clang can then be //inptontiated like modules or| interfaces: vector 1(10) vten; // objoct with vector of size 10 veator H(.#120(2)) viwo; // object with vector of nize 2 uypedef vector# (4) Vfour; // Clana with vector of nize 4 www.maven-gilicon.com 121 ANAVEN, STUICON- Parameterized Classes —_—————_ rm + Extended Class ned cli A parameteri can extend another parameterized class, For example: alana Hitype F = bit 17 Yann claan mnie olnne D1 A (type B= xeml) extend Cy 11% ha Whe (the dafautey Olnee O2 (type B= rem) oxtendn CA Gntayer) // da sategne inew 01 H(type 8 = rant) mxtanda CH) It ine ainae OF N(eype Bm Chem) wacenile By I) fon datnute 7 im cand www.maven-silicon.com, 122 =a & @&@ @ @® €£ & @ &@& a2 & 2 42 £ 2 =Se Sey ww owen ew ow wow ~w~ wo - Inheritance: If class is extended from parent class, it will - Polymorphism + Static properties consumes memory before the run time. - Static properties are shared by all the instances of the same - Virtual class is an abstract class with can not be - Pure virtual method is the method which doesn’t has - Using Scast, we can assign parent handle to child handle, —______s- inherit all properties as well as methods class. instantiated. implementation details. provided that child is previously assigned to parent. www.maven-silicon.com 123 c SILICON Random Stimulus _Constrained Randomization —————_ # SystemVerilog provides a new set of constructs for generating and constraining randoin variables + Random testing allows generation of many data sets with minimal code * Constraints restrict the data set to meaningful data + Random stimulus is very effective to capture design bugs Raver vovd bt (21 tas www.maven-silicon.com 125 ate f T ¥ t vi en Random Variables * Class variables can be declared eiaes Scinebctiony random with rand and randc rand bit (1:0) pktlength; rande bit [1:0] IPG? + rand - variable values uniformly distributed over their range ee : oR atv randc—random-cyclic variables /-y0 that cycle through all the values in” Gd tie # random permutation of their ows’ declared range = Each won't repeat until ail ¢ pitts ea Teluce heve been cycled ehroush haw an equal probebi sian ee 10 // vatie Ding ehoaen of 3/4 SE oe ee Le Arereaia 11 vase L__ 11 Sadie | www.maver-silicon.com 16 UIsRandomize() Method ame ‘ VER , * Class variables are randomized by calling the randomize() method Every class has a built-in randomize viral method (LRM 13.5.1) The randomize() virtual method cannot be overridden . www.maven-silicon.com 127 Pre/Post Randomize() sw. ca.» _ Every class has a built-in pre/post_randomize methods Pre/post_randomize are automatically called by randomize() function void pre randomize(); function void post_randomize(); * pre_randomize is called before objects are randomized * post_randomize is called after objects are randomized * pre/post_randomize can be overridden K when we all Rendonte, Gb wit call remdon, wake ISE prevamdomite 24 post Yan dewuke 74 called www. maven-silicon.com 128class transaction; rand bit [0:7] data; rand bit [0:1] chz function void post_randomizey int success; transaction trans_h = newQ); 1, success = trans_h. randomize (); end www.maven-silicon.com when we coll ROGET Sdisplay ("data is $b”, data); biel “he pre randeu}: Sdisplay (" Channel is %b”, ch); eed ceeds endfunction : post randomize ca aid oRp endclass : transaction tardoniine + initial begin 129 st Constraints in Classes * Constraints restrict the random data generation to meaningful values constraint constraint_identifier {constraint expression [constraint expression) ;) class transaction; rand bit [15:0] pktlength; sain for(int ind: i1é; i+) begia auccess * trans _h-randomize() ; Sdisplay (Pktléagth transaction ‘is %b*,teans hipktength) ; end www. maven-silicon.com be veh yi’ wher ¢ <6 10www wru'w w Ww ~~ ww werw.meven-silicon.com 5:G)pktlength: constraint oversize { phtlength >= 16’h££09, transection : endcloss + trans_ext trans_ext tex h ~ new: initial begio int puceann; nuccess ~ tex _h.randomi.2e()7 Sdimplay ("Fkilength for Groen in 4h”, vax hophtJength) ; ond www maven-silicon.com* Since rendomize finction is virtual, constraints 2 e tas virtual | = oanyidden wilt oppert) | | | | | _hopktlensth)s Ong mL Galant vax | swww.maven-silicon.com ae how a 2 ond hye se sew MF Op vals | chitd cvafde Me marl a> vip a 30: i % Biltsest rote (obi ele) 0 _ Ofhauase oe FRAVER, Set Membership Ds —_—_7E * Constraints support integer value sets and the set membership operator = & Yoo woot constraint constraint_identifier [variable inside {set of legal values} ;) ‘class transaction; rand bit [3:0] addz; oo constraint ade {addr inside (3, 77 Qi endeless : transaction transaction trans_h = new; initial begin int success; muccess = trans_h. randomize (); Sdisplay ("Address is $d", trans_h. dade): end www.maven-silicon.comDistribution Constraints —_— ot weighted values * Operator = assigns weight to the item; ia range, assigns weight to every value in the range ¢ Constrai 'S Support s [101:200) := 200// cach item (101, 102, etc) gets a weight of 200 + Operator :/ assigns weight to the item; if a ran range as a whole [101:200):/ Be, assigns weight to 200 //each item (101, 102, etc) gets a weight of 2 1 (200/100=2) alte, Q + Default weight is 1 Toe a const: constraint identifier [reriable dist (sot of legal values and weights) ;) www.maven-silicon.com 135 Voainte — kendke fs Sn Fo) 4 (ei) ewe, > 5. (11:20):83, (26:30) [elass transaction; rand int Vlantag constraint tag ( Vlentag dist (7 endela: + transaction trassaction trans_h = ne initial begin int success; guccoas ~ trans_h.random{ te () ;—scuenm Sdisploy ("ag Es 4d", trans h.viantag) endRAVER, STL Conditional Constraint * Constraints provide constructs for declaring conditional relations = implication (>) constraint constraint identifier (expression) ->{constraint set} ;} ~ iffelse constraint consiceint_ideatifier (f (expression) (constraint set [else constrain: set)};] Glans trnnsactions Fand ine Viantag: BL moda; Sonatraint tag inode—t*ht -> viantagése, nod “> Viantag>i24a;) endclana + transaction transaction trane_h = ne inivind snicia begin boain + trans hs emndontze 0) Sdisplay (™ 2 h-Viantag) Seenaahevhannil www.maven-silicon.com 8? 4 Leth “The cathon me ae ed Than Ihe ctl coin whl wat Inline Constraints. randomize() with is used to introduce an additional constraint that x < y The randomize() with construct can be used anywhere an expression can appear class inline; rand bit [7:0] x, y, 27 constraint c {z= x + y;} endolass : inline module test; inline inh = ne initials dads Aon eaten a rt(in_h. Seaeatea se) with (x < y;}) endmodule : test www.maven-silicon.com 138 SHR couthrte sptve Pobwa caadoade. aylan hay[s a e | \Fam gf 3] E E Z yy me Lm : i mie ral tty | Threads B89 AB tm Bon Cn Cn C00 Bin Bi OOO mmmfork /join | join_none | join_any create threads disable /abe/; terminate just the named block disable fork; terminate all child threads below the current context level Note~- may stop more threads than you wanted! + Wait fork — Waits until all the fork processes are complete www.maven-silicon.com 141 vu * ¥ EF b Threads — Fork Join ——_—___—_—_____- sedate test(); initial begin Sdisplay( pat : PT starts™, stine) ANG Sdisplay(“@OR: FF vith delay #10", stixel; fork: thread isplay("@Ret: CT vith delay 458°, Stine): Ae Séisplay(“BSt: C2 vith delay #18", stipe): begit BA sbisplayl"@wt: C13 with delay £32", stase); mary ‘ME Sdisplay("@xot: (13 witt delay #19", stise); geod ea moe ont ms Ly join oe ee eee Sdisplay("evst: PT resumes”, Stine) 08 Sdisplay("@8t: FT with delay 220°, stine) end Cercle es Pacer ere sc Papeete es 860: PT resuzes teins Ctraaee toe wwwmaven-silicon.com Ue— —_ Cree t Cee N Threads - Fork Join_any wodule! testi: initial bevir Séjsolayl"@ex : PT starts™, Stine}: AID Sdisplay(“eRet: PT with delay €16°, tine): Fork: thread #58 Sdisplay(“eise: CTI with delay #56", Stine); Sdisplay(“@@t: C12 with delay #10"! Stine); § cheeky fe fowest Time period tnalde ne fox join begis E Sdisplayl"Evot: CTS with delay 430°, stize); | Ae Sdispley("@vet: C73 with delay #18", Stine) ext jetn_any 11 disable thread; Retest) ee ete sdisplay(“@wt: PT resuses", stize): EB Sdisplayt “erat: PT vith’ delay #3 end + Stibe) with delay. Prose ae ere tie sen | www.maven-silicon.com 143 ! Threads — Fork Join_none ——_——__=- eofale testi): initial begin © stisteyveat : PT starts", stine): 40 she Sdisplay{"@uet: PI vith delay sie". tise); ferk: thread GS 658 Sisplay(“Exst: CT) with delay #56", stize): SP Me seisslay(-east: C72 with delay 6", Stine); begin WO He sdisplay(-eet: (13 vith delay #1 SOM sAisplay("GMt: C13 vith delay # ed stive); stise); Sola nose ey 1/1 disable thread; Pam eC) 60 shislaytteut: PT resuees", stiel: Ses yO sho sdisplay("@ret: PT vith delay 68°, stined CT2 with delay #10 et emer ie stg emer sete) endootute 7 re ern) ———____——_ a Baer see www.maven-silicon.com 144+ Features Lk pvea a = FIFO with no size limit gev/pul are atomic operations, no possible race conditionsa = Can suspend 2 process ue @ + Default mailbox has no fata type + Exchange messages / objects between two threads eilbox #( transection } abx; 77 declece « zailbox Pok ble 4® U/ alceate mailbox - Object = Gah 7 // put teaniAction into mailbox I get teansection end renove 1/ Won-blocking version 1/-get trans h but don’t renove ~ blocking 1/ Noo-blecking version count = abz.nun(); how” Man 1/ Mwsber of transactions’ in railbox dag Ta OST Y iy maven-silicon.com 145 x blocking wre tiody Mailbox - Method | www.maven-silicon.com ARAMER 146wow www we ww ww ewww Mailbox — Method II mabox mbx0 = new(); mbxO en.mbx! maiibox mbx = new(); mbx www.maven-silicon.com 147 Mailbox Example fF ¥ ‘ ¥ ef b {, “mailbox # (teansaction! fork [class generator: function new. (ant this -gen2drvnyen2dey: fndfuncrion : se clara drivers mailbox # (ere Function new (anilbox # (transaction) gentdrel ; this -geatdevgen2dev: cask scare: fork repeat (10) begin [-P aen2dzv- gee (erans_h); Rposedge dari f.eb-en)s // orive the stinulus 1 driver silicon.com 148A, Ces rere oN Semaphore > ‘yachonse the ruvady ax worn, with We centeph af you Used for mutual exclusion and synchronization. + Features - « Variable number of keys can be put and removed Applicabise! « Controlled access to a shared object, such as sharing a bus from models ‘semaphore sem; sem ~ new(optional_initial_keycount ~ 0)7 sem.get (optional_num_keys = 1), sem.put (optional _num_keys ~ 1)7 www.maven-silicon.com 149 Semaphore - Example module autoatic tests ‘driver dz(2) i Semaphore sem; lass driver task send); | sen. get bus bus-ch.addr < teaddr; bus-ch.kind < t.bied: bur-ch-clata G t-data; fem new (1)? fork dr [0] -2end (07 de [1} send (0 em. put (1) join one endtask a jendelass, ondnodle www.maven-silicon.comstereo Communication - Events \ So Synchronize concurrent threads + Features + Synchronize parallel threads + Sync blocks process execution until event is triggered + Events connect triggers and syncs + Can be passed into tasks event ev; 11 Declare event > er; U1 Trigger an event tee: 71 Block process, wait for future event g wait (ev-eriggezed) deiver = newier); (/ vase event into task www.maven-silicon.com 151 | Summary ; ————_—_- 1. There are 3 types of threads available: fork / join | join_none | join_any . 2. Mailbox is a inbuilt parameterized class used for communication between components. 3. Mail box consists of blocking and non blocking methods: Blocking: get, put, peek. Non Blocking: try_get, try_put, try_peek. 4. Semaphore is a in built class used for mutual exciusion and synchronization. 5. Events are used for synchronization of different threads, www. maven-silicon.com 182interface Mailbox i 154 www.maven-silicon.comANAVER Sheted Communication - Events . —$_$___ Synchronize concurrent threads * Features + Synchronize parallel threads + Syne blocks process execution until event is triggered + Events connect triggers and syncs + Can be passed into tasks event av 11 Declare event > av V7 teiganr an ovent fev; 1 Mock procenn, wait for future event wait for avent, wit (evitriggered): —// Mock prow M1 including thin tineelo/ R : oe fo? 1 wndsonn ren conditions driver = newter) 1 11 Yann event into tm www.maven-silicon.com 151 1. There are 3 types of threads available: fork / join | join_none | join_any . 2. Mailbox is a inbuilt parameterized class used for communi between components, 3, Mail box consists of blocking and non blocking methods: Blocking: get, put, peek, Non Blocking: try_get, try_put, try_peek. 4, Semaphore is a in built class used for mutual exclusion and synchronization, 5. Events are used for synchronization of different threads, tion Www. nuiven-silicon.com 152ANA uo a ° oO 2m Building Env Components 5 cap Mailbox www maven-silicon.com isclass test; task mn_and build(); Implementation Structure sruveen eo begin TESTCASE www.maven-silicon.com 155 Transaction Class . logic [63:0] dete_out; static int trans_id; Continued...... www.maven-silicon.com 156FRAVER, Transaction Class function void display(seput string messege) ; Sisplay(*————— Sdisplay("%=" message); Sdisplay("\cFrarsaction Xo. Sisplay("\sRead Prarseccion ¥: tread t Sisplay("\tirite Prensaccion Yo. $d", no_of write trans); Séisplay! fo. 34%, o_of_RA_traas) ; Sisplay( "eRe Sdisplay("\thead tdaress=t ¥ dtd address, we_address}; Sdisplay(*\tbata=td" Sisplay("\tbeta_cot Sisplay "== ‘endfunction: display www.maven-silicon.com 57 | f t YW ‘ ¥ EF b Transaction Class Row 0 0 Pb © 1 owl {9 shad {1 DRw function void post_randomize (); Af(this.read==1 && this.write—0) no_of_read_trans*+; i£(this.write==1 && this-read—0) no_of_write_trans++; Af (this.read—1 && this.write—=1) no_of_RW_trans++; this-display("\tRANDOMIZED DATA"); endfunction:post_randomize Continued... Wwww.maven-silicon.com 138cries Ws evcutpet string weasege) d_address) megaagen" succEEsRny CoMFARES"; Feturn(i): ‘www.maven-silicon.com AF STL fe 159 C STI C oN _ Generator -CON Environment/TB Infrastructure . 161 - www.maven-silicon.com AMER Ram TB Generator Class rreianhe - vitend by [class ram_gen; ram_trans gen_trans; ram_trans data2send: mailbox #(ram_crans) gen2xd; mailbox #(ram_trans) gen2wr; function new(mailbox (ram_trans) gen2xd, mailbox #(ram_trans) gen2wr); this. gen2rd=gen2rd; this. gen2wrsgen2wr; this.gen_trans=new; endfunction:new www.maven-silicon.com \62ewe we we we PAAVE! Ram TB Generator Class FRANER ’ oe virtual task start(); fork begin for(int i-€; i-hing rd_non_eb) > endinterface: ram if www.maven-silicon.com 71 Sse ent class ram_env; wr_bfm > now(wr_if.gen2we); dbf = new(rd if, gen2rd); ;pon * nem (wrmon_i f,mr2aa) rd_pop © new(rdmoo_if,xd2em, rd20b) ; endelass : rom ene www. maven-silicon.com 172