Rashtreeya Sikshana Samithi Trust
RV Institute of Technology and Management ®
(Affiliated to VTU, Belagavi)
JP Nagar, Bengaluru – 560076
Department of Computer Science and Engineering
Course Name: Digital Design and Computer Organization / DDCO
Course Code: BCS302 / IPCC
III Semester
2022 Scheme
Prepared By:
Dr. Malini M Patil Professor & HOD
Department of Computer Science and Engineering,RVITM,
Bengaluru – 560076
malinimp.rvitm@rvei.edu.in
Mrs. Padmasree .N Assistant Professor,
Department of Computer Science and Engineering,RVITM,
Bengaluru – 560076
padmasree.rvitm@rvei.edu.in
Mrs. Rashmi Uppin Assistant Professor,
Department of Computer Science and Engineering,RVITM,
Bengaluru – 560076
uppinrashmi.rvitm@rvei.edu.in
Mr. Santhosh Kumar K.P Programmer,
Department of Computer Science and Engineering,RVITM,
Bengaluru – 560076
santhoshkumarkp.rvitm@rvei.edu.in
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Study of All DIGITAL LOGIC Gates (Basic, Universal & Special Function Gates) and its pinout diagram
Study of All Basic Gates and its pinout diagram
IC 7404 – NOT GATE
IC 7408 – AND GATE
IC 7432 – OR GATE
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 2 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Study of All Universal Gates and its pinout diagram
IC 7402 – NOR GATE
IC 7400 – NAND GATE (2-Inputs NAND)
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 3 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Study of All Special Function Gates and its pinout diagram
IC 7486 – ExOR GATE
IC 74266 - ExNOR GATE
Implementation of ExOR Gate using Basic Gates
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 4 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Simulation packages preferred: Multisim, Modelsim, PSpice software or any other relevant
In our Laboratory we use XILINX ISE Design Suite 14.7 Simulation package
Digital Design with XLINX Software (VHDL/Verilog)
Steps to run vhdl codein XILINX ISE Design Suite 14.7software
Step-1: Right click on the ISE Design Suite14.7 icon again click on Run as Administrator
Step-2: Go to File menu and select new project.
Then the following window will appear,
Now we have to give a valid filename in the path “C:\Xilinx\14.7”.
For example: all_gates_VHDL
Top-level source type: should be HDL
After Filling File / Project name & selecting HDL click on Next >
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 5 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Step-3: After step-2 the following window will open which is Project Settings Wizard
For Sample Program For Syllabus Program
Family: Spartan3E Family: Spartan3E
Device: XC3S100E Device: XC3S100E
Preferred Language: VHDL Preferred Language: Verilog
Click on Next > Click on Next >
Step-4: The following window will open. It displays the “Project Summary” before clicking on Finish
ensure all the selected details are proper and click on Finish
step-5: Later the following window will open.
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 6 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
In the above window you will see your project name in the left corner of the window. Right click on that as
follows and click on the New Source option. Now the window will open
Select VHDL Module. Give the same file name all_gates_VHDL which given initally and click on Next button.
Step-6: The Define Module window will open, Fill the Names of the Inputs, Outputs with its directions as in/out
Here you set your behavioral model according to your project and click on the next button
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 7 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Now the following Summary window will open check the name of the I/P, O/P and Port Directions
Step-7: Click on Finish (widow will open for VHDL Coding) Type your program and save it (Cntrl + S)
Hands on Work / Sample Program for ALL LOGIC GATES in the next page
The VHDL / Verilog Code Consists of 3-Steps of Modelling
Gate Level Modeling (Name of I/P & O/P)
Data Level Modeling (Logic to written how Data should flow to OUTPUT )
Behavioral Modeling (How the Logic Gate Level should behave)
Note: If the Coding is in VHDL use the KEYWORDS in Behavioral Modeling part
If the Coding is in Verilog use the ASSIGNMENT OPERATORS in Behavioral Modeling part
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 8 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Hands on Work / Sample Program for ALL LOGIC GATES
VHDL Code for ALL (Basic, Universal & Special Function) LOGIC GATES
KEY WORDS OF Logical Operators Port Name: A,B Port Name: Y,Y_OR, Y_AND
NOT, OR, AND (Basic Gates) Direction: in Y_NOR, Y_NAND
NOR, NAND (Universal Gates) Y_ExOR, Y_ExNOR
XOR, XNOR (Special Function Gates) Direction: out
--VHDL code for ALL LOGIC GATES
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity all_gates_VHDL is
Port ( A,B : in STD_LOGIC;
Y,Y_OR, Y_AND : out STD_LOGIC;
Y_NOR, Y_NAND : out STD_LOGIC;
Y_ExOR, Y_ExNOR : out STD_LOGIC);
end all_gates_VHDL;
architecture Behavioral of all_gates_VHDL is
begin
Y <= NOT A; --Basic BITWISE NOT GATE Operation for A Input
Y_OR <= A OR B; --Basic BITWISE OR GATE Operation for 2-Input's A & B
Y_AND <= A AND B; --Basic BITWISE AND GATE Operation for 2-Input's A & B
Y_NOR <= A NOR B; --Universal BITWISE NOR GATE Operation for 2-Input's A & B
Y_NAND <= A NAND B; --Universal BITWISE NAND GATE Operation for 2-Input's A & B
Y_ExOR <= A XOR B; --Special Function BITWISE ExOR GATE Operation for 2-Input's A & B
--ExOR <= (((NOT A) AND B) OR (A AND (NOT B)));
Y_ExNOR <= A XNOR B; --Special Function BITWISE ExNOR GATE Operation for 2-Input's A & B
--ExNOR <= ((NOT A) AND (NOT B)) OR (A AND B);
end Behavioral;
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 9 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
OUTPUT: Simulated Waveform / Timing Diagram of ALL LOGIC GATES
View of RTL Schematic View of Technology Schematic
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 10 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Hands on Work / Sample Program for ALL LOGIC GATES
Verilog Code for ALL (Basic, Universal & Special Function) LOGIC GATES
ASSIGNMENT OPERATORS OF Logical Function Port Name: Port Name:
~ (Bitwise NOT) A,B NOT,OR, AND
& (Bitwise AND) Direction: NOR, NAND
in ExOR, ExNOR
| (Bitwise OR)
Direction: out
^ (Bitwise XOR)
~^ (Bitwise XNOR)
// Verilog code for ALL LOGIC GATES wire OR;
wire AND;
`timescale 1ns / 1ps wire NOR;
module all_gates_Verilog( wire NAND;
input A,B, wire ExOR;
wire ExNOR;
output NOT,OR, AND,
output NOR, NAND,
// Instantiate the Unit Under Test (UUT)
output ExOR, ExNOR all_gates_Verilog uut (
); .A(A),
.B(B),
assign NOT = ~A; // .NOT(NOT),
assign OR = A | B; .OR(OR),
assign AND = A & B; .AND(AND),
.NOR(NOR),
assign NOR = ~(A | B); .NAND(NAND),
assign NAND = ~(A & B); .ExOR(ExOR),
.ExNOR(ExNOR)
);
assign ExOR = A ^ B;
assign ExNOR = ~(A ^ B); initial begin
endmodule // Initialize Inputs
---------------------------------------------------------- #000; B = 0; A = 0;
// Testbench code for ALL LOGIC GATES #100; B = 0; A = 1;
#100; B = 1; A = 0;
`timescale 1ns / 1ps #100; B = 1; A = 1;
module all_gates_tb; // Wait 100 ns for global reset to
finish
// Inputs //#100;
reg A; // Add stimulus here
reg B; end
// Outputs endmodule
wire NOT;
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 11 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
OUTPUT: Simulated Waveform / Timing Diagram of ALL LOGIC GATES
View of RTL Schematic View of Technology Schematic
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 12 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Once you saved your typed program follow the below steps check for the errors in your code
Under the Design The View should be in Implementation
Under No Processes Running window Drop Down the Synthesize - XST
Double click on the check syntax option.
If there is are errors it will display the following message
The Code should be error free Clear the errors to proceed towards SIMULATION
“Process "Check Syntax" completed successfully”
If No errors are there in the program The WARNINGS/ERROR window will be blank and the Check Syntax will
be highlighted in the GREEN TRUEMARK as shown below
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 13 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
Step8: Now we have simulate by choosing the simulate option as follows
Do Single Click / Select your Project under Design Hierarchy all_gates
In No Processes Running Window DOUBLE CLICK on Simulate Behavioral Model
Now the following window (Waveform Window) will open separately
Under Objects Object Name Right Click on the INPUT - A
click on Force Constant as per the TRUTH TABLE
again do the same for other INPUT - B
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 14 |32
(BCS302)
RV Institute of Technology & Management®
Department of Computer Science & Engineering
click on Force Constant as per the TRUTH TABLE
You can enforce the value for A & B as shown below
Place your cursor inside the Force to Value: Fill the 0/1 as per your truth table
You can enforce the value for A & B as shown below
Click on Apply and OK
TRUTH TABLE of ALL GATES
INPUTS OUTPUT
B A Y
0 0
0 1
1 0
1 1
After filling the values for INPUTS with every combination click on the RUN icon shown below
Once run the simulation for all the possible INPUTS as per the TRUTH TABLE click on below icon to see
all the combinations of waveforms next to next on the same window.
The Final OUTPUT waveform window will be like this Verify it with OUTPUT of the TRUTH TABLE
Binary -0 will be like this LOW FALLEN WAVE
Binary -1 will be like this HIGH RISE WAVE
INPUT’S: A & B are High Lighted in different colors (Default is Green Colour)
III-Semester, Digital Design & Computer Organization-DDCO Lab / IPCC P a g e 15 |32
(BCS302)
