DPCO

Unit 01
Part A
1. Define Combinational and Sequential Circuit
2. Define 1’s and 2’s Complement with example
3. Define Multiplexer. Draw the logic diagram for 2 to 1 MUX
4. Define Encoder
5. Construct Half adder and full adder circuit
6. Evaluate Logic circuit of 2 bit comparator
7. List the four possible elementary operations simple binary addition consists of.
8. Write down the sum and carry expression for half adder & full adder
9. How many selection inputs ,data inputs and output for 16X1 MUX
10.Define HDL
Part B
1.a)Discuss about adder and subtractor with neat diagram
b) Present the graphic symbol,algebraic expression and truth table for the digital logic gates:
AND,OR,Invertor,Buffer,NAND,NOR,Exclusive OR & Exclusive NOR
2.i) Illustrate the following Boolean function in Karnaugh map and simplify it f(w,x,y,z)
=∑m(0,1,2,4,5,6,8,9,12,13,14)
ii) Specify the following using multiplexer: F(A,B,C,D) = ∑ (0,1,5,6,8,10,12,15)
3 a) Explain about the decoders. Design 3 to 8 line decoder with necessary inverters & AND gates or Binary
to Octal decoder
b) Write about Demultiplexer
4.i) Discuss about the BCD to Decimal Decoder?
ii) Discuss the magnitude comparator with three outputs A>B,A=B,A<B?
5.a)Decimal adder or BCD adder [ Unit 01 Page 17 ]
b)Analysis and Design Procedures
c) Encoder or Octal to binary encoder
Part C
Unit 01
 Design full adder using two half adder [ Unit 01 Page :05]
 Simplify the function using multiplexer f= ∑(0,1,3,4,8,9,15)
 Demonstrate 4 bit magnitude comparator with three output A>B,A=B,A<B [ Unit 01 Page :16,17]
 Build a 4 bit priority encoder using gates [ Unit 01 Page :37]
 Implement the following Boolean function using 8X1 multiplexer. Considering D as the input & A,B,C as
selection lines f(A,B,C,D)=AB’+BD+B’CD’
 Using K-Map ,Find the Sum of Products & Product of Sums for the given function
F=∑(0,2,6,78,10,12,14,15)
Unit 02
Part A
1. What is flip-flop? What is edge triggered flip flop?
2. What is a state diagram?
3. Write the difference between combinational and sequential circuits
4. Mention the different types of shift registers.
5. Difference between latch & flip flop
6. Give the excitation tables of JK flip flop
7. Difference between synchronous sequential circuit & asynchronous sequential circuit
8. What is shift register? List its types
9. How many flip flops are required for designing BCD counter? Justify
10. Define Counters? Write the types

Part B
1. Describe the types of flip flop with the operation ,excitation tables and Triggering of FF or Latches state
diagram & characteristic equation of T,D,JK ,SR filp flop
2.(i)Explain Moore and Mealy models with the help of block diagram
(ii) Explain the Design and Analysis of clocked sequential circuit
3. Describe in detail about shift registers and its types? Or 4 bit shift register
4. Explain in detail about counters and its types?
5. a)state minimization, state assignment, circuit implementation
b) Flip flop conversion [ Unit 02 Page 03 ]
Part C
Unit 02
 Realize D flip flop using SR Flip flop
 Construct a 4 bit down counter using logic gates
  a) What is an SR Latch? Outline the design of SR latch using NOR gates. Also present the function table
for the same.
b) Outline the design of a D flip flop with two D latches and an inverter with a diagram
 Design a Mod - 7 Synchronous counter using JK flip flop
 BCD ripple counter using JK FF
Unit 03
Part A
1. Draw the Functional Units of a Digital Computer [8 Mark]
2. What is meant by ISA?
3. Define assembler, Compiler and interpreter
4. Define program counter.
5. Draw the stock diagram for Von Neumann Architecture
6. Define addressing mode. Write its types
7. What are data transfer instructions
8. Outline instruction cycle with a diagram
9. Define ISA
10. Draw the types of instruction
Part B
1. i) Explain about Von Neumann Architecture with neat diagram
ii) Explain about operations operands of computer hardware instruction in detail
2. a)Explain about Instruction Set Architecture in detail
3. Explain the following
i) Instruction and Instruction Sequencing & branching
ii) Addressing Modes & its types
4.Explain the following
i) Encoding of Machine Instruction or Encoding assembly language & types of instruction
ii)Interaction between Assembly and High Level Language
5.a)Instruction Execution
b)Memory Management
c)Instruction cycle Unit 03-Page 32 [ Question No:30]
Unit 04
Part A
1.List the stages of instruction execution.
2. Define pipelining. Write the types &advantages of pipelining
3. Define Data hazards and Control hazards
4.Define hazards and its types
5. Define cache memory or Why we need cache memory
6. Which signal is used to notify the processor that the transfer is completed. Define
7. When do hazard occur in pipelining
8. Define Hardwired Control & Micro programmed Control
9. Define essential hazard
10.Which signal is used to notify the processor that the transfer is completed
Part B
1.a)Illustrate the concept of Hardwired Control and Micro programmed Control with neat sketch
b)Explain in detail about how a control unit and the state functions performed by a control unit.
2.Explain in detail about pipelining. Give examples
3.Illustrate the concepts of data hazards and control hazards with examples or Pipeline hazards & types
4.Building a Data Path or how instruction is being fetched and executed through the data path in the processor
5. What is hazard? Give hazard free realization for the following Boolean function F(A,B,C,D)= ∑(1,5,6,7) using
AND-OR gate network.
Unit 05
Part A
1. Define hit rate, hit time,miss rate and miss penality
2. Define USB and SATA
3. What is memory hierarchy?
4. Define DMA
5. What is a direct- Mapped cache
6. Differentiate write back & write through
7. Define virtual address & Physical address
8. Address translation
9. Segmentation & Page table
10. Swap space & Page Fault
Part B
1.Explain about Interrupt driven I/O with necessary diagram
2.a)Illustrate the concept of interconnection of standard USB and SATA in detail.
b) Cache Replacement Techniques
3.Explain about the following i) DMA ii) Virtual Memory
4. Explain the various Memory mapping techniques associated with cache memories.
5. I/O – Accessing I/O: Parallel and Serial Interface
6. How virtual addresses are translated into physical addresses? Explain with the help of virtual memory
organization and page translation. Or Outline virtual address, physical address, address translation,
segmentation, page table, swap space & page fault.
Cache level Diagram

Virtual Memory

Storage views
Segmentation
A Segment is a logically related contiguous allocation of words in MM.

Example of allotted Segments in Main Memory

Address Translation in Segmentation Mechanism
Paging

Virtual Memory Pages to MM Page Frame Mapping

Virtual Memory Address Translation in Paging Implementation

Translation Look-aside Buffer (TLB)

Address Translation sequence in a Multilevel Memory with TLB

Address Translation verification sequence starts from the lowest level i.e.
TLB -> Segment / Page Table Level 1 -> Segment / Page Table Level n
Once the address is translated into a physical address, then the data is serviced to CPU. Three possibilities exist
depending on where the data is.
Case 1 - TLB or PT hit and also Cache Hit - Data returned from CPU to Cache
Case 2 - TLB or PT hit and Cache Miss - Data returned from MM to CPU and Cache
Case 3 - Page Fault - Data from disk loaded into a segment / page frame in MM; MM returns data to CPU and
Cache
Advantages
 Generality
 Storage management
 Protection Flexibility
 Storage efficiency
 Concurrent I/O
 Expandability

Logic Gates –AND,OR,NOT,NAND,NOR,XOR,XNOR