1.

LINEAR WAVE SHAPING

1(a) HIGH PASS RC CIRCUIT

Aim: 1. Design a High pass RC circuit for a given cutoff frequency.

2. Verify the condition for which the High pass circuit acts as a differentiator.
3. Measure % of tilt for the designed 3 Time constants.
Apparatus: i) C.R.O ii) Function Generator iii) Resistance box

iv) Capacitance box. v) Single stand wires vi) Bread board

Design: fl = 1 / (2RC),  = RC

Circuit Diagram: By fixing R, Calculate C

Procedure:

1. Connect
C the circuit as shown in Fig.

2. Apply sine wave 5v p-p and take

the frequency response from 0 Hz upto
100 KHz. And R
Vin Vo
draw The graph - Gain (db) vs
Frequency and find f1(lower 3 db
frequency ).

3. Using a signal generator apply

square wave 5v p-p 3 KHz with time
periods  = T,  =

T/20 and  = 20T Note the output wave form for the above mentioned time periods.

4. Calculate the % tilt of the out put waveforms and verify with the theoretical values.

Observations:

Frequency response:
 Vi =

S.No. FREQUENCY(Hz) Vo Av = Vo/ Vi =20 log(Vo / Vi) db

1. 0

2. 10

3. 50

4. 100

5. 200

6. .

. .

. .

. 100KHz

Graph:

Output waveforms:
Result:

Theoretical and experimental values are verified from the response of the HPRC Circuit.

Exercises:

1. Design a differentiator circuit to differentiate 5 KHz square wave signal.

2. Design a HPRC circuit for a tilt of 5%.

3. What is the condition for the high pass circuit to act as a differentiator.

1. LINEAR WAVE SHAPING

1(b) LOW PASS RC CIRCUIT

Aim: 1. Design a Low pass RC circuit for a given cutoff frequency.

 2. Verify the condition for which the lowpass circuit acts as an
integrator.
3. Measure rise time of the design circuit for the long time constant.
Apparatus: i) C.R.O ii) Function Generator

iii) Resistance box iv) Capacitance box.

Design: fu = 1 / (2RC), Time constant () = RC

Circuit Diagram: By fixing R, Calculate C

Procedure:

1. Connect the
R circuit as shown in Fig.

2. Apply sine wave 5v p-p and take the

frequency response upto 100 kHz.
And draw the Vin C Vo
graph - Gain (db) Vs Frequency.

3. Apply a square wave of 5v p-p, 1

KHz with time periods = T, = T/20 and
 = 20T. Draw

the output waveforms for the three time constants.

4. Calculate the rise time for  = 20T and verify with the theoretical value.

5. What is the condition for the low pass circuit to act as an integrator.

Observations:

Frequency Response: Vi =

SNo. FREQUENCY(Hz) Vo Av = VO / Vi = 20 log(VO / Vi) db

1. 0
 2. 10

3. 50

4. 100

5. 200

6. .

. .

. .

. 100KHz

Graph:

Output waveforms:
Result:

Theoretical and Experimental values are verified from the out put waveforms.

Exercises:

1. Verify that whether the DC level is maintained or not.

2. Design an integrator for 2.5 KHz,5v p-p square wave.

3. Design an integrator circuit to get the rise time Tr = 35 msec.

 2. NON LINEAR WAVE SHAPING – CLIPPER CIRCUITS

Aim: To study various Clipper circuits and also observe transfer characteristics

Apparatus: i) C.R.O ii) Function Generator

iii) Resistance box iv) Capacitance box

Circuit Diagram:

Theoretical calculations:

Positive peak clipper with reference voltage, V=2V Positive peak clipper:

Vr=2v, Vγ=0.6v

When the diode is forward biased Vo =Vr+ Vγ

=2v+0.6v

= 2.6v

When the diode is reverse biased the Vo=Vi

Positive Base Clipper with Reference Voltage, Positive base clipper:

Vr=2v, Vγ=0.6v

When the diode is forward biased Vo=Vr –Vγ

= 2v-0.6v

= 1.4v

When the diode is reverse biased Vo=Vi .

Negative Base Clipper with Reference Voltage,V=-2V

Negative base clipper

Vr=2v, Vγ=0.6v

When the diode is forward biased Vo = -Vr+ Vγ

 =-2v+0.6v

=-1.4v

When the diode is reverse biased Vo=Vi .

Negative peak clipper with reference voltage, V=-2v Negative peak clipper:

Vr=2v, Vγ=0.6v

When the diode is forward biased Vo= -(Vr+ Vγ)

= -(2+0.6)v

=-2.6v

When the diode is reverse biased Vo=Vi .

Slicer Circuit: Slicer:

When the diode D1 is forward biased and D2 is

reverse biased Vo= Vr+ Vγ

=2.6v

When the diode D2 is forward biased and D2 is

reverse biased Vo=-(Vr+ Vγ)

= -(2+0.6)v

= -2.6v

When the diodes D1 &D2 are reverse biased Vo=Vi .

Procedure:

1. Connect input signal in one channel and output signal to other channel of CRO. Adjust both the
channel of CRO to ground position. Put them to DC position.

2. Give a sine wave input (Vi) of amplitude 10Vp-p at a frequency of 1KHz.

3. R = [Rf R f ]1/2 Rf = 100 ohms ; Rr = 50K ohms. R must be chosen a value of 1k ohm
 Observe output waveforms.

4. Press XYmode (i.e. Disconnecting the Time base from X–plates)&Observe transfer Characteristics.

Model wave forms and Transfer characteristics

Positive peak clipper: Reference voltage= 2V

Positive base clipper: Reference voltage= 2V

Negative base clipper: Reference voltage= 2v

Negative peak clipper: Reference voltage= 2 V

Slicer Circuit:
Result: Transfer characteristics of various clipper circuits are verified.

Exercises:

1. Verify that two way clipper of Fig 5 as a sine wave to square wave Converter if the input is

Triangular wave.

2. Design clipper circuits for the given Transfer characteristics.

Vo

3 Vi
-3
 3. NON LINEAR WAVE SHAPING – CLAMPER
CIRCUITS
Aim: To Study various biased and unbiased clamper circuits & verify the clamping Circuit
theorem.

Apparatus: i) C.R.O ii) Function Generator

iii) Resistance box iv) Capacitance box

CIRCUIT DIAGRAM:

Positive peak clamping to 0V:

Positive peak clamping to Vr=2v

Negative peak clamping to Vr=0v

Negative peak clamping to Vr= -2v

Procedure:

1. Connect input signal to channel 1 and output signal to other channel of CRO. Adjust both the

channel of CRO to ground position. Put them to DC position.

2. Give a square wave input of amplitude 10Vp-p at a frequency of 1KHz. Observe the clamped

output waveforms and draw the graphs.

RESULT: DC level is restored in each case.

EXERCISES:

1.Design clamper circuit which can satisfy the clamping circuit theorem.

4. TWO STAGE RC COUPLED AMPLIFIER

AIM: Design Two stage RC coupled Amplifier with the given parameters, and obtain the

frequency response of the amplifier.

APPARATUS: CRO, Function Generator, Decade resistance Box. Resistors, Capacitors,

Tr BC107, Bread board, Connecting wires.

CIRCUIT DIAGRAM:

Vcc = 12v

51kohm 2.2kohm
51kohm 2.2kohm 10uF
10uF

BC107BP
BC107BP

1kohm 10uF Vo
20kohm 10uF1kohm
1kohm 1kohm
DESIGN:

Given Av2, Av1, fL , Ic1, Ic2, Vcc, hfe1, hfe2.

RC1 = (VCC – VCE – Ve) / IC1

RC2 = (VCC – VCE – Ve) / IC1

where RL’ = Rc2 // RL

we have hie2 = hfe1.re2

-hfe2 . RL’

Av2 = ------------

hie2

re2 = 26mv/Ie2 ohms

By applying Kirchoff’s voltage law to the out put loop, we get

Vcc = IC2 . RC2 + VCE2 + VE2 ------- (1)

We have VCE2 = VCC/2

And VE2 = IE2.RE2

We have IC2 = IE2

Take VE2 = VCC/10( If VE2 is more, drop across the capacitor load reduces)

From e.q(1) find RC2

Since RL’ = RC2 // RL , find RL

Since VE2 = IE2 . RE2 , find RE2.

Since

-hfe2 . RL’

Av2 = ------------ , find RL’

hie2

The stability factor is S = 1 + ( RB2 / RE2), find RB2

The base resistance of the 2nd stage is

RB2 = R3 // R4

We have VB2 = VCC . [R4/(R3 + R4)]

And VB2 = VBE2 + VE2

Find R3.

Then from RB2 = R3 // R4 find R4

Apply KVL for the out put circuit of 1st stage, VCC = IC1 RC1 + VCE1 + VE1

Since IC1 = IE1 find RC1

We have RE1 = VE1 / IE1 find RE1

From S = = 1 + ( RB1 / RE1), find RB1

The base resistance of the 1st stage is

RB1 = R1 // R2

We have VB1 = VCC . [R2/(R1 + R2)]

And VB1 = VBE1 + VE1

Find R2 and R1 .

Gain including source resistance is AVS = AV1. Ri1 / (Ri1 + RS)

Ri1 = hie1 // RB1

Find AVS

Total gain of the cascade including source resistance is AV = AVS . AV2

To find the i/p coupling capacitance

Take XCi = hie1 // RB1/10

And XCi = 1/(2ПfL Ci) find Ci

Rc2 // RL

The out put coupling capacitor can be obtained as XCO = --------------

10

And XCo = 1/(2ПfL Co) find Co

The by pass capacitor can be obtained as XCE2 = RE2/10

Where RE2 = RE2 // [( RB2 + hie2) / hfe2]

And XCE2 = 1/(2ПfL CE2) find CE2

Similarly CE1
PROCEDURE:

SOFTWARE :

1. Select the components from the toolbar and connect the circuit as shown in fig.
2. Check dc conditions and note down Vbe, Ib, Vce, Ic.
3. Apply a sinusoidal signal from the function generator and observe the out put wave forms.
4. Go for AC analysis and observe the magnitude vs frequency and phase vs frequency
graphs.

HARDWARE:

1. Connect the circuit as shown in figure, and check for the D.C conditions of the transistor to

ensure that it is in active region. Obtain the maximum signal handling capacity of the amplifier.

2. Finding the 3db bandwidth of the amplifier.

i)Keeping the input voltage constant (below maximum signal handling capacity), vary the
frequency of the input signal from 10 Hz to 1MHz and note down the corresponding output
voltage using CRO.

ii)Plot a graph between frequency and the voltage gain in db (Vo/Vi) on a semi log graph sheet and
determine the half power points. The difference of these two frequencies will give the 3db bandwidth
of the amplifier.

iii) Verify the relation Av= Av1 . Av2 at a frequency of 1KHz. Where Av is the gain of the two stage

amplifier and Av1 and Av2 are the gain’s of the first and second stages of the cascade section
respectively.

OBSERVATIONS :

Vi = mv

S.NO FREQUENCY Vo1 (v) Vo2(v) Av1 = Av2 = Av(db)=20

(Vo1/Vi) (Vo/Vo1) log(Vo/Vi)
RESULT:

SNO PARAMETER THEORITICAL EXPERIMENTAL

1. Mid band voltage gain

2. 3db gain

3. Lower half power frequencyf1=very

4. small

5.
Upper half power frequency f2
6.
Band width B=(f2-f1) = f2
 CHARACTERISTICS OF A SILICON CONTROLED RECTIFIER (SCR)

Aim:

To Study the forward characteristics of the given SCR (TY 6004) for different gate currents.

Apparatus :

Circuit Kit, Voltmeter(0-20V), Ammeter(0-100mA,0-500mA)

Circuit Diagram:

The circuit diagram for the study of the characteristics of SCR is given in Fig.1

Ia 0-100mA 1K
Ra 0.5K + -
00.000 A
Ig 50%
12V V1 + A +
00.000 V 00.000 A
- SCR G -
0-20V Vak TY6004 0-20mA
K 12V V2

Fig.1

Theory :
i. SCR firing is indicated by the sudden increase of current IA in the anode circuit along with
a

sudden fall in voltage across SCR’s anode to cathode.

ii. If SCR is on ‘ON’ state the anode current is sufficient enough to hold this SCR in ON

Procedure:

i. Connect the circuit as shown in the Fig.1

ii. Connect (0-500ma) Digital multimeter in anode circuit, (0-20)v voltmeter across SCR and

(0-100)ma meter in the gate circuit.

iii. Adjust gate current to any value in the range of (4.1,4.2,4.3………5.8,5.9,6.0)ma with the
help

of the power supply V2and a series resistance (potentiometer) in the gate circuit.

iv. Care should be exercised in adjusting the gate current in very small steps of 0.1V to
enable the

observation of the anode current variations carefully. Otherwise it is difficult to observe

and

record the same.

v. Initially fix the gate current IG = 0, and vary power supply V1 from its minimum and note

down the readings of VAK and IA tabulate these values in the table.

vi. Repeat step v for a different value of gate current.

vii. Plot the observations as shown in Table-1.

Table -I
 IG1=0 mA IG2=4.41mA IG3=4.46mA

Sno VAK(Volts) IA (mA) VAK (Volts) IA (mA) VAK (Volts) IA (mA)

Results:

It is experimentally observed that –

i. The holding current for the SCR TY 6004 is ________ mA

ii. The blocking region for Ig =0 extends upto__________ volts
iii. The break over voltage VBR ___________________________________ Volts

Specifications of SCR ( TY 6004)

i. Repetitive peak reverse voltages (open gate voltages) VRRM 400V

ii. Rms On state current Irms --------------- 6 Amps

iii. Average trigger voltage Vgt--------------- 1.5v

iv. Surge Non-Repetitive ON state current------- 7A

 UNIJUCTION TRANSISTOR CHARACTERISTICS

Aim :
i. To study the static characteristics of a given UJT (2N2646)
 ii. Identify the negative resistance region and estimate the resistance of the device.
Apparatus:

1. Circuit board containing UJT(2N2646), resistors

2. Ammeter (0-50mA)

3. Voltmeter (0-30 V)- 1 No, and (0-10V) – 1No.

4. Patch cords.

5.Regulated Power Supply Unit.

Circuit Diagram :
The circuit diagram for the study of the characteristics is shown in Fig.1 and the equivalent
circuit in Fig.2

220Ohms 0-50ma B2 220ohms

Ie E
B1 0-30V Vb1b2
0-10V Veb1 0-30V
0-30V

Fig.1

B2 +

r2
Ie
Veb1 VBB

VEE r1

-
B1
Fig.2
 Theory :

The Uni-junction transistor (UJT) is a three terminal silicon semiconductor device.

The UJT has only one PN junction. The PN junction is formed between the emitter

and the base regions. The emitter region is heavily doped. The emitter region is closer

to base (B1) terminal than base (B2). The operational difference between FET and

UJT is that FET is normally operated with gate junction reverse biased, whereas

useful behavior of UJT occurs when the emitter is forward biased.

Procedure :

i. Connect the circuit as shown in Fig.1 above.

ii. Ensure that the power supply is switched OFF. Keep the voltage control knob in
the minimum position and current control knob in maximum position.
iii. Switch ON the power supply. Keep VBB at 5volts. Now vary VEB1 by varying VEE.
Note down IE once UJT is ON, Increase the emitter current IE in small steps of
5mA and note down the corresponding VEB1 value upto a maximum of 50mA.

iv. Repeat above steps for V EB = 10V and 15V. Plot graph of IE versus V EB1 for different
values of VBB as shown in Fig.3.

v. Calculate resistance of the UJT in the negative resistance region using the formula
r(-) = V EB1 /  I E at V BB = constant.

Table-I
 S.No. VBB=5 V VBB=8 V VBB=10 V

IE VEB1 IE VEB1 IE VEB1

(ma) (V) (ma) (V) (ma) (V)

Result :

i. The operation of UJT as a negative resistance device is verified.

ii. Present results of the experiment

R (-) = … ohms at VBB=5V

R (-) =……ohms at VBB=10V

R (-) = … ohms at VBB=15V

i. The operation of UJT as a negative resistance device is verified.

Specifications:

Intrinsic stand off ratio : ή

Peak point emitter current : Ipeak

Valley point current : Iv

Discussions:

i. Draw the equivalent circuit of the UJT?

ii. Name a few of the applications of the UJT?

r -ΔV
B1 = EB1 / ΔIE at Constant VBB
 VEB

Fig.3 IE

Characteristics of a UJT (2N2646)

.UJT RELAXATION OSCILLATOR

Aim: To generate the saw tooth wave form by using UJT relaxation oscillator.

Apparatus: i) C.R.O ii) Function Generator

iii) Power Supply iv) Bread Board
v) Resistor vi) Capacitor.
Design:  = 0.5 to 0.8  = Rb1 /Rb1 + Rb2
Rb1 = 4.7K ohms Rb2 = 2.2K ohms
Select  = 0.65 T = RC log e(1/(1-n))
Select C= 0.01f, and R = 50K, 60K, 70K.
Circuit Diagram:
 +Vbb
12V

2.2KOhm
50%

2N2646

Vb2

Vb1
4.7KOhm

Procedure:
1. Connect the circuit as shown in the circuit Diagram.
2. Keep the capacitance constant and vary the resistance.
3. Note down the output waveforms across the capacitor and at the out put.
4. Measure the frequency of the waveform. Compare the theoretical frequency.
Out Put Waveforms:

Out put wave forms of UJT Relaxation Oscillator

Result: The UJT as square wave generator is verified.
Exercises: Design a 1 KHz square wave using UJT relaxation oscillator

9.MOSFET Amplifier
Aim : 1. Design as MOSFET amplifier

2. Simulate the design circuit

3. Develop the hardware for design circuit

4. Compare the practical results with theoretical values

Apparatus required:

1. CRO
2. Function Generator
3. Regulator DC power supply
4. Decade resistance box
 5. Resistors
6. Capacitors
7. Transistor(MOSFET)
8. Breadboard
9. Connecting wires

Procedure:

1. Connect the circuit as per the circuit diagram shown

2. Apply the supply voltage Vdd=12V
3. Make sure that the transistor is operating in right region by keeping Vgs and Ids
4. Now feed an ac signal of 20mv at the input of the amplifier with different frequencies ranging
from 100Hz to 300mHz and measure the amplifier output voltage
5. Now calculate the gain in decibals at various input signal frequencies.
6. Draw a graph with frequencies on x-axis and gain in db on y-axis
7. From the graph calculate band width

Result:

10.Darlington Pair Amplifier…………………..

Aim: a) Perform the frequency response of a Darlington amplifier

b) Calculate the gain and bandwidth.

Apparatus:

1. Transistor
2. Capacitors
3. Resistors
4. Function generator
5. CRO
 6. Regulated power supply

Circuit diagram:

Procedure:

1. Connect the circuit diagram as shown in figure

2. Apply supply voltage Vcc=12v
3. Keep Vi=20mv by keeping frequency of function generator at 1KHz.
4. Keep input constant throughout the experiment
5. Vary the input frequency 50Hz to 1MHz and note down the output voltage
6. Calculate the gain of the amplifier in decibals using the formula

Gain in db = 20log(Vo/Vi)

7.Plot the graph between frequency vs gain

Result:
CLASS B COMPLEMENTARY SYMMETRY POWER
AMPLIFIER

AIM: To calculate the efficiency of Class B Complementary Symmetry Power Amplifier

and observe the cross over distortion.

APPARATUS:
1. C.R.O
2. Function Generator
3. Regulated Power Supply
4. Resistors
5. Capacitors
6. Bread Board
7. Connecting Wires

PROCEDURE:

1. Connect the components as per the circuit diagram and note down Idc
2. Apply the sinusoidal signal amplitude around 10v at constant frequency (1KHz).
3. Observe the cross over distortion in the output waveforms.
4. Calculate the efficiency (ὴ) of the amplifier.
RESULT:
The efficiency of the Class B Complementary Symmetry Power Amplifier is calculated
and cross over distortion is observed.

CASCODE AMPLIFIER
AIM: To design a cascode amplifier and observe its frequency response.

SOFTWARE USED: NI MULTISIM 14.0

APPARATUS REQUIRED:

1. Transistor (BC107)
2. Function Generator
3. Resistors
4. Capacitors
5. D.S.O

THEORY:
Cascode amplifier is a two-stage circuit consisting of a transconductance amplifier followed
by a buffer amplifier. The word cascade was originated from the phase “ Cascode
to Cathode ”. This circuit have a lot of advantages over the single stage amplifier like better
input isolation, better gain, improved bandwidth, higher input impedance, higher output
impedance, better stability, higher slow rate etc.

The reason behind the increase in bandwidth is the reduction of Miller Effect.

Cascode Amplifier is generally constructed using FET (or) BJT. One stage will be usually
wired in common source/ common emitter mode and the other will be wired in common
base/common gate mode.

PROCEDURE:

1. Connect the circuit as per the diagram.

2. Draw equivalent circuit for given amplifier, check the D.C conditions to ensure it is in
active conditions and note IC, IB, IE, VCE, VBE.
3. Apply sinewave from function generator and observe maximum signal handling
capacity of amplifier at constant input signal frequency of 1KHz.
4. Set the input signal amplitude which is less than maximum signal handling capacity.
5. For constant input amplitude by varying frequency from 100Hz to 1MHz. Note
corresponding output amplitude.
6. Go for A.C analysis and observe frequency vs gain graph.
RESULT:

CLASS A: POWER AMPLIFIER

AIM: To design class ‘A’ power amplifier using the given parameters and to calculate
the efficiency of the amplifier.

APPARATUS: CRO, Function generator, Decade resistance box, Resistors, Capacitors,

TrCL100.

DESIGN:

Vcc = , Vce = , Ic = , Vbe=

Find Rc and Rs from the below given equations.

Vcc= IcRc+Vce

Vcc= IbRs+Vbe

PROCEDURE:

1. Connect the components as per the circuit diagram.

2. Draw dc equivalent circuit for the given amplifier, check dc conditions of the
transistor to ensure that it is in active condition and note down Vbc, Ib, Vce, Ic.
3. Select C1=C2=47uf
4. Apply a sinusoidal signal from the function generator and observe the
maximum signal handling capacity of the amplifier at constant signal frequency
of 1KHz.
5. Set the amplitude of input signal which is less than the maximum signal
handling capacity.
6. For constant input amplitude, by varying the frequency from 100Hz to 1MHz,
note down the corresponding output amplitude.
RESULT:

The operation of class ‘A’ power amplifier is studied and efficiency is calculated.

The efficiency of the class A power amplifier is 11.32%

 SINGLE TUNED VOLTAGE AMPLIFIER –(CLASS C -AMPLIFIER).
AIM:

To design single tuned voltage amplifier using given parameters and to observe the frequency
response of the amplifier.

APPARATUS:

CRO,Function generator,RPS,Resistors,Capacitors,DIB,DCB,TrBC107.

THEORY:

The amplifier is said to be a class c ,if the Q-point and the input signal are selected such that the
output signal is obtained for less than a half cycle for a full input cycle.Hence only that much part is
reproduced at the output. For remaining cycle of the input cycle,the transistor remains cut-off and
no signal is produced at the output. Here a parallel resonant circuit acts as a load impedance.As
collector current followed for less than half cycle,the IC consists of a series of pulses with the
harmonics of the input signal. A parallel tuned circuit acting as a load impedance is turned the
input frequency.

Therefore it filters out harmonic frequencies and produce a sine wave output voltage consisting of
fundamental component of the input signal.

Fr=1/2

CIRCUIT DIAGRAM:
DESIGN:

L=10mH C=0.01H

Fr=1/2

PROCEDURE:

1.Connect the circuit.

2.Apply a sine signal and vary input signal and note down output values.

3.At Fr the output will be maximum.

4.Compare practical and theoretical Fr values.

OBSERVATION:

T=______.

Fr=1/T.
Result: