UNIVERSITY OF NAIROBI UNIVERSITY EXAMINATIONS 2008/20 JOOL OF COMPUTING LIBRARY First Semester Examination for the Degree of Bachelor of Science (Computer Scienc ICS311 : Advanced Computer Architecture TIME: DATI ‘There are five (5) questions on this paper. Candidates are required to attempt Question 1 and any TWO other questions Question 1 (20 marks) a) The classical von Neumann model of the computer can be enhanced to exploit parallelism in the. computation process. Explain clearly the concepts of available parallelism and utilized parallelism. Give an example of available functional parallelism naming the computer architecture that exploits that type. (4 marks) b) Distinguish between instruction level and threa el available parallelism. Describe two parallel computer ‘architectures, one that exploits instruction level and a second that exploits thread level parallelism, (4 marks) 6) Describe the concurrent “C” access scheme that is applicable on an interleaved ‘memory system and explain the performance advantages. (4 marks) 4) Inthe context of instruction level paraliel architectures explain i) Output dependency and if) Anti-dependency. Explain why they are considered as false data dependencies. (4 marks) * ©) Explain clearly the goals of the array processor architecture on the one hand and S| iP architecture on the other. (4 marks) | Question 2. (15 marks) instruction execution, (Smarks) >) Explain the distingui is i uishing characteristics of i) coarse-grained and ii) fine-orai wy poseson ems) °) Describe the NUMA architec! sluster architecture that it addr CC-NUMA arebitecture. ture highlighting the limitations of the traditional sses. Also, explain the cache coherency problem in (5 marks) NFORMI UNIVERSITY OF NAIRA-Question 3 (15 marks) 1 architectures endeavor to exploit instruction level parallelism (ILP). f dependencies that present a challenge to (5 marks) a) Supersca Explain this. Also explain the types o effectiveness of the superscalar architecture. by Using an illustrative diagram, describe the organization and operation of a superscalar processor that employs direct (blocking) instruction issue as opposed to shelved issue. (5 marks) ¢) Related to the superscalar concept, describe the idea of super-threading. (5 marks) Question 4 (15 marks) processor architecture, ¢.g. a) Using an illustrative diagram, describe the classical array (5 marks) as employed in the Burroughs Scientific Processor computer. and C[I:n] where n is large. Describe the sm implemented by processors. (5 marks) b) Given three vectors A[J:n], BUI:n] performance gains realizable by employing i) pipelined parallelis vector processor units and ii) spatial parallelism implemented by array Explain the importance of the PE interconnection network as a design issue of the array processor architecture. Assume an array processor with 16 PEs, compare the two interconnection networks known as the bus and 2-D near-neighbour with wrap- ‘around in terms of two parameters, network diameter, throughput and probability of blocking. (5 marks) 9 Question 5 (15 marks) a) Deseribe the objectives (expected benefits) and the basic structure of the symmetric multiprocessor system (SMP). (5 marks) + b) In the context of SMP architectures, explain the cache coherency problem. Describe respectively i) the directory based and ii) the distributed cache coherency protocols. (S marks) ~ ) For an SMP, a switching network may be an appropriate interconnection system for connecting 8 processors to a shared memory system consisting of 8 memory modules (units). Compare two alternative switch design options, namely crossbar switch and the Omega switch with regard to implementation complexity, bandwidth and probability of blocking. (5 marks)