RP2350 Datasheet

Bits Description Type Reset

1 Reserved. - -

0 VBUS_DETECTED: Device: VBUS Detected RO 0x0

USB: INT_EP_CTRL Register

Offset: 0x054

Description
interrupt endpoint control register

Table 1202.
Bits Description Type Reset
INT_EP_CTRL Register

31:16 Reserved. - -

15:1 INT_EP_ACTIVE: Host: Enable interrupt endpoint 1 → 15 RW 0x0000

0 Reserved. - -

USB: BUFF_STATUS Register

Offset: 0x058

Description
Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is
enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the
next clock cycle.

Table 1203.
Bits Description Type Reset
BUFF_STATUS
Register
31 EP15_OUT WC 0x0

30 EP15_IN WC 0x0

29 EP14_OUT WC 0x0

28 EP14_IN WC 0x0

27 EP13_OUT WC 0x0

26 EP13_IN WC 0x0

25 EP12_OUT WC 0x0

24 EP12_IN WC 0x0

23 EP11_OUT WC 0x0

22 EP11_IN WC 0x0

21 EP10_OUT WC 0x0

20 EP10_IN WC 0x0

19 EP9_OUT WC 0x0

18 EP9_IN WC 0x0

17 EP8_OUT WC 0x0

16 EP8_IN WC 0x0

15 EP7_OUT WC 0x0

14 EP7_IN WC 0x0

12.7. USB 1160

RP2350 Datasheet

Bits Description Type Reset

13 EP6_OUT WC 0x0

12 EP6_IN WC 0x0

11 EP5_OUT WC 0x0

10 EP5_IN WC 0x0

9 EP4_OUT WC 0x0

8 EP4_IN WC 0x0

7 EP3_OUT WC 0x0

6 EP3_IN WC 0x0

5 EP2_OUT WC 0x0

4 EP2_IN WC 0x0

3 EP1_OUT WC 0x0

2 EP1_IN WC 0x0

1 EP0_OUT WC 0x0

0 EP0_IN WC 0x0

USB: BUFF_CPU_SHOULD_HANDLE Register

Offset: 0x05c

Description
Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not
valid for host interrupt endpoint polling because they are only single buffered.

Table 1204.
Bits Description Type Reset
BUFF_CPU_SHOULD_H
ANDLE Register
31 EP15_OUT RO 0x0

30 EP15_IN RO 0x0

29 EP14_OUT RO 0x0

28 EP14_IN RO 0x0

27 EP13_OUT RO 0x0

26 EP13_IN RO 0x0

25 EP12_OUT RO 0x0

24 EP12_IN RO 0x0

23 EP11_OUT RO 0x0

22 EP11_IN RO 0x0

21 EP10_OUT RO 0x0

20 EP10_IN RO 0x0

19 EP9_OUT RO 0x0

18 EP9_IN RO 0x0

17 EP8_OUT RO 0x0

16 EP8_IN RO 0x0

12.7. USB 1161

RP2350 Datasheet

Bits Description Type Reset

15 EP7_OUT RO 0x0

14 EP7_IN RO 0x0

13 EP6_OUT RO 0x0

12 EP6_IN RO 0x0

11 EP5_OUT RO 0x0

10 EP5_IN RO 0x0

9 EP4_OUT RO 0x0

8 EP4_IN RO 0x0

7 EP3_OUT RO 0x0

6 EP3_IN RO 0x0

5 EP2_OUT RO 0x0

4 EP2_IN RO 0x0

3 EP1_OUT RO 0x0

2 EP1_IN RO 0x0

1 EP0_OUT RO 0x0

0 EP0_IN RO 0x0

USB: EP_ABORT Register

Offset: 0x060

Description
Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a
buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in
EP_ABORT_DONE is set when it is safe to modify the buffer control register.

Table 1205.
Bits Description Type Reset
EP_ABORT Register

31 EP15_OUT RW 0x0

30 EP15_IN RW 0x0

29 EP14_OUT RW 0x0

28 EP14_IN RW 0x0

27 EP13_OUT RW 0x0

26 EP13_IN RW 0x0

25 EP12_OUT RW 0x0

24 EP12_IN RW 0x0

23 EP11_OUT RW 0x0

22 EP11_IN RW 0x0

21 EP10_OUT RW 0x0

20 EP10_IN RW 0x0

19 EP9_OUT RW 0x0

12.7. USB 1162

RP2350 Datasheet

Bits Description Type Reset

18 EP9_IN RW 0x0

17 EP8_OUT RW 0x0

16 EP8_IN RW 0x0

15 EP7_OUT RW 0x0

14 EP7_IN RW 0x0

13 EP6_OUT RW 0x0

12 EP6_IN RW 0x0

11 EP5_OUT RW 0x0

10 EP5_IN RW 0x0

9 EP4_OUT RW 0x0

8 EP4_IN RW 0x0

7 EP3_OUT RW 0x0

6 EP3_IN RW 0x0

5 EP2_OUT RW 0x0

4 EP2_IN RW 0x0

3 EP1_OUT RW 0x0

2 EP1_IN RW 0x0

1 EP0_OUT RW 0x0

0 EP0_IN RW 0x0

USB: EP_ABORT_DONE Register

Offset: 0x064

Description
Device only: Used in conjunction with EP_ABORT. Set once an endpoint is idle so the programmer knows it is safe to
modify the buffer control register.

Table 1206.
Bits Description Type Reset
EP_ABORT_DONE
Register
31 EP15_OUT WC 0x0

30 EP15_IN WC 0x0

29 EP14_OUT WC 0x0

28 EP14_IN WC 0x0

27 EP13_OUT WC 0x0

26 EP13_IN WC 0x0

25 EP12_OUT WC 0x0

24 EP12_IN WC 0x0

23 EP11_OUT WC 0x0

22 EP11_IN WC 0x0

21 EP10_OUT WC 0x0

12.7. USB 1163

RP2350 Datasheet

Bits Description Type Reset

20 EP10_IN WC 0x0

19 EP9_OUT WC 0x0

18 EP9_IN WC 0x0

17 EP8_OUT WC 0x0

16 EP8_IN WC 0x0

15 EP7_OUT WC 0x0

14 EP7_IN WC 0x0

13 EP6_OUT WC 0x0

12 EP6_IN WC 0x0

11 EP5_OUT WC 0x0

10 EP5_IN WC 0x0

9 EP4_OUT WC 0x0

8 EP4_IN WC 0x0

7 EP3_OUT WC 0x0

6 EP3_IN WC 0x0

5 EP2_OUT WC 0x0

4 EP2_IN WC 0x0

3 EP1_OUT WC 0x0

2 EP1_IN WC 0x0

1 EP0_OUT WC 0x0

0 EP0_IN WC 0x0

USB: EP_STALL_ARM Register

Offset: 0x068

Description
Device: this bit must be set in conjunction with the STALL bit in the buffer control register to send a STALL on EP0.
The device controller clears these bits when a SETUP packet is received because the USB spec requires that a
STALL condition is cleared when a SETUP packet is received.

Table 1207.
Bits Description Type Reset
EP_STALL_ARM
Register
31:2 Reserved. - -

1 EP0_OUT RW 0x0

0 EP0_IN RW 0x0

USB: NAK_POLL Register

Offset: 0x06c

Description
Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.

12.7. USB 1164

RP2350 Datasheet

Table 1208.
Bits Description Type Reset
NAK_POLL Register

31:28 RETRY_COUNT_HI: Bits 9:6 of nak_retry count RO 0x0

27 EPX_STOPPED_ON_NAK: EPX polling has stopped because a nak was WC 0x0

received

26 STOP_EPX_ON_NAK: Stop polling epx when a nak is received RW 0x0

25:16 DELAY_FS: NAK polling interval for a full speed device RW 0x010

15:10 RETRY_COUNT_LO: Bits 5:0 of nak_retry_count RO 0x00

9:0 DELAY_LS: NAK polling interval for a low speed device RW 0x010

USB: EP_STATUS_STALL_NAK Register

Offset: 0x070

Description
Device: bits are set when the IRQ_ON_NAK or IRQ_ON_STALL bits are set. For EP0 this comes from SIE_CTRL. For all other
endpoints it comes from the endpoint control register.

Table 1209.
Bits Description Type Reset
EP_STATUS_STALL_N
AK Register
31 EP15_OUT WC 0x0

30 EP15_IN WC 0x0

29 EP14_OUT WC 0x0

28 EP14_IN WC 0x0

27 EP13_OUT WC 0x0

26 EP13_IN WC 0x0

25 EP12_OUT WC 0x0

24 EP12_IN WC 0x0

23 EP11_OUT WC 0x0

22 EP11_IN WC 0x0

21 EP10_OUT WC 0x0

20 EP10_IN WC 0x0

19 EP9_OUT WC 0x0

18 EP9_IN WC 0x0

17 EP8_OUT WC 0x0

16 EP8_IN WC 0x0

15 EP7_OUT WC 0x0

14 EP7_IN WC 0x0

13 EP6_OUT WC 0x0

12 EP6_IN WC 0x0

11 EP5_OUT WC 0x0

10 EP5_IN WC 0x0

9 EP4_OUT WC 0x0

12.7. USB 1165

RP2350 Datasheet

Bits Description Type Reset

8 EP4_IN WC 0x0

7 EP3_OUT WC 0x0

6 EP3_IN WC 0x0

5 EP2_OUT WC 0x0

4 EP2_IN WC 0x0

3 EP1_OUT WC 0x0

2 EP1_IN WC 0x0

1 EP0_OUT WC 0x0

0 EP0_IN WC 0x0

USB: USB_MUXING Register

Offset: 0x074

Description
Where to connect the USB controller. Should be to_phy by default.

Table 1210.
Bits Description Type Reset
USB_MUXING Register

31 SWAP_DPDM: Swap the USB PHY DP and DM pins and all related controls and RW 0x0
flip receive differential data. Can be used to switch USB DP/DP on the PCB.
This is done at a low level so overrides all other controls.

30:5 Reserved. - -

4 USBPHY_AS_GPIO: Use the usb DP and DM pins as GPIO pins instead of RW 0x0
connecting them to the USB controller.

3 SOFTCON RW 0x0

2 TO_DIGITAL_PAD RW 0x0

1 TO_EXTPHY RW 0x0

0 TO_PHY RW 0x1

USB: USB_PWR Register

Offset: 0x078

Description
Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the
override and then the override enable to switch over to the override value.

Table 1211. USB_PWR

Bits Description Type Reset
Register

31:6 Reserved. - -

5 OVERCURR_DETECT_EN RW 0x0

4 OVERCURR_DETECT RW 0x0

3 VBUS_DETECT_OVERRIDE_EN RW 0x0

2 VBUS_DETECT RW 0x0

1 VBUS_EN_OVERRIDE_EN RW 0x0

12.7. USB 1166

RP2350 Datasheet

Bits Description Type Reset

0 VBUS_EN RW 0x0

USB: USBPHY_DIRECT Register

Offset: 0x07c

Description
This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to
enable each override bit.

Table 1212.
Bits Description Type Reset
USBPHY_DIRECT
Register
31:26 Reserved. - -

25 RX_DM_OVERRIDE: Override rx_dm value into controller RW 0x0

24 RX_DP_OVERRIDE: Override rx_dp value into controller RW 0x0

23 RX_DD_OVERRIDE: Override rx_dd value into controller RW 0x0

22 DM_OVV: DM over voltage RO 0x0

21 DP_OVV: DP over voltage RO 0x0

20 DM_OVCN: DM overcurrent RO 0x0

19 DP_OVCN: DP overcurrent RO 0x0

18 RX_DM: DPM pin state RO 0x0

17 RX_DP: DPP pin state RO 0x0

16 RX_DD: Differential RX RO 0x0

15 TX_DIFFMODE: TX_DIFFMODE=0: Single ended mode RW 0x0

TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)

14 TX_FSSLEW: TX_FSSLEW=0: Low speed slew rate RW 0x0

TX_FSSLEW=1: Full speed slew rate

13 TX_PD: TX power down override (if override enable is set). 1 = powered down. RW 0x0

12 RX_PD: RX power down override (if override enable is set). 1 = powered down. RW 0x0

11 TX_DM: Output data. TX_DIFFMODE=1, Ignored RW 0x0

TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive.
DPM=TX_DM

10 TX_DP: Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. RW 0x0

TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive.
DPP=TX_DP

9 TX_DM_OE: Output enable. If TX_DIFFMODE=1, Ignored. RW 0x0

If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving

8 TX_DP_OE: Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - RW 0x0

DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving

7 Reserved. - -

6 DM_PULLDN_EN: DM pull down enable RW 0x0

5 DM_PULLUP_EN: DM pull up enable RW 0x0

12.7. USB 1167

RP2350 Datasheet

Bits Description Type Reset

4 DM_PULLUP_HISEL: Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - RW 0x0

Pull = Rpu1 + Rpu2

3 Reserved. - -

2 DP_PULLDN_EN: DP pull down enable RW 0x0

1 DP_PULLUP_EN: DP pull up enable RW 0x0

0 DP_PULLUP_HISEL: Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - RW 0x0

Pull = Rpu1 + Rpu2

USB: USBPHY_DIRECT_OVERRIDE Register

Offset: 0x080

Description
Override enable for each control in usbphy_direct

Table 1213.
Bits Description Type Reset
USBPHY_DIRECT_OVE
RRIDE Register
31:19 Reserved. - -

18 RX_DM_OVERRIDE_EN RW 0x0

17 RX_DP_OVERRIDE_EN RW 0x0

16 RX_DD_OVERRIDE_EN RW 0x0

15 TX_DIFFMODE_OVERRIDE_EN RW 0x0

14:13 Reserved. - -

12 DM_PULLUP_OVERRIDE_EN RW 0x0

11 TX_FSSLEW_OVERRIDE_EN RW 0x0

10 TX_PD_OVERRIDE_EN RW 0x0

9 RX_PD_OVERRIDE_EN RW 0x0

8 TX_DM_OVERRIDE_EN RW 0x0

7 TX_DP_OVERRIDE_EN RW 0x0

6 TX_DM_OE_OVERRIDE_EN RW 0x0

5 TX_DP_OE_OVERRIDE_EN RW 0x0

4 DM_PULLDN_EN_OVERRIDE_EN RW 0x0

3 DP_PULLDN_EN_OVERRIDE_EN RW 0x0

2 DP_PULLUP_EN_OVERRIDE_EN RW 0x0

1 DM_PULLUP_HISEL_OVERRIDE_EN RW 0x0

0 DP_PULLUP_HISEL_OVERRIDE_EN RW 0x0

USB: USBPHY_TRIM Register

Offset: 0x084

Description
Used to adjust trim values of USB phy pull down resistors.

12.7. USB 1168

RP2350 Datasheet

Table 1214.
Bits Description Type Reset
USBPHY_TRIM
Register
31:13 Reserved. - -

12:8 DM_PULLDN_TRIM: Value to drive to USB PHY RW 0x1f

DM pulldown resistor trim control
Experimental data suggests that the reset value will work, but this register
allows adjustment if required

7:5 Reserved. - -

4:0 DP_PULLDN_TRIM: Value to drive to USB PHY RW 0x1f

DP pulldown resistor trim control
Experimental data suggests that the reset value will work, but this register
allows adjustment if required

USB: LINESTATE_TUNING Register

Offset: 0x088

Description
Used for debug only.

Table 1215.
Bits Description Type Reset
LINESTATE_TUNING
Register
31:12 Reserved. - -

11:8 SPARE_FIX RW 0x0

7 DEV_LS_WAKE_FIX: Device - exit suspend on any non-idle signalling, not RW 0x1

qualified with a 1ms timer

6 DEV_RX_ERR_QUIESCE: Device - suppress repeated errors until the device RW 0x1

FSM is next in the process of decoding an inbound packet.

5 SIE_RX_CHATTER_SE0_FIX: RX - when recovering from line chatter or bitstuff RW 0x1

errors, treat SE0 as the end of chatter as well as
8 consecutive idle bits.

4 SIE_RX_BITSTUFF_FIX: RX - when a bitstuff error is signalled by rx_dasm, RW 0x1

unconditionally terminate RX decode to
avoid a hang during certain packet phases.

3 DEV_BUFF_CONTROL_DOUBLE_READ_FIX: Device - the controller FSM RW 0x1

performs two reads of the buffer status memory address to
avoid sampling metastable data. An enabled buffer is only used if both reads
match.

2 MULTI_HUB_FIX: Host - increase inter-packet and turnaround timeouts to RW 0x0

accommodate worst-case hub delays.

1 LINESTATE_DELAY: Device/Host - add an extra 1-bit debounce of linestate RW 0x0

sampling.

0 RCV_DELAY: Device - register the received data to account for hub bit dribble RW 0x0
before EOP. Only affects certain hubs.

USB: INTR Register

Offset: 0x08c

Description
Raw Interrupts

12.7. USB 1169

RP2350 Datasheet

Table 1216. INTR

Bits Description Type Reset
Register

31:24 Reserved. - -

23 EPX_STOPPED_ON_NAK: Source: NAK_POLL.EPX_STOPPED_ON_NAK RO 0x0

22 DEV_SM_WATCHDOG_FIRED: Source: DEV_SM_WATCHDOG.FIRED RO 0x0

21 ENDPOINT_ERROR: Source: SIE_STATUS.ENDPOINT_ERROR RO 0x0

20 RX_SHORT_PACKET: Source: SIE_STATUS.RX_SHORT_PACKET RO 0x0

19 EP_STALL_NAK: Raised when any bit in EP_STATUS_STALL_NAK is set. Clear RO 0x0

by clearing all bits in EP_STATUS_STALL_NAK.

18 ABORT_DONE: Raised when any bit in ABORT_DONE is set. Clear by clearing RO 0x0
all bits in ABORT_DONE.

17 DEV_SOF: Set every time the device receives a SOF (Start of Frame) packet. RO 0x0
Cleared by reading SOF_RD

16 SETUP_REQ: Device. Source: SIE_STATUS.SETUP_REC RO 0x0

15 DEV_RESUME_FROM_HOST: Set when the device receives a resume from the RO 0x0
host. Cleared by writing to SIE_STATUS.RESUME

14 DEV_SUSPEND: Set when the device suspend state changes. Cleared by RO 0x0
writing to SIE_STATUS.SUSPENDED

13 DEV_CONN_DIS: Set when the device connection state changes. Cleared by RO 0x0
writing to SIE_STATUS.CONNECTED

12 BUS_RESET: Source: SIE_STATUS.BUS_RESET RO 0x0

11 VBUS_DETECT: Source: SIE_STATUS.VBUS_DETECTED RO 0x0

10 STALL: Source: SIE_STATUS.STALL_REC RO 0x0

9 ERROR_CRC: Source: SIE_STATUS.CRC_ERROR RO 0x0

8 ERROR_BIT_STUFF: Source: SIE_STATUS.BIT_STUFF_ERROR RO 0x0

7 ERROR_RX_OVERFLOW: Source: SIE_STATUS.RX_OVERFLOW RO 0x0

6 ERROR_RX_TIMEOUT: Source: SIE_STATUS.RX_TIMEOUT RO 0x0

5 ERROR_DATA_SEQ: Source: SIE_STATUS.DATA_SEQ_ERROR RO 0x0

4 BUFF_STATUS: Raised when any bit in BUFF_STATUS is set. Clear by clearing RO 0x0
all bits in BUFF_STATUS.

3 TRANS_COMPLETE: Raised every time SIE_STATUS.TRANS_COMPLETE is RO 0x0

set. Clear by writing to this bit.

2 HOST_SOF: Host: raised every time the host sends a SOF (Start of Frame). RO 0x0
Cleared by reading SOF_RD

1 HOST_RESUME: Host: raised when a device wakes up the host. Cleared by RO 0x0
writing to SIE_STATUS.RESUME

0 HOST_CONN_DIS: Host: raised when a device is connected or disconnected RO 0x0

(i.e. when SIE_STATUS.SPEED changes). Cleared by writing to
SIE_STATUS.SPEED

USB: INTE Register

Offset: 0x090

12.7. USB 1170

RP2350 Datasheet

Description
Interrupt Enable

Table 1217. INTE

Bits Description Type Reset
Register

31:24 Reserved. - -

23 EPX_STOPPED_ON_NAK: Source: NAK_POLL.EPX_STOPPED_ON_NAK RW 0x0

22 DEV_SM_WATCHDOG_FIRED: Source: DEV_SM_WATCHDOG.FIRED RW 0x0

21 ENDPOINT_ERROR: Source: SIE_STATUS.ENDPOINT_ERROR RW 0x0

20 RX_SHORT_PACKET: Source: SIE_STATUS.RX_SHORT_PACKET RW 0x0

19 EP_STALL_NAK: Raised when any bit in EP_STATUS_STALL_NAK is set. Clear RW 0x0

by clearing all bits in EP_STATUS_STALL_NAK.

18 ABORT_DONE: Raised when any bit in ABORT_DONE is set. Clear by clearing RW 0x0
all bits in ABORT_DONE.

17 DEV_SOF: Set every time the device receives a SOF (Start of Frame) packet. RW 0x0
Cleared by reading SOF_RD

16 SETUP_REQ: Device. Source: SIE_STATUS.SETUP_REC RW 0x0

15 DEV_RESUME_FROM_HOST: Set when the device receives a resume from the RW 0x0
host. Cleared by writing to SIE_STATUS.RESUME

14 DEV_SUSPEND: Set when the device suspend state changes. Cleared by RW 0x0
writing to SIE_STATUS.SUSPENDED

13 DEV_CONN_DIS: Set when the device connection state changes. Cleared by RW 0x0
writing to SIE_STATUS.CONNECTED

12 BUS_RESET: Source: SIE_STATUS.BUS_RESET RW 0x0

11 VBUS_DETECT: Source: SIE_STATUS.VBUS_DETECTED RW 0x0

10 STALL: Source: SIE_STATUS.STALL_REC RW 0x0

9 ERROR_CRC: Source: SIE_STATUS.CRC_ERROR RW 0x0

8 ERROR_BIT_STUFF: Source: SIE_STATUS.BIT_STUFF_ERROR RW 0x0

7 ERROR_RX_OVERFLOW: Source: SIE_STATUS.RX_OVERFLOW RW 0x0

6 ERROR_RX_TIMEOUT: Source: SIE_STATUS.RX_TIMEOUT RW 0x0

5 ERROR_DATA_SEQ: Source: SIE_STATUS.DATA_SEQ_ERROR RW 0x0

4 BUFF_STATUS: Raised when any bit in BUFF_STATUS is set. Clear by clearing RW 0x0
all bits in BUFF_STATUS.

3 TRANS_COMPLETE: Raised every time SIE_STATUS.TRANS_COMPLETE is RW 0x0

set. Clear by writing to this bit.

2 HOST_SOF: Host: raised every time the host sends a SOF (Start of Frame). RW 0x0
Cleared by reading SOF_RD

1 HOST_RESUME: Host: raised when a device wakes up the host. Cleared by RW 0x0
writing to SIE_STATUS.RESUME

0 HOST_CONN_DIS: Host: raised when a device is connected or disconnected RW 0x0

(i.e. when SIE_STATUS.SPEED changes). Cleared by writing to
SIE_STATUS.SPEED

USB: INTF Register

12.7. USB 1171

RP2350 Datasheet

Offset: 0x094

Description
Interrupt Force

Table 1218. INTF

Bits Description Type Reset
Register

31:24 Reserved. - -

23 EPX_STOPPED_ON_NAK: Source: NAK_POLL.EPX_STOPPED_ON_NAK RW 0x0

22 DEV_SM_WATCHDOG_FIRED: Source: DEV_SM_WATCHDOG.FIRED RW 0x0

21 ENDPOINT_ERROR: Source: SIE_STATUS.ENDPOINT_ERROR RW 0x0

20 RX_SHORT_PACKET: Source: SIE_STATUS.RX_SHORT_PACKET RW 0x0

19 EP_STALL_NAK: Raised when any bit in EP_STATUS_STALL_NAK is set. Clear RW 0x0

by clearing all bits in EP_STATUS_STALL_NAK.

18 ABORT_DONE: Raised when any bit in ABORT_DONE is set. Clear by clearing RW 0x0
all bits in ABORT_DONE.

17 DEV_SOF: Set every time the device receives a SOF (Start of Frame) packet. RW 0x0
Cleared by reading SOF_RD

16 SETUP_REQ: Device. Source: SIE_STATUS.SETUP_REC RW 0x0

15 DEV_RESUME_FROM_HOST: Set when the device receives a resume from the RW 0x0
host. Cleared by writing to SIE_STATUS.RESUME

14 DEV_SUSPEND: Set when the device suspend state changes. Cleared by RW 0x0
writing to SIE_STATUS.SUSPENDED

13 DEV_CONN_DIS: Set when the device connection state changes. Cleared by RW 0x0
writing to SIE_STATUS.CONNECTED

12 BUS_RESET: Source: SIE_STATUS.BUS_RESET RW 0x0

11 VBUS_DETECT: Source: SIE_STATUS.VBUS_DETECTED RW 0x0

10 STALL: Source: SIE_STATUS.STALL_REC RW 0x0

9 ERROR_CRC: Source: SIE_STATUS.CRC_ERROR RW 0x0

8 ERROR_BIT_STUFF: Source: SIE_STATUS.BIT_STUFF_ERROR RW 0x0

7 ERROR_RX_OVERFLOW: Source: SIE_STATUS.RX_OVERFLOW RW 0x0

6 ERROR_RX_TIMEOUT: Source: SIE_STATUS.RX_TIMEOUT RW 0x0

5 ERROR_DATA_SEQ: Source: SIE_STATUS.DATA_SEQ_ERROR RW 0x0

4 BUFF_STATUS: Raised when any bit in BUFF_STATUS is set. Clear by clearing RW 0x0
all bits in BUFF_STATUS.

3 TRANS_COMPLETE: Raised every time SIE_STATUS.TRANS_COMPLETE is RW 0x0

set. Clear by writing to this bit.

2 HOST_SOF: Host: raised every time the host sends a SOF (Start of Frame). RW 0x0
Cleared by reading SOF_RD

1 HOST_RESUME: Host: raised when a device wakes up the host. Cleared by RW 0x0
writing to SIE_STATUS.RESUME

0 HOST_CONN_DIS: Host: raised when a device is connected or disconnected RW 0x0

(i.e. when SIE_STATUS.SPEED changes). Cleared by writing to
SIE_STATUS.SPEED

12.7. USB 1172

RP2350 Datasheet

USB: INTS Register

Offset: 0x098

Description
Interrupt status after masking & forcing

Table 1219. INTS

Bits Description Type Reset
Register

31:24 Reserved. - -

23 EPX_STOPPED_ON_NAK: Source: NAK_POLL.EPX_STOPPED_ON_NAK RO 0x0

22 DEV_SM_WATCHDOG_FIRED: Source: DEV_SM_WATCHDOG.FIRED RO 0x0

21 ENDPOINT_ERROR: Source: SIE_STATUS.ENDPOINT_ERROR RO 0x0

20 RX_SHORT_PACKET: Source: SIE_STATUS.RX_SHORT_PACKET RO 0x0

19 EP_STALL_NAK: Raised when any bit in EP_STATUS_STALL_NAK is set. Clear RO 0x0

by clearing all bits in EP_STATUS_STALL_NAK.

18 ABORT_DONE: Raised when any bit in ABORT_DONE is set. Clear by clearing RO 0x0
all bits in ABORT_DONE.

17 DEV_SOF: Set every time the device receives a SOF (Start of Frame) packet. RO 0x0
Cleared by reading SOF_RD

16 SETUP_REQ: Device. Source: SIE_STATUS.SETUP_REC RO 0x0

15 DEV_RESUME_FROM_HOST: Set when the device receives a resume from the RO 0x0
host. Cleared by writing to SIE_STATUS.RESUME

14 DEV_SUSPEND: Set when the device suspend state changes. Cleared by RO 0x0
writing to SIE_STATUS.SUSPENDED

13 DEV_CONN_DIS: Set when the device connection state changes. Cleared by RO 0x0
writing to SIE_STATUS.CONNECTED

12 BUS_RESET: Source: SIE_STATUS.BUS_RESET RO 0x0

11 VBUS_DETECT: Source: SIE_STATUS.VBUS_DETECTED RO 0x0

10 STALL: Source: SIE_STATUS.STALL_REC RO 0x0

9 ERROR_CRC: Source: SIE_STATUS.CRC_ERROR RO 0x0

8 ERROR_BIT_STUFF: Source: SIE_STATUS.BIT_STUFF_ERROR RO 0x0

7 ERROR_RX_OVERFLOW: Source: SIE_STATUS.RX_OVERFLOW RO 0x0

6 ERROR_RX_TIMEOUT: Source: SIE_STATUS.RX_TIMEOUT RO 0x0

5 ERROR_DATA_SEQ: Source: SIE_STATUS.DATA_SEQ_ERROR RO 0x0

4 BUFF_STATUS: Raised when any bit in BUFF_STATUS is set. Clear by clearing RO 0x0
all bits in BUFF_STATUS.

3 TRANS_COMPLETE: Raised every time SIE_STATUS.TRANS_COMPLETE is RO 0x0

set. Clear by writing to this bit.

2 HOST_SOF: Host: raised every time the host sends a SOF (Start of Frame). RO 0x0
Cleared by reading SOF_RD

1 HOST_RESUME: Host: raised when a device wakes up the host. Cleared by RO 0x0
writing to SIE_STATUS.RESUME

12.7. USB 1173

RP2350 Datasheet

Bits Description Type Reset

0 HOST_CONN_DIS: Host: raised when a device is connected or disconnected RO 0x0

(i.e. when SIE_STATUS.SPEED changes). Cleared by writing to
SIE_STATUS.SPEED

USB: SOF_TIMESTAMP_RAW Register

Offset: 0x100

Table 1220.
Bits Description Type Reset
SOF_TIMESTAMP_RA
W Register
31:21 Reserved. - -

20:0 Device only. Raw value of free-running PHY clock counter @48MHz. Used to RO 0x000000
calculate time between SOF events.

USB: SOF_TIMESTAMP_LAST Register

Offset: 0x104

Table 1221.
Bits Description Type Reset
SOF_TIMESTAMP_LAS
T Register
31:21 Reserved. - -

20:0 Device only. Value of free-running PHY clock counter @48MHz when last SOF RO 0x000000
event occured.

USB: SM_STATE Register

Offset: 0x108

Table 1222.
Bits Description Type Reset
SM_STATE Register

31:12 Reserved. - -

11:8 RX_DASM RO 0x0

7:5 BC_STATE RO 0x0

4:0 STATE RO 0x00

USB: EP_TX_ERROR Register

Offset: 0x10c

Description
TX error count for each endpoint. Write to each field to reset the counter to 0.

Table 1223.
Bits Description Type Reset
EP_TX_ERROR
Register
31:30 EP15 WC 0x0

29:28 EP14 WC 0x0

27:26 EP13 WC 0x0

25:24 EP12 WC 0x0

23:22 EP11 WC 0x0

21:20 EP10 WC 0x0

19:18 EP9 WC 0x0

12.7. USB 1174

RP2350 Datasheet

Bits Description Type Reset

17:16 EP8 WC 0x0

15:14 EP7 WC 0x0

13:12 EP6 WC 0x0

11:10 EP5 WC 0x0

9:8 EP4 WC 0x0

7:6 EP3 WC 0x0

5:4 EP2 WC 0x0

3:2 EP1 WC 0x0

1:0 EP0 WC 0x0

USB: EP_RX_ERROR Register

Offset: 0x110

Description
RX error count for each endpoint. Write to each field to reset the counter to 0.

Table 1224.
Bits Description Type Reset
EP_RX_ERROR
Register
31 EP15_SEQ WC 0x0

30 EP15_TRANSACTION WC 0x0

29 EP14_SEQ WC 0x0

28 EP14_TRANSACTION WC 0x0

27 EP13_SEQ WC 0x0

26 EP13_TRANSACTION WC 0x0

25 EP12_SEQ WC 0x0

24 EP12_TRANSACTION WC 0x0

23 EP11_SEQ WC 0x0

22 EP11_TRANSACTION WC 0x0

21 EP10_SEQ WC 0x0

20 EP10_TRANSACTION WC 0x0

19 EP9_SEQ WC 0x0

18 EP9_TRANSACTION WC 0x0

17 EP8_SEQ WC 0x0

16 EP8_TRANSACTION WC 0x0

15 EP7_SEQ WC 0x0

14 EP7_TRANSACTION WC 0x0

13 EP6_SEQ WC 0x0

12 EP6_TRANSACTION WC 0x0

11 EP5_SEQ WC 0x0

12.7. USB 1175

RP2350 Datasheet

Bits Description Type Reset

10 EP5_TRANSACTION WC 0x0

9 EP4_SEQ WC 0x0

8 EP4_TRANSACTION WC 0x0

7 EP3_SEQ WC 0x0

6 EP3_TRANSACTION WC 0x0

5 EP2_SEQ WC 0x0

4 EP2_TRANSACTION WC 0x0

3 EP1_SEQ WC 0x0

2 EP1_TRANSACTION WC 0x0

1 EP0_SEQ WC 0x0

0 EP0_TRANSACTION WC 0x0

USB: DEV_SM_WATCHDOG Register

Offset: 0x114

Description
Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn’t
idle for the configured limit. The counter is reset on every state transition.
Set limit while enable is low and then set the enable.

Table 1225.
Bits Description Type Reset
DEV_SM_WATCHDOG
Register
31:21 Reserved. - -

20 FIRED WC 0x0

19 RESET: Set to 1 to forcibly reset the device state machine on watchdog expiry RW 0x0

18 ENABLE RW 0x0

17:0 LIMIT RW 0x00000

12.8. System Timers

12.8.1. Overview
The system timer peripheral on RP2350 provides a microsecond timebase for the system, and generates interrupts
based on this timebase. RP2350 has two instances of the system timer: TIMER0 and TIMER1. This allows for two
separately controlled timers, each in a different security domain. It supports the following features:

• A single 64-bit counter, incrementing once per microsecond

◦ Read from a pair of latching registers for race-free reads over a 32-bit bus
• Four alarms that match on the lower 32 bits of the counter and generate IRQ on match
The timer uses a one microsecond reference generated by the tick generators (see Section 8.5), and derived from the
reference clock (Figure 32), which itself is usually connected directly to the crystal oscillator (Section 8.2).

The 64-bit counter effectively cannot overflow (thousands of years at 1 MHz), so the system timer is completely

12.8. System Timers 1176

RP2350 Datasheet

monotonic in practice.

12.8.1.1. Changes from RP2040

• RP2350 now has two timer instances: TIMER0 and TIMER1

• On RP2350, the tick source for each timer comes from the system-level tick generators (see Section 8.5)
• RP2350 added two new registers: LOCKED is used to disable write access to the timer, and SOURCE allows the timer to
count system clock cycles rather than a 1 μs tick

12.8.1.2. Other Timer Resources on RP2350

The system timer provides a global timebase for software. RP2350 has a number of other programmable counter
resources which can provide regular interrupts, or trigger DMA transfers.

• The PWM (Section 12.5) contains 12× 16-bit programmable counters. These counters:
◦ run at up to system speed
◦ can generate interrupts to either of two system IRQ lines
◦ can be continuously reprogrammed via the DMA
◦ can trigger DMA transfers to other peripherals
• 12× PIO state machines (Chapter 11) can count 32-bit values at system speed, and generate interrupts.
• The DMA (Section 12.6) has four internal pacing timers which trigger transfers at regular intervals.
• Each Cortex-M33 core (Section 3.7) has a standard 24-bit SysTick timer, counting either the microsecond tick
(Section 8.5) or the system clock.

• SIO has a standard 64-bit RISC-V platform timer (Section 3.1.8). Arm and RISC-V software can use this timer.
• The Power Manager (Chapter 6) incorporates a 64-bit timer (AON Timer) which nominally counts milliseconds (see
Section 12.10). This is the only timer that runs when the chip is in its lowest power state, with all switchable power
domains powered down. It is used to schedule power-ups.

12.8.2. Counter
The timer has a 64-bit counter, but RP2350 only has a 32-bit data bus. This means that the TIME value is accessed
through a pair of registers. These are:

• TIMEHW and TIMELW to write the time

• TIMEHR and TIMELR to read the time
To use these pairs, access the lower register, L, followed by the higher register, H. In the read case, reading the L register
latches the value in the H register to provide an accurate time. To read the raw time without any latching, use TIMERAWH
and TIMERAWL.

 CAUTION

Don’t write to the TIMEHW and TIMELW registers to force a new time value if other software may be using the timer. The
SDK uses the time value for timeouts, elapsed time, and more, and expects the value to increase monotonically.

12.8.3. Alarms
The timer has 4 alarms, and outputs a separate interrupt for each alarm. The alarms match on the lower 32 bits of the

12.8. System Timers 1177

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64-bit counter, which means they can be fired at a maximum of 232 microseconds into the future. This is equivalent to:

• 2 ÷ 10 : ~4295 seconds
32 6

• 4295 ÷ 60: ~72 minutes

 NOTE

This timer supports alarm intervals on the order of one microsecond to one hour. For a longer alarm, see Section
12.10.

To enable an alarm:

1. Enable the interrupt at the timer with a write to the appropriate alarm bit in INTE (e.g. (1 << 0) for ALARM0).

2. Enable the appropriate timer interrupt at the processor (see Section 3.2).

3. Write the time you would like the interrupt to fire to ALARM0 (i.e. the current value in TIMERAWL plus your desired alarm
time in microseconds). Writing the time to the ALARM register sets the ARMED bit as a side effect.

Once the alarm has fired, the ARMED bit clears to 0. To clear the latched interrupt, write a 1 to the appropriate bit in INTR.

12.8.4. Programmer’s Model

 NOTE

The timer’s tick (see Section 8.5) must be running for the timer to start counting. The SDK starts this tick as part of
the platform initialisation code.

12.8.4.1. Reading the time

 NOTE

Time here refers to the number of microseconds since the timer was started, not a clock. For a clock, see Section
12.10.

To read the 64-bit time, read TIMELR followed by TIMEHR. Reading TIMELR latches (stops) the value in TIMEHR until TIMEHR is
read. Because RP2350 has 2 cores, it is unsafe to do this if the second core executes code that can also access the
timer, or if the timer is read concurrently in an IRQ handler and in thread mode. If one core reads TIMELR followed by
another core reading TIMELR, the value in TIMEHR isn’t necessarily accurate. The example below shows the simplest form
of getting the 64-bit time:

Pico Examples: https://github.com/raspberrypi/pico-examples/blob/master/timer/timer_lowlevel/timer_lowlevel.c Lines 15 - 23

15 // Simplest form of getting 64 bit time from the timer.

16 // It isn't safe when called from 2 cores because of the latching
17 // so isn't implemented this way in the sdk
18 static uint64_t get_time(void) {
19 // Reading low latches the high value
20 uint32_t lo = timer_hw->timelr;
21 uint32_t hi = timer_hw->timehr;
22 return ((uint64_t) hi << 32u) | lo;
23 }

The SDK provides a time_us_64 function that uses a more thorough method to get the 64-bit time, which makes use of
the TIMERAWH and TIMERAWL registers. The RAW registers don’t latch, making time_us_64 safe to call from multiple cores at
once.

12.8. System Timers 1178

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SDK: https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_timer/timer.c Lines 57 - 73

57 uint64_t timer_time_us_64(timer_hw_t *timer) {

58 // Need to make sure that the upper 32 bits of the timer
59 // don't change, so read that first
60 uint32_t hi = timer->timerawh;
61 uint32_t lo;
62 do {
63 // Read the lower 32 bits
64 lo = timer->timerawl;
65 // Now read the upper 32 bits again and
66 // check that it hasn't incremented. If it has loop around
67 // and read the lower 32 bits again to get an accurate value
68 uint32_t next_hi = timer->timerawh;
69 if (hi == next_hi) break;
70 hi = next_hi;
71 } while (true);
72 return ((uint64_t) hi << 32u) | lo;
73 }

12.8.4.2. Set an alarm

The standalone timer example, timer_lowlevel, demonstrates how to set an alarm at a hardware level without the
additional abstraction over the timer provided by SDK. To use these abstractions, see Section 12.8.4.4.

Pico Examples: https://github.com/raspberrypi/pico-examples/blob/master/timer/timer_lowlevel/timer_lowlevel.c Lines 27 - 74

27 // Use alarm 0
28 #define ALARM_NUM 0
29 #define ALARM_IRQ timer_hardware_alarm_get_irq_num(timer_hw, ALARM_NUM)
30
31 // Alarm interrupt handler
32 static volatile bool alarm_fired;
33
34 static void alarm_irq(void) {
35 // Clear the alarm irq
36 hw_clear_bits(&timer_hw->intr, 1u << ALARM_NUM);
37
38 // Assume alarm 0 has fired
39 printf("Alarm IRQ fired\n");
40 alarm_fired = true;
41 }
42
43 static void alarm_in_us(uint32_t delay_us) {
44 // Enable the interrupt for our alarm (the timer outputs 4 alarm irqs)
45 hw_set_bits(&timer_hw->inte, 1u << ALARM_NUM);
46 // Set irq handler for alarm irq
47 irq_set_exclusive_handler(ALARM_IRQ, alarm_irq);
48 // Enable the alarm irq
49 irq_set_enabled(ALARM_IRQ, true);
50 // Enable interrupt in block and at processor
51
52 // Alarm is only 32 bits so if trying to delay more
53 // than that need to be careful and keep track of the upper
54 // bits
55 uint64_t target = timer_hw->timerawl + delay_us;
56
57 // Write the lower 32 bits of the target time to the alarm which
58 // will arm it
59 timer_hw->alarm[ALARM_NUM] = (uint32_t) target;

12.8. System Timers 1179