WHAT IS STA?
Static timing analysis (STA) is a method of validating the timing performance of a design by checking
all possible paths for timing violations. STA breaks a design down into timing paths, calculates the
signal propagation delay along each path, and checks for violations of timing constraints inside the
design and at the input/output interface.
Another way to perform timing analysis is to use dynamic simulation, which determines the full
behavior of the circuit for a given set of input stimulus vectors. Compared to dynamic simulation,
static timing analysis is much faster because it is not necessary to simulate the circuit's logical
operation. STA is also more thorough because it checks all timing paths, not just the logical
conditions that are sensitized by a set of test vectors. However, STA can only check the timing, not
the functionality, of a circuit design.