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CITE-Cp E-Introduction to HDL Syllabus 2022-2023

Introduction to Linguistics (De La Salle Lipa)

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First Semester SY 2024-2025

COMPUTER ENGINEERING

Vision-Mission

Inspired by our faith in God, by our Catholic traditions, and by the charism of St. John Baptist De La Salle, educational innovator par excellence, we, together and by association, are
committed to give quality human and Christian education to all, building a society founded on equity and justice and on sustainable and inclusive development.

Course Title: Introduction to HDL

Course Code: INTHDL

No. of Units: 1

Prerequisite: Proglad, Funelecs

Course Description:

In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most
commonly, digital logic circuits. This is a laboratory course that introduces hardware description language as a tool for designing and testing combinational and sequential circuits. It
covers fundamental of concepts of HDL and the basic building blocks of HDL programming.

Institutional Learning Outcomes (ILO)

Competent Professional

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1. [CCP3] Demonstrates honesty and fairness in the practice of profession.

2. [CCP2] Adheres and practices to the ethical standard of the profession.

Critical and Innovative Thinker

1. [CIT1] Applies concepts, theories, methods, and processes appropriate to real life situations.
2. [CIT2] Explores alternative schemes and solutions to address various needs and problems of the society.

Life-long Learner
1. [LLL1] Engages in various forms of learning for professional growth.
2. [LLL4] Undertakes research to provide solutions to issues and challenges in society.
Christ Centered Person
1. [CCP3] Demonstrates honesty and fairness in the practice of profession.

Socially Responsible Citizen

1. [SRC3] Develops and practices intra and interpersonal skills in promoting inclusion (race, gender and ethnicity).

Program Learning Outcomes

1. [PLO4] Apply knowledge of mathematics and sciences to solve complex engineering problems.
2. [PLO5] Develop and conduct appropriate experimentation, analyze and interpret data.
3. [PLO6] Recognize ethical and professional responsibilities in engineering practice.
4. [PLO9] Recognize the need for additional and engage in life-long learning.
5. [PLO5] Identify, formulate and solve complex problems in Engineering.
6. [PLO12] Demonstrate knowledge and understanding of engineering and management principles as a member and/or leader in a team to manage projects in multidisciplinary
environments.

Course Learning Outcome

Knowledge
1. [CLO1] Summarize VSIC Hardware Description Language elements.
2. [CLO2] Classify valid sequential statements and expressions.
3. [CLO3] Outline categories of types in VHDL.
4. [CLO4] Outline predefined and user-define types.
Skills
5. [CLO7] Enter a design into the CAD system.
6. [CLO8] Compile the design into a selected device.
7. [CLO9] Simulate the functionality and timing of the resulting circuit.
8. [CLO10] Implement the designs in actual devices using FPGA Trainer.
Lasallian Values
9. [CLO5] Examine and prioritize the social impact of the final output.
10. [CLO6] Explain and defend the output solution.
Modules Learning Outcomes Topics Week No. Borderfree++ Learning Activities and Assessments
Integration Materials
(Essential Skills and
Values, SIF, and SDG)

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• Providing comprehensive • Formative

Module 1 1. Summarize the 1. A VHDL Refresher Week 1-2 SIF: Global Issues
concept of VHDL. 1.1 What is VHDL?
2. Review the main 1.2 Levels of Abstraction in SDGs: and interactive lectures Assessment 1
constructs used in the Digital System
creation of synthesizable 1.3 Summary of VHDL SDG#9: Industry, • Canvas Playlist • Graded Task 1
VHDL designs. Innovation, and
3. Familiarize the theory of 2. Design and Infrastructure
design Architecture 2.1 What is • Video Presentation
Design?

• Lecture and Online

4. Introduce the topics of 2.2 Architecture SDG#11: Sustainable
design and architecture 2.3 Basic Design Loop Cities and Communities
and discuss the main Discussions
qualities directly related 3. Design Principles
to source code. 3.1 Modularity • Canvas Homework and
5. Analyze the main factors 3.2 Abstraction
Activities
that negatively affect
the 4. Statements,
quality of source code, Declarations, and
keeping the code Expressions
checked to make it more
intellectually 5. Operators, Operands,
manageable. and Attributes
6. Introduce the principle of
modularity that a
system
should be designed as a
number of modules that
work as independently as
possible.
7. Introduce the basic
constructs used in VHDL
code with a discussion
about statements,
elements and behavior in
any program.
8. Describe and use
operators, operands and
attributes.
[CLO 1]

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• Providing comprehensive • Formative

Module 2 1. Learn the VHDL type 6. Categories of Types in VHDL Week 3 SIF: Global Issues
hierarchy.
2. Explains how types are 7. Predefine and User- SDGs: and interactive lectures Assessment 2
organized in VHDL. Define Types
3. Define and make use of SDG#9: Industry, • Canvas Playlist • Summative
objects and classes. 8. VHDL Data Objects Innovation, and
Assessment 1
4. Introduce logic functions Infrastructure
and circuits. 9. Introduction to Logic • Video Presentation
5. Learn Boolean algebra Circuits 9.1 Synthesis using SDG#11: Sustainable
for dealing with logic AND, OR, and NOT Gates Cities and Communities
function. • Lecture and Online
6. Learn logic gates and Discussions
synthesis of simple
circuits.
• Canvas Homework and
7. Use CAD tools and the
VHDL hardware
description language. Activities
[CLO 2]

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• Providing comprehensive • Formative

Module 3 1. Learn the commonly 10. Combinational-Circuit Week 4 SIF: Global Issues
used combinational Building Blocks
subcircuits. 10.1 Multiplexers SDGs: and interactive lectures Assessment 3
2. Describe multiplexers, 10.2 Decoders/Encoders
which can be used for 10.3 Code Converters SDG#9: Industry, • Canvas Playlist • Graded Task 2
selection of signals and Innovation, and
for implementation of 11. Flip-flops, Registers, Infrastructure
general logic function. Counters, and a Simple • Video Presentation
3. Make use of circuits used Processor SDG#11: Sustainable
for encoding, decoding, Cities and Communities
and code conversion • Lecture and Online
purposes. Discussions
4. Analyze the key VHDL
constructs used to define
• Canvas Homework and
combinational circuits.
5. Learn about logic circuits
that can store Activities
information.
6. Understand flip-flops,
which store a single bit.
7. Understand registers,
which store multiple bits.
8. Understand Shift
registers which shift the
contents of the register.
9. Use counters of various
types.
10. Use VHDL constructs
to implement storage
elements.
11. Design a small
subsystem.

[CLO 3]

• Providing comprehensive • Formative

Module 4 1. Learn the design Synchronous Sequential Week 5 SIF: Global Issues
techniques for circuits Circuits
that use flip-flops SDGs: and interactive lectures Assessment 4
2. Outline the concept of 12. Basic Design Steps
states and their 12.1 State diagram SDG#9: Industry, • Canvas Playlist • Summative
implementation with flip 12.2 State Table Innovation, and
Assessment 2
flops 12.3 State Assignment Infrastructure
3. Describe synchronous • Video Presentation
control by using a clock SDG#11: Sustainable
signal Cities and Communities
4. Explain the concept of • Lecture and Online
finite state machines Discussions
[CLO 7, 8, 9]

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• Canvas Homework and

Activities

5. Learn the VHDL

specification of
sequential circuits

• Providing comprehensive • Formative

Module 5 1. Learn sequential circuits Asynchronous Week 6 SIF: Global Issues
that are not Sequential Circuits
synchronized SDGs: and interactive lectures Assessment 5
by a clock. 13. Asynchronous
2. Analyze asynchronous Behavior 14. State SDG#9: Industry, • Canvas Playlist • Graded Task 3
sequential circuits. Assignment Innovation, and
3. Explain the concept of Infrastructure
stable and unstable 15. State Reduction • Video Presentation
states. SDG#11: Sustainable
4. Determine the hazards 16. Hazards Cities and Communities
that cause incorrect • Lecture and Online
behavior of a circuit. Discussions
[CLO 7, 8, 9]

• Canvas Homework and

Activities

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• Providing comprehensive • Formative

Module 6 1. Enable inputs for flip Digital System Design Week 7-9 SIF: Global Issues
flops, registers and shift
registers. 17. Building block circuits SDGs: and interactive lectures Assessment 6
2. Analyze static random
access memory blocks. 18. Design Examples SDG#9: Industry, • Canvas Playlist • Summative
Innovation, and
Assessment 3
[CLO 10, 5, 6] 19. Clock Synchronization Infrastructure
• Video Presentation
(CAPSTONE)
SDG#11: Sustainable
Cities and Communities
• Lecture and Online
Discussions

• Canvas Homework and

Activities

References/Suggested Readings

1. Effective Coding with VHDL Principles and Best Practice by Ricardo Jasinski
2. Fundamentals of Digital Logic with VHDL Design, Second Edition by Stephen Brown and Zvonko Vranesic

Grading System

Below are the course requirements and bases for final grade computation.
Course Requirements Number Mode of Points
Administration
of
Assessment*

Modules 6 -- --

Graded Tasks (GTs) 3 GTs: Asynchronous 30

Major Assessments (MAs) 2 Prelim & Final: 70

Asynchronous

Total points (Canvas grade) 100

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*Sample only.

The Canvas grade is transmuted to 60% base which will then be assigned a grade point equivalent and letter grade using the following table.
Point % Ranges Grade-point Letter
Ranges Equivalent Grade

96 - 100 98% - 100% 4.00 A

92 – 95 95% - 97% 3.75 A

87-91 92% - 94% 3.50 B+

82 – 86 89% - 91% 3.25 B

77 – 81 86% - 88% 3.00 B

72 – 76 83% - 85% 2.75 C+

68 – 71 80% - 82% 2.50 C

63 – 67 77% - 79% 2.25 C

60 – 62 75% - 76% 2.00 D

0 – 59 65% - 74% 0.00 F

Prepared by: Noted and Approved:

Engr. Imelda R. Martin Engr. Mary Lou Teñoso Program/Learning Area Chair

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