Prestige Institute of Management and Research, Bhopal

Department of Electronics and Communication Engineering

B.Tech III Semester Computer Science Engg. Session: July -Dec 2024
Course: CS 304 Digital Systems

Assignment –1 (C304.1)
Q.1 Convert the following Decimal numbers into their Binary equivalents:
i. 53.625
ii. 255.0625
iii. 124.125
iv. 1024.5125
Q. 2 Convert the following Binary numbers into their Decimal equivalents:
i. 110110.0011
ii. 101110.11011
iii. 111111.1101
iv. 1110111.1101
Q.3 Convert the following Decimal numbers into their Octal and Hexadecimal equivalents:
i. 564.886
ii. 255.654
iii. 124.665
iv. 888.88
Q4. Convert the following Binary numbers into their Octal and Hexadecimal equivalents:
i. 11010101.11001101
ii. 1100.0111
iii. 111101010101.0001
iv. 111111111.111111
Q.5. Obtain the BCD codes for following decimal numbers:
i. 456.78
ii. 125.15
iii. 654.43
iv. 999.888
Q.6. Obtain the Gray codes for following Binary numbers:
i. 11001101111
ii. 1011011101
iii. 111100011
iv. 101010101010
 Prestige Institute of Management and Research, Bhopal
Department of Electronics and Communication Engineering
B.Tech III Semester Computer Science Engg. Session: July -Dec 2024
Course: CS 304 Digital Systems

Assignment –2 (C304.1)

Q. 1. Simplify the following Boolean expressions:

i.) x' + y' + xyz'

ii.) xy + wxyz' + x'y

Q. 2. Simplify the following Boolean expressions:

i) AB'C' + A'BC + A'B'C'

ii) ((AB + ABC )' + A(B + AB'))'

Q.3 Obtain the Truth Tables for following functions:

i) F = A'B'C + A + BC
ii) F = ABC + BC'D + A'BC
iii) f = XY + XZ

Q.4 . Given A'B + A'B = C , show that A'C + AC' = B

Q. 5. Determine the Canonical SOP and POS expressions for:

i ) x + x'y' + x'z
ii ) C + (A'+ B)(A + B')
iii) xy +y'z' + wxz'
iv) w'x' + x'y' + w'z' + yz

Q.6. Find the complement of each of the following expressions and then simplify them:

i) x'(y' + z' )(x + y + z')

ii) (x + y'z' )(y + x'z' )(z + x'y' )
 Prestige Institute of Management and Research, Bhopal
Department of Electronics and Communication Engineering
B.Tech III Semester Computer Science Engg. Session: July -Dec 2024
Course: CS 304 Digital Systems

Assignment –3 (C304.2)
Q.1. With the aid of four-variable K-map, derive minimal SOP and minimal POS expressions for
each of the following functions:

i) f(w,x,y,z) = ∑ (0,1,2,3,4,6,8,9,10,11)

ii) f(w,x,y,z) = ∑ (0,1,2,5,7,8,10,14,15)

iii) f(w,x,y,z) = ∑ (0,1,2,5,7,8,10,14,15)

Q.2. With the aid of four-variable K-map, derive minimal SOP and minimal POS expressions for
each of the following functions:

i) f(w,x,y,z) = ∑ (0,2,4,9,12,15) + ∑d( 1,5,7,10)

ii) f(w,x,y,z) = ∑ (1,2,3,5,13) + ∑d(6,7,8,9,11,15)

iii) f(w,x,y,z) = ∑ (1,5,6,12,13,14) + ∑d( 2,4)

Assignment –4 (C304.2)

Q.1. Prove that NAND and NOR are Universal operations.

Q.2. Show that the set of EXCLUSIVE OR and AND operations form a Universal Operation
set.

Q.3 Prove that T (x,y ) = xy' , is a Universal operation fuction.

Q.4. Implement the following using only NAND and only NOR Gates:

i ) Exclusive-OR Gate
ii ) Exclusive-NOR Gate

Q.5. Implement a Full Adder using two Half Adders and an OR Gate.

Q6. Design a Full Adder using only NAND Gates.

 Prestige Institute of Management and Research, Bhopal
Department of Electronics and Communication Engineering
B.Tech III Semester Computer Science Engg. Session: July -Dec 2024
Course: CS 304 Digital Systems
Assignment – 5 (C304.3)
Q.1. Differentiate between Latch and Flip-Flop.

Q2. With the help of Characteristic Tables, explain the operations of:
i) S -R FF
ii) J-K FF
iii) D type FF
iv) T type FF

Q.3. What is Race-around Problem? Explain, how is it removed in Master-Slave FFs.

Q.4. Give circuit diagrams to implement T-Type FF using (i) J-K FF(ii) D-Type FF

Q.5. Give circuit diagrams to implement D-Type FF using (i) J-K FF(ii) S-R -Type FF.

Q6. Draw the logic diagram and explain the working of Master Slave Flip Flop.

Assignment – 6 (C304.3)
Q.1. Write a brief note on:
i) Multiplexer
ii) Demultiplexer
iii) Decoder
iv) Encoder

Q.2. What do you understand by Priorty Encoders?

Q. 3 Design a Full Adder using 8:1 Multiplexer.

Q4. Realize the following functions of 4-variables using:

8:1 Multiplexers:
f(w,x,y,z) = ∑ (0,1,2,3,4,6,8,9,10,11)

Q5. Realize the function in Q 4 using 16:1 Multiplexers

Q6. Realize the function in Q 4 using 4-to-16 decoder

 Prestige Institute of Management and Research, Bhopal
Department of Electronics and Communication Engineering
B.Tech III Semester Computer Science Engg. Session: July -Dec 2024
Course: CS 304 Digital Systems

Assignment – 7 (C304.4)
Q. 1 With the help of logic diagrams explain the working of:
i) 4-bit Shift Left Register
ii) 4-bit Shift Right Register
iii) 4-Bit Bidirectional Shift Register

Q.2. With the aid of Logic Diagram explain the working of a 4-bit Universal Shift Register.

Q4. Draw the Logic Diagram of a 4-bit Ripple Counter (count up ) and explain it.

Q.5. Draw the Logic Diagram of a 4-bit Synchronous UP/DOWN Counter and explain its working.

Q.6. Draw the Logic Diagram of a Decade Counter and explain it.

Assignment – 8 (C304.4)
Q1 Explain the parameters used to characterize logic family

Q2 Describe major difference between a bipolar integrated circuit & MOS integrated CKT

Q3 Why ECL Logic is faster than TTL

Q4 Discuss why wired logic should not be used with active pull up outputs

Q5 Why CMOS switching speed is greater than NMOS/PMOS

Q6 Explain the purpose of totem Pole output stage used in TTL gate
 Prestige Institute of Management and Research, Bhopal
Department of Electronics and Communication Engineering
B.Tech III Semester Computer Science Engg. Session: July -Dec 2024
Course: CS 304 Digital Systems

Assignment – 9 (C304.5)

Q.1 Differentiate between:

i) Main and Secondary Memories
ii) Static and Dynamic Memories
iii) Volatile and Non-volatile Memories
iv) RWM and ROM
v) Random and Sequential Access Memories

Q.2. Draw the circuit diagrams and explain the followings:

i) Bipolar RAM Cell
ii) MOS RAM Cell

Q.3. Write short notes on :

i) PROM
ii) EPROM
iii) EEPROM

Q4. With the help of Timing Diagrams, Explain the READ and WRIRE operations of
Semiconductor Memories.

Q5. Explain PLA.

Assignment – 10 (C304.5)

Q1. Why the input variables to a PAL are buffered.

Q2. Give the comparison between PROM and PLA.
Q3. What is meant by PLA? Draw a block diagram & explain its working.
Q4. Explain FPGA
Q5. How the capacity of a PLA is specified.
Q6. Explain ROM & It’s working. How it is different from PLA