Question:
Interfacing 32KB memory with the 8086 in both Minimum Mode and Maximum Mode,
including memory mapping, chip selection, control signals, and circuit diagrams.
Solution:
1. Memory Interfacing with 8086 in Minimum Mode
Step 1: Memory Size and Address Range Calculation
Given Memory Size: 32KB = 2^15 locations.
8086 Address Bus: 20-bit (A0 to A19).
Address Range Required: 00000H−07FFFH
Memory Organization:
o We use 8KB memory chips (2^13 locations each).
o 4 Chips are required to get 32KB.
o Each chip has a unique chip select (CS̅ ) based on address decoding.
Step 2: Address Decoding (Using 74LS138 Decoder)
Address lines A0-A12: Connect directly to the memory chip's address inputs.
Address lines A13, A14: Used for chip selection.
Address lines A15-A19: Not needed (all zeros for this address range).
Address Range A14 A13 Selected Chip
00000H-01FFFH 0 0 Chip 1 (8KB)
02000H-03FFFH 0 1 Chip 2 (8KB)
04000H-05FFFH 1 0 Chip 3 (8KB)
06000H-07FFFH 1 1 Chip 4 (8KB)
The 74LS138 (3-to-8 decoder) uses A13 and A14 to activate one of the four memory
chips.
Step 3: Control Signals in Minimum Mode
In Minimum Mode (MN/MX̅ = 1), the 8086 directly generates control signals:
RD̅ (Read)
WR̅ (Write)
M/IO̅ (Memory or I/O selection) → Memory Access = 0
AEN̅ (Address Enable)
Memory Read Operation
1. Address placed on the address bus.
2. 8086 sets M/IO̅ = 0 (indicating memory operation).
3. RD̅ activated (0) to read from memory.
4. Selected memory chip places data on the data bus.
5. RD̅ deactivated after reading.
Memory Write Operation
1. Address placed on the address bus.
2. 8086 sets M/IO̅ = 0.
3. WR̅ activated (0) to write to memory.
4. Data written to the memory chip.
5. WR̅ deactivated after writing.
Step 4: Circuit Diagram for Minimum Mode
A0-A12: Directly connected to all memory chips.
A13, A14: Connected to 74LS138 decoder to generate CS̅ .
RD̅ and WR̅ : Connected to memory chips.
M/IO̅ : Set to 0 for memory operation.
2. Memory Interfacing with 8086 in Maximum Mode
Step 1: Maximum Mode Selection
Set MN/MX̅ = 0 to enable Maximum Mode.
The 8086 does not generate control signals directly.
An 8288 Bus Controller generates:
o MRDC̅ (Memory Read Command)
o MWTC̅ (Memory Write Command)
o DEN̅ (Data Enable)
o ALE (Address Latch Enable)
Step 2: Address Decoding in Maximum Mode
Addressing remains the same as in Minimum Mode.
A0-A12: Connected to memory chips.
A13, A14: Used to enable one of the four 8KB chips using 74LS138 decoder.
Step 3: Control Signals in Maximum Mode
The 8086 generates status signals:
o S2, S1, S0 (Bus cycle type)
8288 Bus Controller decodes these into control signals:
o MRDC̅ (Read from Memory)
o MWTC̅ (Write to Memory)
o IORC̅ , IOWC̅ (For I/O, not used here)
Memory Read Operation
1. Address placed on the address bus.
2. 8086 sets S2, S1, S0 for memory read.
3. 8288 decodes and generates MRDC̅ .
4. Selected memory chip places data on the bus.
5. Data read, MRDC̅ deactivates.
Memory Write Operation
1. Address placed on the address bus.
2. 8086 sets S2, S1, S0 for memory write.
3. 8288 generates MWTC̅ .
4. Data written to the memory chip.
5. MWTC̅ deactivates.
Step 4: Circuit Diagram for Maximum Mode
A0-A12: Directly connected to all memory chips.
A13, A14: Connected to 74LS138 decoder for chip selection.
S2, S1, S0: Connected to 8288 Bus Controller.
MRDC̅ & MWTC̅ : Connected to memory chips.
