continuous signal representations.

vector: Represents multi-bit signals module identifier_usage;

Overview of Verilog like buses or registers. Packed Arrays: Used for arrays of contiguous // Valid identifiers
bits, such as vectors or buses. Unpacked Arrays: Used for arrays of reg [7:0] data_out; // register for output data
OPERATORS:
individual registers or wires, not contiguous. wire clk_1; // wire for clock signal
Arithmetic operators, Relational operators, Logical operators, Bitwise module data_types_example; reg reset_signal; // register for reset signal
operators, Shift operators, Reduction operators, Concatenation and // Wire Data Type integer counter; // integer for counting operations
Replication, Conditional operator wire [7:0] wire_data; // Represents a physical connection parameter WIDTH = 8; // constant for width (parameter)
module operators_example; (combinational net) // Invalid identifier
// Declare variables wire [7:0] data_out; // Represents another wire connection reg 1data_out; // Error: Cannot start with a digit
reg [3:0] a = 4'b1010; // 10 in decimal tri [7:0] tri_data; // Tri-state wire (can be high impedance) reg module; // Error: 'module' is a reserved keyword
reg [3:0] b = 4'b0101; // 5 in decimal wand [7:0] and_data; // Logical AND between multiple drivers
reg select = 1'b1; // Select signal for conditional operator wor [7:0] or_data; // Logical OR between multiple drivers KEYWORDS:
wire [3:0] arithmetic_result, bitwise_result, shift_result; // Reg Data Type
wire [7:0] concat_result, replicate_result; reg [7:0] reg_data; // 8-bit register (stores values) and always assign attribute begin
wire equal, not_equal, less, greater; reg [7:0] counter; // 8-bit counter register buf bufif0 bufif1 case cmos
wire logical_and, logical_or, logical_not; reg reset; // Register for reset control deassign default defparam disable else
reg [3:0] reg_count; // 4-bit counter for testing endattribute end endcase endfunction endprimitive
wire reduction_and, reduction_or, reduction_xor;
// Parameter Data Type endmodule endtable endtask event force
// Arithmetic operators
parameter WIDTH = 8; // Constant for width (fixed value) forever fork function highz0 highz1
assign arithmetic_result = a + b - (a * b) / b; // Combines +, -, *, /
parameter MAX_COUNT = 15; // Max counter value for comparison if initial inout input integer
// Relational operators
// Integer Data Type join large medium module nand
assign equal = (a == b); // Equality
integer count; // 32-bit signed integer negedge nor not notif0 notif1
assign not_equal = (a! = b); // Inequality
integer sum; // Integer to store sum of values nmos or output parameter pmos
assign less = (a < b); // Less than
// Time Data Type posedge primitive pulldown pullup pull0
assign greater = (a > b); // Greater than
time clk_time; // Simulation time variable pull1 rcmos reg release repeat
// Logical operators rnmos rpmos rtran rtranif0 rtranif1
assign logical_and = (a[0] && b[0]); // Logical AND // Real Data Type
real voltage; // Floating-point value for representing voltage scalared small specify specparam strong0
assign logical_or = (a[0] || b[0]); // Logical OR strong1 supply0 supply1 table task
assign logical_not = !(a[0]); // Logical NOT // Vector Data Type
reg [15:0] data_bus; // Represents a 16-bit bus (multi-bit register) tran tranif0 tranif1 time tri
// Bitwise operators triand trior trireg tri0 tri1
assign bitwise_result = (a & b) | (~a ^ b); // Combines &, |, ~, ^ reg [7:0] data_array [0:3]; // Array of 4 8-bit elements (packed array)
// Unpacked Array Data Type vectored wait wand weak0 weak1
// Shift operators while wire wor for
assign shift_result = (a << 1) | (b >> 1); // Combines <<, >> reg [7:0] unpacked_array [0:3]; // Non-contiguous elements
// Reduction operators (unpacked array)
assign reduction_and = &a; // Reduction AND // Integer Array Data Type FORMAT SPECIFICATIONS IN VERILOG:
assign reduction_or = |b; // Reduction OR integer int_array [0:3]; // Array of integers
assign reduction_xor = ^a; // Reduction XOR // Real Array Data Type %d Display an integer in decimal format.
// Concatenation and Replication real real_array [0:3]; // Array of real (floating-point) values %o Display an integer in octal format.
assign concat_result = {a, b}; // Concatenation // String Data Type %h Display an integer in hexadecimal format. %h and %x behave
assign replicate_result = {4{b [0]}}; // Replication string message; // String data type (text) or identically.
// Conditional operator // Event Data Type %x
wire [3:0] conditional_result; event event_trigger; // Event data type for triggering procedural %b Display an integer in binary format.
assign conditional_result = select? a: b; blocks %c Display the ASCII character corresponding to an integer.
%s Display a string.
INDENTIFIERS: %e Display a real number in exponential notation.
DATATYPES: %f Display a real number in floating-point format.
In Verilog, identifiers are names used to represent variables, registers, %g Display a real number in the shorter of exponential or floating-
Wire(net): Used for connecting elements in combinational logic. Its value
wires, modules, functions, tasks, parameters, and other elements within point format.
is driven by external sources.reg: Used to store values in sequential logic
%t Display the current simulation time.
(e.g., inside always blocks). parameter: Used for defining constant values the design. An identifier must follow specific rules to be valid in Verilog:
%m Display the hierarchical name of the module where the task is
that do not change throughout the simulation. integer: A 32-bit signed Must begin with an alphabet (a-z, A-Z) or underscore (_).
executed.
number used for mathematical operations or counters. Time: Followed by alphabets, digits (0-9), or underscores. %p Display complex data structures such as unpacked arrays or
Used to represent and track simulation time, typically for delays or Cannot use Verilog keywords as identifiers. structures.
timing analysis. Real: Used for floating-point values, often for analog or Case-sensitive (e.g., data and Data are different). %u Display unformatted 2- and 4-value data.
Should not include spaces or special characters (#, @, etc.). ,%z
NUMBER REPRESENTATION IN VERILOG Methods of Connecting Ports GATE DELAYS IN VERILOG
Ordered Connection: The ports are connected in the same order as
Signed and Unsigned Numbers
defined in the module declaration. This method is simpler but can Delays refer to the time it takes for a signal to propagate through a gate
Signed Numbers: Represent positive and negative values using two's
become error-prone in complex designs. or from one component to another. Delays can affect the overall
complement. MSB indicates the sign (0 for positive, 1 for negative).
module mux_2_1(input sel, input i0, i1, output y); performance and timing of a system, and they are critical in both
Unsigned Numbers: Represent only non-negative values.
// Module's logic goes here simulation and synthesis.
reg signed [7:0] signed_num = -8; // Signed
endmodule Propagation delay: Rise and Fall Delays for Gates (Gate-Level
reg [7:0] unsigned_num = 8; // Unsigned
module mux_tb; Modeling):
Numerical Bases
reg in0, in1, select; Rise Delay: The time it takes for the output to transition from low to
Binary: [size]'b[number] (e.g., 4'b1010)
wire out; high.
Decimal: [size]'d[number] (e.g., 4'd10)
mux_2_1 mux(select, in0, in1, out); // Connecting ports in order Fall Delay: The time it takes for the output to transition from high to
Hexadecimal: [size]'h[number] (e.g., 8'hFF)
endmodule low.
Floating-Point Representation
Named Connection: This method is more robust for complex designs. Usage: These delays simulate real-world signal propagation times,
used for precise decimal values with components: sign, exponent, and
Here, the connection is explicitly made by the port names, meaning the where each gate or buffer takes time to change its output.
mantissa.
order of the ports doesn't matter Turn-off Delay in Buffer:
real num = 3.14;
module and_gate(input a, b, output y); Turn-off delay defines the time it takes for the output to go into a high-
$display("Floating-point: %f", num); // Output: 3.140000
assign y = a & b; impedance state (Z), preventing other drivers from affecting the bus.
endmodule module gate_delays();
MODULES AND PORTS IN VERILOG
module or_gate(input a, b, output y); reg in;
assign y = a | b; wire out_single, out_double, out_triple, out_rise, out_fall, out_turn_off,
Modules
endmodule out_min_max;
A module is like a building block for your Verilog design. It represents a
module top_module(input a, b, output and_out, or_out); // Single delay: A simple buffer with one delay value
piece of hardware or a specific function, and it can be connected to
// Instantiating AND gate buf #(5) U_single_delay (out_single, in);
other modules to create a larger system.
and_gate and1 (.a(a), .b(b), .y(and_out)); // Double delay: Using two delays for rise and fall
A module can contain:
// Instantiating OR gate buf #(2, 4) U_double_delay (out_double, in);
Variables, Logic operations, Sub-modules (smaller modules inside a
or_gate or1 (.a(a), .b(b), .y(or_out)); // Triple delay: Using three delays (rise, fall, and turn-off)
bigger one), Tasks and functions (to reuse code)
endmodule endmodule buf #(1, 3, 5) U_triple_delay (out_triple, in);
module declaration
To access signals inside a module instance, Verilog uses dot notation, // Rise and fall delay: Specific delay for each transition type
module my_module(input a, output y);
following the hierarchy. buf #(1, 2) U_rise_fall (out_rise, in);
// Module's logic goes here
dut_top.d3.d2.signal_name // Access a signal inside the dut_2 module buf #(2, 3) U_fall (out_fall, in);
endmodule
// Turn-off delay: A turn-off delay (typically to simulate high-
input a: A signal coming into the module.output y: A signal going out of
GATE-LEVEL MODELLING IN VERILOG impedance state)
the module.
buf #(2, 3, 4) U_turn_off (out_turn_off, in);
Ports
Verilog supports built-in primitives for common logic gates like and, or, // Min and Max delay: Specifying min, typical, and max delay values
Ports are the interfaces through which a module communicates with
xor, nand, nor, xnor, buf (buffer), and not (inverter). These primitives buf #(1:3:5) U_min_max_delay (out_min_max, in);
other modules or external signals. These are the inputs and outputs
can have multiple scalar inputs and typically a single scalar output. //min=1,typical=3,max=5
that allow a module to pass data in and out of its scope. There are three
module half_adder (input A, B, output SUM, CARRY); // Initial block to provide input stimulus and display simulation
types of ports in Verilog:
xor(SUM, A, B); // XOR gate for SUM output
Input port, output port, bidirectional port
and(CARRY, A, B); // AND gate for CARRY initial begin
Port Declarations and Types
endmodule $monitor("Time=%g in=%b | Single=%b Double=%b Triple=%b |
Input ports must be connected to reg or net types externally, but inside
bufif1: Buffer enabled by a control signal (output valid when control is Rise=%b Fall=%b TurnOff=%b MinMax=%b",
the module, they must be of net type.
1). $time, in, out_single, out_double, out_triple, out_rise, out_fall,
Output ports inside a module can be either reg or net, but must be
notif1: Inverter with control signal (output valid when control is 1). out_turn_off, out_min_max);
connected to net types externally.
bufif0 and notif0: Same as above but with inverted control polarity. // Initialize input and apply delays
Inout ports must be connected to net types both internally and
module gates(input a, input ctrl, output c); in = 0; // Initial state
externally.
bufif1 (c, a, ctrl); // Buffer with control signal #10 in = 1; // Transition to high after 10 time units
Instantiating Modules
endmodue #10 in = 0; // Transition back to low after 10 more time units
In bigger designs, you often break the design into smaller modules. To
#20 $finish; // End the simulation
use a module inside another, you instantiate it.
end
<module_name> <instance_name>(.port1(signal1), .port2(signal2), ...);
endmodule
DATA FLOW MODELING IN VERILOG variables, applying stimuli, or setting up simulation conditions in
input wire [3:0] vec2, // 4-bit vector input testbenches.
Dataflow modeling is one of the three main styles of Verilog modeling,
output wire and_out, // Output of AND gate Variable Initialization:
focusing on how data flows between inputs and outputs in a design. In
output wire mux_out, // Output of multiplexer initial a = 2'b10; // Assigns a value at t = 0
this approach, the hardware behavior is described using operators and
output wire delayed_out, // Delayed multiplexer output Applying Delays:
expressions, without having to explicitly specify the individual gates
output wire [4:0] sum, // 5-bit output for adder initial begin
and their connections.
output wire carry // Carry output from adder); a = 2'b10; // At t = 0
Continuous Assignment:
// Explicit Net Declaration with Regular Continuous Assignment #10 b = 1'b0; // At t = 10
The core construct of dataflow modeling is continuous assignment,
wire regular_net; // Explicit net declaration End
which assigns values to nets (wires). It is used to describe
assign regular_net = a & b; // AND gate implemented with Concurrent Execution:
combinational logic. The assign statement continuously drives a value
continuous assignment initial begin
to a wire whenever the expression on the right-hand side (RHS)
// Implicit Net Declaration (implicitly created for `implicit_net`) #20 x = 1;
changes.
assign implicit_net = a | b; // OR gate using implicit net declaration end
assign <net_name> = <expression>;
// Continuous Assignment with Delay (Regular Assignment Delay) initial begin
assign out = a & b; // AND operation in dataflow style
wire delayed_net; // Explicit net declaration #10 y = 0;
Here, assign continuously assigns the result of a & b to the out wire.
assign #10 delayed_net = a ^ b; // XOR gate with 10-time unit delay #40 y = 1;
module adder(a, b, sum);
// Implicit Continuous Assignment with Delay End
input [2:0] a, b;
wire #5 implicit_delayed_net = ~a; // NOT gate with 5-time unit
output [3:0] sum;
delay ALWAYS STATEMENT:
assign sum = a + b;
// Net Declaration Delay The always block in Verilog is a key procedural construct used to
endmodule//Continuous Assignments on Vectors:
wire #8 net_declared_delay; // Delay declared at the time of net model combinational and sequential logic. Its behavior is
Nets:
declaration determined by the sensitivity list and the type of assignments
In Verilog, nets are used to represent connections between hardware
assign net_declared_delay = b; // Assigned without delay at the within it.
elements. Nets do not store values but hold the values driven by
assignment level Combinational Logic
outputs from other components. Common net types include wire, wand,
// Multiplexer using Continuous Assignment always @ (a or b or c) begin//sensitivity list containing all input
trior, and others, with wire being the most commonly used.
assign mux_out = sel ? a : b; // 2:1 Multiplexer signals.
Implicit Continuous Assignment:
assign #12 delayed_out = mux_out; // Adding a delay to multiplexer z = a & b & c;// Use blocking assignments (=)
wire out = a & b; // Implicit continuous assignment
output end
You can directly declare and assign a net without using the assign
// Vector Operations and Concatenation for Adder Sequential Logic
keyword explicitly, making the code more compact.
assign #6 {carry, sum} = vec1 + vec2; // Adding two vectors with 6- always @ (posedge clk or negedge rst) begin//sensitivity to clock
Delays in Continuous Assignment: Verilog allows the inclusion of time unit delay (posedge or negedge).
delays in dataflow assignments to model real-time behavior and timing // Combining Nets and Continuous Assignments for Final Outputs if (!rst)
characteristics. In real-world circuits, there is always a time gap assign and_out = regular_net & implicit_net; // Combining explicit q <= 0;// Use non-blocking assignments (<=).
between input changes and the resulting output. You can model these and implicit nets else
delays in Verilog using the # symbol followed by the delay value. endmodule q <= d;
assign #10 out = a & b; // 10 ns delay in the assignment end
This delay simulates the time it takes for the output out to change after BEHAVIORAL MODELING always #10 clk = ~clk; // Generates a clock signal(Timing control)
inputs a and b change.
Types of Continuous Assignment Delays: Behavioral modeling abstracts the hardware’s functionality, PROCEDURAL ASSIGNMENTS:
Regular Assignment Delay: The delay is explicitly defined after the allowing you to focus on the what instead of the how. This higher Procedural assignments in Verilog are crucial for defining how
assign statement. level of abstraction not only simplifies your design but also variables are updated within procedural block (always, initial,
Implicit Continuous Assignment Delay: The delay is included when accelerates debugging and verification. task, and function)
the net is declared. Blocking Assignments (=):
wire #10 out = a & b; // Delay when the net is declared Behavioral modeling allows for high-level functional descriptions, A blocking assignment is executed sequentially, where each
Net Declaration Delay: Delay is applied during net declaration. simplifying the design process without focusing on hardware details. statement must finish before the next one begins. The LHS (left-
wire #10 out; hand side) of the assignment is updated immediately after
assign out = a & b; INITIAL STATEMENT evaluating the RHS (right-hand side) expression.
module _dataflow ( The initial block in Verilog is a procedural construct used in
input wire a, // Scalar input simulations to execute a set of statements once, starting at
input wire b, // Scalar input simulation time t = 0. It is primarily utilized for initializing
input wire sel, // Selector for multiplexer
input wire [3:0] vec1, // 4-bit vector input
 initial begin #15 -> my_event; // Trigger the named event after 15 time units
data = 4'hA; // blocking assignment reg a, b, o;//reg and net end
$display("Data = %0h", data); // This will show data after it is initial begin always @(my_event) begin
assigned a = 1; b = 0; // Initialize inputs $display("Named event triggered at time %0t", $time); //
end force o = a & b; // Temporarily force o = a & b Display the time of event
endmodule #10 release o; // Release control, o can now be assigned end
RACE-AROUND CONDITION: normally // Event OR Control
when two different procedural blocks attempt to write to the same o = 1; // Procedural assignment resumes always @(posedge clk or negedge reset) begin
register at the same simulation time. Verilog’s blocking end if (!reset)
assignments (=) can cause race conditions because the assignment q <= 0; // Reset the value of `q` to 0 on negative edge of reset
completes immediately, and the simulation might not know which TIMING CONTROL IN VERILOG else
block's value to use when multiple assignments happen reg clk, reset, a, b, c, q, d; q <= d; // Assign the value of `d` to `q` on positive edge of
simultaneously integer i; clock
// Clock Generation: Generates a clock signal with a 10-time unit end
NON-BLOCKING ASSIGNMENT: period // Level-Sensitive Timing Control
initial begin initial begin
A non-blocking assignment allows the RHS expression to be clk = 0; ready = 0;
evaluated immediately, but the LHS update happens at the end of forever #5 clk = ~clk; // Clock toggles every 5 time units #20 ready = 1; // Set `ready` to 1 after 20 time units
the current simulation time slot. This allows other statements to end wait (ready == 1); // Wait until `ready` becomes 1
execute while waiting for the LHS to be updated, which is helpful // Wait Statement: Waits for a condition to become true start = 1; // Set `start` to 1 after `ready` is 1
for modeling sequential logic. initial begin $display("Start triggered at time %0t", $time); // Display the
always @(posedge clk or posedge reset) begin reset = 1; #15 reset = 0; // De-assert reset after 15 time units simulation time
if (reset) begin wait (reset == 0); // Waits until reset is 0 end
q <= 4'b0000; // Reset the register to 0 b = 1; // Executes after the wait condition is met endmodule
end else begin end
q[3] <= q[2]; // Shift data // Non-Blocking Delayed Assignment: Non-blocking assignment CONDITIONAL STATEMENT:
q[2] <= q[1]; with delay if Statement
q[1] <= q[0]; initial begin Used for conditional execution of one or more statements.
q[0] <= din; // Load new data into LSB d <= #30 c; // Assigns `c` to `d` after 30 time units if (condition) begin
end end // Statements to execute if condition is true
end // Inter-Assignment Delay Control end
endmodule initial begin if-else Statement
a = 0; Provides an alternative path of execution when the condition is
PROCEDURAL CONTINOUS ASSIGNMENTS: #10 a = 1; // `a` is set to 1 after 10 time units false.
procedural continuous assignments allow you to temporarily end if (condition) begin
override existing assignments for variables or signals during // Intra-Assignment Delay Control // Statements to execute if condition is true
simulation. initial begin end else begin
assign ... deassign: b = 5; // Statements to execute if condition is false
The value remains constant until the deassign statement is c = #5 b + 2; // Assign `b + 2` to `c` after 5 time units end
executed, after which other assignments can take over. end if-else if-else Statement
reg q//only reg data types // Zero Delay Control Checks multiple conditions sequentially.
initial begin always @(posedge clk) begin if (condition1) begin
$monitor("Time: %0t | q = %b", $time, q); #0 d = a + b; // Execute immediately at the current simulation // Execute if condition1 is true
q = 1; // Procedural assignment assign time end else if (condition2) begin
q = 0; // Temporarily forces q = 0 end // Execute if condition2 is true
#10 deassign q; // Releases control, q = 1 resumes // Named Event Control end else begin
force ... release: initial begin // Execute if none of the conditions are true
Temporarily overrides all other assignments, including end
procedural, continuous, or procedural continuous assignments. Ternary (Conditional) Operator
Allows bit-selects and part-selects A concise way to implement if-else logic.
output_value = (input_signal == 2'b00) ? 4'b0001 : 4'b0010;
case Statement always @(*) begin module (
Used to execute one of many blocks based on the value of a signal. casex (signal_input) input wire clk,
case (expression) 2'bxx: traffic_light = 3'b000; // If signal is unknown (x), turn input wire [3:0] input_signal, // 4-bit input signal
value1: begin off all lights output reg [3:0] counter // 4-bit counter
// Statements for value1 2'b00: traffic_light = 3'b100; // Green light );
end 2'b01: traffic_light = 3'b010; // Yellow light // Variables for loop control
value2: begin 2'b10: traffic_light = 3'b001; // Red light integer i;
// Statements for value2 default: traffic_light = 3'b000; // Default case, turn off all // Looping Statements (for, while, repeat, forever)
end lights always @(posedge clk) begin
default: begin endcasex // for loop
// Statements if no other cases match end for (i = 0; i < 4; i = i + 1) begin
end // Use 'casez' to handle high-impedance ('z') signals counter = counter + 1; // Increment counter in the for loop
endcase always @(*) begin end
casez Statement casez (signal_input) // while loop
Similar to case, but allows z or ? in values to act as wildcards. 2'bz?: traffic_light = 3'b000; // If the first bit is 'z' (high- i = 4;
casez (expression) impedance), turn off all lights while (i > 0) begin
4'b1???: begin 2'b00: traffic_light = 3'b100; // Green light counter = counter + 1; // Increment counter while i > 0
// Matches any value where MSB is 1 2'b01: traffic_light = 3'b010; // Yellow light i = i - 1;
end 2'b10: traffic_light = 3'b001; // Red light end
default: begin default: traffic_light = 3'b000; // Default case, turn off all // repeat loop
// Default case lights repeat (3) begin
end endcasez counter = counter + 1; // Increment counter 3 times
endcase end end
casex Statement endmodule // forever loop
Similar to casez, but treats both z and x as wildcards. forever begin
casex (expression) LOOPING STATEMENTS counter = counter + 1; // Continuously increment counter
4'b1x0z: begin for Loop with Condition #10; // Add a small delay to avoid infinite incrementing
// Matches patterns where x or z can be any value Used for repetitive execution based on a condition. without control
end for (initialization; condition; iteration) begin end
default: begin // Statements to execute in the loop end
// Default case End endmodule
end while Loop
endcase Executes statements as long as the condition is true BLOCKS IN VERILOG
module traffic_light_controller ( while (condition) begin Parallel Blocks (fork...join) allow simultaneous execution of
input wire [1:0] signal_input, // 2-bit input signal representing // Statements to execute different operations.
the state End Sequential Blocks (always @(posedge clk)) control operations
output reg [2:0] traffic_light // 3-bit output for the traffic light repeat Loop based on events like clock edges or resets.
status Executes a block of statements a fixed number of times. Named Blocks improve code readability and manageability by
); repeat (number) begin naming specific sections of code.
// Use 'case' to match exact signal values // Statements to execute Generate Blocks help in creating scalable and reusable code for
always @(*) begin end generating multiple instances of a component.
case (signal_input) forever Loop Initial Blocks are used to set up initial conditions for simulations.
2'b00: traffic_light = 3'b100; // Green light (0) Executes statements indefinitely. Usually combined with a parameters are an essential feature for creating configurable,
2'b01: traffic_light = 3'b010; // Yellow light (1) condition inside the loop to break it. reusable, and scalable designs
2'b10: traffic_light = 3'b001; // Red light (2) forever begin module #(parameter N = 4); // Parameter to control the size of
default: traffic_light = 3'b000; // Default: All off if invalid // Statements to execute generated blocks
input end reg clk, reset;
endcase reg [7:0] data_in;
end reg [7:0] data_out;
// Use 'casex' to handle unknown or invalid states represented reg [3:0] counter;
by 'x' wire [7:0] sum, product;
 TASKS AND FUNCTIONS module ;
// Initial block for initialization Functions in Verilog // Declare variables
initial begin They are perfect for combinatorial logic like arithmetic integer fd; // File descriptor for file operations
clk = 0; // Initialize clock to 0 operations, bitwise operations, and comparisons. reg [3:0] a, b; // Test signals
reset = 1; // Set reset signal to active module; reg done; // Task completion flag
data_in = 8'b00000001; // Set initial data input function int add(input int a, input int b); // Function to compare two numbers
counter = 4'b0000; // Initialize counter to 0 add = a + b; // Return the sum of a and b function compare(input int x, y);
#5 reset = 0; // Deactivate reset after 5 time units endfunction if (x > y) $display("x (%0d) is greater than y (%0d)", x, y);
end initial begin else if (x < y) $display("x (%0d) is less than y (%0d)", x, y);
// Clock generation (flip-flop simulation) int result; else $display("x (%0d) is equal to y (%0d)", x, y);
always #5 clk = ~clk; // Toggle clock every 5 time units result = add(10, 20); // Call the function return x + y; // Return sum
// Sequential block (Triggered by clock) $display("The sum is: %d", result); endfunction
always @(posedge clk or posedge reset) begin end // Task to perform operations and write to file
if (reset) begin endmodule task do_operations(input int x, y, output done_flag);
counter <= 4'b0000; Tasks in Verilog integer result;
data_out <= 8'b00000000; More suitable for actions that involve time delays, event control, result = compare(x, y); // Call the function
end else begin or multiple outputs. Tasks can model behavior like waiting for a $fdisplay(fd, "Comparison result: x = %0d, y = %0d, sum = %0d",
counter <= counter + 1; signal or triggering events, making them ideal for clocked or x, y, result);
data_out <= data_in + counter; // Simple operation based on sequential logic. #10; // Delay of 10 time units
counter module task; done_flag = 1; // Mark task as done
end task compare(input int a, input int b, output bit done); endtask
end if(a > b) // Initial block for simulation
// Parallel block $display("a is greater than b"); initial begin
fork else if(a < b) // Open a file for writing
// Perform sum calculation $display("a is less than b"); fd = $fopen("simulation_output.txt", "w");
sum = data_in + counter; else if (fd) $display("File opened successfully!");
// Perform product calculation $display("a is equal to b"); else $display("File open failed!");
product = data_in * counter; done = 1; // Set done flag when comparison is done // Set initial values
join endtask a = 4'd9;
// Named block for counting initial begin b = 4'd6;
count_block: begin bit done; // Display simulation start
if (counter == 4'b1111) compare(10, 10, done); // Call the task $display("Simulation starts at time %0t", $time);
$display("Counter reached maximum value: %d", counter); $display("Comparison done: %b", done); // Monitor signal changes
end compare(15, 20, done); // Call the task again $monitor("At time %0t: a = %0d, b = %0d", $time, a, b);
// Generate block (Creates multiple instances of adder based on $display("Comparison done: %b", done); // Perform task
parameter N) end do_operations(a, b, done);
generate endmodule if (done) $display("Operation completed at time %0t", $time);
genvar i; SYSTEM TASKS IN VERILOG // Generate random number
for (i = 0; i < N; i = i + 1) begin : adder_block System tasks in Verilog are pre-defined tasks that provide $display("Random number: %0d", $random);
assign sum = sum + i; // Sum up values from 0 to N-1 essential functionality for simulation, debugging, monitoring // Display mathematical utility
end $display("Ceiling of log2(16): %0d", $clog2(16));
endgenerate $display Prints messages with a newline at the end. // Simulation timing info
// Display the outputs $monitor Monitors changes to signals and prints them. $timeformat(-9, 2, " ns", 10); // Set time format to nanoseconds
initial begin $stop Pauses simulation (useful for debugging). $display("Current simulation time: %t", $time);
#10; $finish Ends the simulation. // End simulation
$display("Data Out: %b", data_out); $fopen Opens a file and returns its descriptor. $fclose(fd); // Close file
$display("Sum: %b", sum); $fclose Closes an open file. $finish; // Terminate simulation
$display("Product: %b", product); $fwrite Writes data to a file end
end $readmemb Reads binary data from a file into a memory array. endmodule
endmodule $random Generates a random number.
$time Returns the current simulation time in simulation
units.