Advanced Power MOSFET SFW/I9Z14

FEATURES
BVDSS = -60 V
n Avalanche Rugged Technology
n Rugged Gate Oxide Technology
RDS(on) = 0.5 Ω
n Lower Input Capacitance ID = -6.7 A
n Improved Gate Charge
n Extended Safe Operating Area
o D2-PAK I2-PAK
n 175 C Operating Temperature
n Lower Leakage Current : 10 µA (Max.) @ VDS = -60V 2

n Low RDS(ON) : 0.362 Ω (Typ.) 1

1
2
3 3

1. Gate 2. Drain 3. Source

Absolute Maximum Ratings
Symbol Characteristic Value Units
VDSS Drain-to-Source Voltage -60 V
o
Continuous Drain Current (TC=25 C) -6.7
ID o A
Continuous Drain Current (TC=100 C) -4.7
IDM Drain Current-Pulsed O1 -27 A
VGS Gate-to-Source Voltage O2 ±30 V
EAS Single Pulsed Avalanche Energy 115 mJ
IAR Avalanche Current O1 -6.7 A
EAR Repetitive Avalanche Energy O1 3.8 mJ
dv/dt Peak Diode Recovery dv/dt O3 -5.5 V/ns
o
Total Power Dissipation (TA=25 C) * 3.8 W
o
PD Total Power Dissipation (TC=25 C) 38 W
o
Linear Derating Factor 0.25 W/ C
Operating Junction and
TJ , TSTG - 55 to +175
Storage Temperature Range o
C
Maximum Lead Temp. for Soldering
TL 300
Purposes, 1/8” from case for 5-seconds

Thermal Resistance
Symbol Characteristic Typ. Max. Units
RθJC Junction-to-Case -- 3.95
o
RθJA Junction-to-Ambient * -- 40 C/W
RθJA Junction-to-Ambient -- 62.5
* When mounted on the minimum pad size recommended (PCB Mount).

Rev. C
 P-CHANNEL
SFW/I9Z14 POWER MOSFET

Electrical Characteristics (TC=25oC unless otherwise specified)

Symbol Characteristic Min. Typ. Max. Units Test Condition
BVDSS Drain-Source Breakdown Voltage -60 -- -- V VGS=0V,ID=-250µA
∆BV/∆TJ Breakdown Voltage Temp. Coeff. -- -0.05 --
o
V/ C ID=-250µA See Fig 7
VGS(th) Gate Threshold Voltage -2.0 -- -4.0 V VDS=-5V,ID=-250µA
Gate-Source Leakage , Forward -- -- -100 VGS=-20V
IGSS nA
Gate-Source Leakage , Reverse -- -- 100 VGS=20V
-- -- -10 VDS=-60V
IDSS Drain-to-Source Leakage Current µA VDS=-48V,TC=150 C
o
-- -- -100
Static Drain-Source
RDS(on) -- -- 0.5 Ω VGS=-10V,ID=-3.4A O
4
On-State Resistance
gfs Forward Transconductance -- 2.4 -- S VDS=-30V,ID=-3.4A O
4

Ciss Input Capacitance -- 270 350

VGS=0V,VDS=-25V,f =1MHz
Coss Output Capacitance -- 90 135 pF
See Fig 5
Crss Reverse Transfer Capacitance -- 25 35
td(on) Turn-On Delay Time -- 10 30
VDD=-30V,ID=-6.7A,
tr Rise Time -- 19 50
ns RG=24 Ω
td(off) Turn-Off Delay Time -- 21 50
See Fig 13 O
4O5
tf Fall Time -- 16 40
Qg Total Gate Charge -- 9 11 VDS=-48V,VGS=-10V,
Qgs Gate-Source Charge -- 1.8 -- nC ID=-6.7A
Qgd Gate-Drain(“Miller”) Charge -- 4.2 -- See Fig 6 & Fig 12 O
4O5

Source-Drain Diode Ratings and Characteristics

Symbol Characteristic Min. Typ. Max. Units Test Condition
IS Continuous Source Current -- -- -6.7 Integral reverse pn-diode
A
ISM Pulsed-Source Current O
1 -- -- -27 in the MOSFET
o
VSD Diode Forward Voltage O4 -- -- -3.8 V TJ=25 C,IS=-6.7A,VGS=0V
o
trr Reverse Recovery Time -- 75 -- ns TJ=25 C,IF=-6.7A
Qrr Reverse Recovery Charge -- 0.17 -- µC diF/dt=100A/µs O
4

Notes ;
O1 Repetitive Rating : Pulse Width Limited by Maximum Junction o
Temperature
O2 L=3.0mH, I AS=-6.7A, V DD=-25V, RG =27Ω *, Starting T J =25 C
O3 ISD <_ -6.7A, di/dt <_ 200A/µs, VDD<_ BVDSS , Starting TJ =25oC
O4 Pulse Test : Pulse Width = 250µs, Duty Cycle< _ 2%
O5 Essentially Independent of Operating Temperature
 P-CHANNEL
POWER MOSFET SFW/I9Z14
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
VGS
Top : - 15 V
1 - 10 V
10 - 8.0 V 101
-ID , Drain Current [A]

- 7.0 V

-ID , Drain Current [A]

- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V

175 oC
100 100
@ Notes :
25 oC 1. VGS = 0 V
@ Notes : 2. VDS = -30 V
1. 250 µs Pulse Test 3. 250 µs Pulse Test
- 55 oC
2. TC = 25 oC
10-1 -1 10-1
10 100 101 2 4 6 8 10
-VDS , Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V]

Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage
1.2
-IDR , Reverse Drain Current [A]

101
Drain-Source On-Resistance

0.9
RDS(on) , [ Ω ]

VGS = -10 V

0.6
100
175 oC
0.3 @ Notes :
1. VGS = 0 V
25 oC 2. 250 µs Pulse Test
VGS = -20 V @ Note : TJ = 25 oC
0.0 10-1
0 5 10 15 20 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
-ID , Drain Current [A] -VSD , Source-Drain Voltage [V]

Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage
500
Ciss= Cgs+ Cgd ( Cds= shorted )
Coss= Cds+ Cgd VDS = -12 V
Crss= Cgd 10
400 VDS = -30 V
-VGS , Gate-Source Voltage [V]

C iss VDS = -48 V

Capacitance [pF]

C oss
300

@ Notes : 5
200 1. VGS = 0 V
2. f = 1 MHz
C rss
100
@ Notes : ID =-6.7 A

00 0
10 101 0 2 4 6 8 10
-VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC]
 P-CHANNEL
SFW/I9Z14 POWER MOSFET

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

1.2 2.5
Drain-Source Breakdown Voltage

Drain-Source On-Resistance
2.0
-BVDSS , (Normalized)

RDS(on) , (Normalized)
1.1

1.5

1.0

1.0

0.9 @ Notes : @ Notes :

1. VGS = 0 V 0.5 1. VGS = -10 V
2. ID = -250 µA 2. ID = -3.4 A

0.8 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 200 -75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Junction Temperature [ C] o
TJ , Junction Temperature [oC]

Fig 9. Max. Safe Operating Area Fig 10. Max. Drain Current vs. Case Temperature
8
-ID , Drain Current [A]

102 Operation in This Area

is Limited by R DS(on)
-ID , Drain Current [A]

6
0.1 ms
101 1 ms
10 ms 4
DC
@ Notes :
100 1. TC = 25 oC
2. TJ = 175 oC 2
3. Single Pulse

10-1 0 0
10 101 102 25 50 75 100 125 150 175
-VDS , Drain-Source Voltage [V] Tc , Case Temperature [oC]

Fig 11. Thermal Response

Thermal Response

D=0.5

100 @ Notes :
0.2 1. Zθ J C (t)=3.95 o C/W Max.
2. Duty Factor, D=t1 /t2
0.1
3. TJ M -TC =PD M *Zθ J C (t)
0.05 P.DM
Z (t) ,

0.02
t1.
10- 1 0.01
t2.
θ JC

single pulse

10- 5 10- 4 10- 3 10- 2 10- 1 100 101

t 1 , Square Wave Pulse Duration [sec]
 P-CHANNEL
POWER MOSFET SFW/I9Z14
Fig 12. Gate Charge Test Circuit & Waveform

“ Current Regulator ”
VGS
Same Type
50KΩ as DUT Qg
12V 200nF
300nF -10V

VDS
VGS Qgs Qgd

DUT
-3mA
R1 R2

Current Sampling (IG) Current Sampling (ID)

Charge
Resistor Resistor

Fig 13. Resistive Switching Test Circuit & Waveforms

RL
t on t off
Vout tf
td(on) tr td(off)
Vin VDD
( 0.5 rated VDS ) Vin
10%
RG
DUT

-10V
90%
Vout

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

1 BVDSS
LL EAS = ---- LL IAS2 --------------------
VDS 2 BVDSS -- VDD
Vary tp to obtain ID tp Time
required peak ID
VDD VDS (t)
RG C VDD ID (t)
DUT
-10V IAS
tp BVDSS
 P-CHANNEL
SFW/I9Z14 POWER MOSFET

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

VDS
DUT
--

IS
L

Driver
VGS
Compliment of DUT
RG
(N-Channel) VDD

VGS • dv/dt controlled by “RG”

• IS controlled by Duty Factor “D”

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

Body Diode Reverse Current

IRM
IS
( DUT )
di/dt

IFM , Body Diode Forward Current

Vf
VDS
( DUT )
Body Diode VDD
Forward Voltage Drop

Body Diode Recovery dv/dt

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PRODUCT STATUS DEFINITIONS

Definition of Terms

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Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

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any time without notice in order to improve design.

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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I1