2024년 2학기

M. Morris Mano
Computer System Architecture

Chapter 11: Input-Output Organization

박 찬식
http://gnc.chungbuk.ac.kr
chansp@chungbuk.ac.kr
교육관 325호, T. 3259

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목차
■ Peripheral Devices
■ Input-Output Interface
■ Asynchronous Data Transfer
■ Modes of Transfer
■ Priority Interrupt
■ DMA(Direct Memory Access)
■ IOP(Input-Output Processor)
■ Serial Communication

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Peripheral Devices
■ I/O provides an efficient mode of communication
between central system and the outside environment
■ Peripherals are I/O devices attached to the computer
▣ Monitor and Keyboard
▣ Printer
▣ Magnetic Tapes
▣ HDD, FDD, CD, ….

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Input-Output Interface
■ Interface unit interfaces between the processor bus
and peripheral devices
▣ Conversion of Signals
▪ electronic device Vs. Electromechanical device
▣ Synchronization mechanism
▪ Fast Memory Vs. Slow device
▣ Change word format
▪ Different word format
▣ Operating mode of peripherals are different
▪ must be controlled so as not to disturb the operation of other peripherals

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I/O Bus and Interface Modules

I/O Bus
Data
Processor Address
Control

Interface Interface Interface

Keyboard
and Display Printer HDD
Terminal

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I/O Vs. Memory Bus
■ Two Separate Buses
▣ IOP(I/O Processor) communicates with CPU through memory
bus
▪ IOP is master of IO Bus

■ One common bus but have separate control lines

▣ Isolated I/O (I/O mapped I/O)
▪ Different instruction for memory (LD/ST) and I/O (IN/OUT)
▪ CPU is master of IO Bus
▪ Zilog, Intel, ….

■ One common bus with common control lines

▣ Memory mapped I/O
▪ Same instruction for memory and I/O(MOV)
▪ CPU is master of IO bus
▪ Motorola, ….

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Example of I/O interface
CPU I/O Interface I/O Device

Data Port A
Bus Bus buffer
Register
Port B
Chip Select CS

Internal Bus
Register
Register RS1 Timing
Select Control
RS0 and Register
I/O Read RD Control
I/O Write WR Status
Register

Example:CS = A7&A6&…&A2, RS1 = A1, RS0 = A0

FC Port A Register
FD Port B Register
FE Control Register
FF Status
7
Register
Asynchronous Data Transfer
■ Synchronous Vs. Asynchronous
▣ Synchronous Data Transfer
▪ Common bus operations of Basic Computer
▪ Synchronized with clock pulses
▣ Asynchronous Data Transfer
▪ Two computers connected by serial cable
▪ No Common clock pulses
- Strobe or Handshaking methods are used

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Strobe Control
Source Initiate Strobe Vs. Destination Initiate Strobe
Data Data
Source Destination Source Destination
Unit Strobe Unit Unit Strobe Unit

Data Data

Strobe Strobe

Hey, Get the Data Hey, Give me Data

while Strobe is High while Strobe is High
(제대로 받았나?) (Data를 제대로 보냈나?)
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Handshaking
■ Source Initiated Transfer

Data
Source DStrobe Destination
Unit DAck Unit

Data
1. Hey, Get Data 3. OK, Let’s Finish
DStrobe See you

2. OK, I got Data

4. OK, See You
DAck
*. Good position to read data
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Handshaking
■ Destination Initiated Transfer

Data
Source DStrobe Destination
Unit Ready Unit

Ready
3. I got Data
1. Hey, Give me Data See you
DStrobe

2. OK, Here’s Data 4. OK, See You

Data
*. Good position to read data
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Handshaking
■ Timeout Mechanism
▣ What can CPU do if There is no DAck
▪ Have to wait forever ? No !
▪ Use Timer(or Counter) to measure time
- Timer start at rising of DStrobe
- DAck reset Timer
- If No DAck, Then timeout occurs
- Special Interrupt (Trap) to CPU

▣ Note that Instruction is not finished, thus usual interrupt

mechanism can not recover this situation
▣ Same mechanism can be applied to memory to implement
Virtual Memory

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Asynchronous Serial Transfer
■ Parallel Vs. Serial Data Transfer
▣Parallel D0
Source Destination

….
D7

▪ Faster but requires many lines

▪ Short distance: Printer, Common bus, …
▣Serial
Source D0,D1,…,D7 Destination

▪ Slower but requires only one pair of conductors

▪ Long distance: Mouse, Modem, …

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Synchronous Serial Transfer
■ Synchronizing using
▣ Common Clock Frequency
D0,D1,…,D7
Source Clock Destination

▣ Clock Information hidden in Data using Coding

Source D0,D1,…,D7 Destination

Clock Info.

■ Up to MHz (Mbps)

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Asynchronous Serial Transfer
■ No Clock Information
▣ Predefined Speed
▪ 9600bps, 5.6Kbps, …

■ To Indicate Data part

▣ Start and Stop bit are added
■ Number of bits in Data part
▣ Predefined
▪ 8 bits/Character, 7 bits/Character, …

■ To detect error
▣ Parity bit is included
▪ Even, Odd, None, (Mark), (Space)

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Asynchronous Serial Transfer
■ Transmitting Data 10100011B
If there is no Data
Get the Data
Signal is High(Mark)
B0,B1,…,B7 Order
How do you know
No Parity
High or No data?

1 1 0 0 0 1 0 1

Start Bit say that Stop Bit say that

“ This is start of “ This is End of
transmission, transmission,
Get the Data bit Reset your circuit
after Start bit” to receive next character”

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Asynchronous Serial Transfer
■ Receiving Data

Reset Counter
with Start Bit

0 1 2 3 4 5 6 7 0 1 2 34 5 6 7 0

Receiver has Counter

Ex: For 9600bps Get Data in the Middle of Counter
8 Values/Bit This is best way to remove noise

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Asynchronous Serial Transfer
■ Easy to Implement
▣ 1 Tx Line, 1 Rx Line, 1 GND line
▣ UART(Universal Asynchronous Receiver Transmitter)
■ Overheads
▣ 1 Start bit, 1~2 Stop bits, 1 Parity bit
▪ Ex: 9600 bps
- 8 bit Data + 1 Start + 1 Stop + 1 Parity
- 11/9600 = 1.146 msec/Character
▣ Hard to Speed up
▪ Internal Counter Speed

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 Asynchronous Communication Interface
UART
Tx
Data Transmitter Shift Data
Bus Bus buffer
Register Register
Tx
Control Tx Control Clock
Chip Select
CS

Internal Bus
Register and Clock
Register Select RS Timing
Status Rx Control
and Rx
I/O Read Register and Clock
RD Control Clock
I/O Write
WR Receiver Shift
Register Register Rx
Data

Example:CS = A7&A6&…&A2&A1, RS = A0
FE + WR Transmitter Register
FE + RD Receiver Register
FF + WR Control Register
FF + RD Status Register
FIFO(First-In, First-Out) Buffer
■ What happens if
▣ 10 Byte/Sec Data comes from Rx line
▣ 7 Byte/Sec Data goes to CPU
▪ CPU is Busy or Slow

■ 3 Byte/Sec Data will be Lost (Overrun) !

▣ Flow Control Using XON/XOFF
▪ Send XOFF(^S) if Receiver Register is full
▪ Send XON(^Q) if Receiver Register has room
▣ FIFO

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FIFO(First-In, First-Out) Buffer

Rx Data
Shift Register
Rx Data
Shift Register Buffer

FIFO FIFO
Receiver Register
Depth=1 Depth=3 Buffer

To CPU
Receiver Register

To CPU

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Summary &
■ 주변장치
■ Interface
■ Serial vs Parallel
■ Synchronous vs Asynchronous
■ Port, PIO, 8255 (Parallel)
■ UART, 8251 (Serial)

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