Chapter Two
Hardware Issue
8051 Microcontroller
1
Microcontroller(MCU)
A microcontroller is an integrated circuit (IC) or
system on chip which is small, low cost and self
contained computer
designed to handle a specific task in embedded
systems like receiving remote signals etc.
MCU can be programmed to do a specific task
based on it’s instruction set and capabilities.
The general microcontroller consists of the
processor, the memory (RAM, ROM, EPROM), Serial
ports, peripherals (timers, counters), etc.
A microcontroller processes data given to it’s input
pins using it’s CPU and gives output via output pins.
2
C P U families used in microcontrollers
Microcontroller family defines the controllers
architecture.
All microcontrollers of a family
they may differ in the additional components like the
number of timers or the amount of memory.
There are numerous microcontrollers on the market:
Intel 8051, Motorola MC68HC11, PIC,ARM ,AT89C51 and
others.
3
C P U families used in microcontrollers
In 1981,Intel Corporation introduced an 8-bit
microcontroller called the 8051(Intel refers to it as MCS-
51)
The Intel 8051 microcontroller is one of the most popular
general purpose microcontrollers in use today.
The 8051 microcontroller family became widely popular.
The Intel 8051 is an 8-bit microcontroller which means that most
available operations are limited to 8 bits
The 8051 family has the largest number of diversified
suppliers:Intel,Atmel,Philips,AMD, Infineon and others.
4
Overview of 8051 family
The 8051 is an 8-bit processor and it has
128 bytes of RAM
4K bytes of on-chip ROM
Two 16-bit timers
One serial port
Four I/O ports, each 8 bits wide
8-bit Data bus
16-bit Address bus
Four 8-bit ports
3 internal and 2 external interrupts
5
8051 Microcontroller
External Interrupts
Interrupt 4k 128 bytes Timer 0
Control ROM RAM Timer 1
CPU
OSC Bus
4 I/O Ports Serial
Control
P0 P2 P1 P3 TXD RXD
Addr/Data
6
8051 Family
7
8051
pin diagram P1.0
P1.1
1
2
40
39
Vcc
P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 P0.6(AD6)
RST
8
9
8051 33
32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
8
I/O Ports of 8051 MCU
There are 4 8-bit ports: P0, P1, P2 and P3.
In order to make the microcontroller useful, it is necessary to connect it to
peripheral devices.
The Peripherals of an embedded processor can either be on the same chip as
the processor or can be connected externally through the I/O pins.(network,
display port..)
Each microcontroller has one or more registers connected to the
microcontroller pins.
Pins can either be input only, output only, or most commonly— bidirectional,
that is, capable of both input and output.
The application programmer can select which function should be used for the
pin by enabling the functionality within the appropriate module.
9
8051 I/O ports
8051 MCU has four ports P0, P1, P2, and P3 and each use 8
pins
10
8051 MCU I/O ports
Port 0 （pins 32-39）：P0（P0.0-P0.7）
In addition to serving as I/O port, lower order address and data are
multiplexed with this port.
PORT 0. P0 is configured as address output (A0-A7) when the ALE pin
is driven high (1) or as data output (Data Bus) when the ALE pin is
driven low (0).
Address Bus: 8051 microcontrollers is consisting of 16 bit address bus. It is generally be
used for transferring the data from Central Processing Unit to Memory.
Data bus: 8051 microcontroller is consisting of 8 bits data bus.
11
8051 MCU I/O ports
Port 1 （pins 1-8） ：P1（P1.0-P1.7）
Only 8- P1 is a true I/O port as it doesn’t have any alternative functions
as in P0.
if logic zero (0) is applied to the I/O port it will act as an output pin and
if logic one (1) is applied the pin will act as an input pin
Port 2 （pins 21-28）：P2（P2.0-P2.7）
PORT P2 can also be used as a general purpose 8 bit port
when no external memory is present, but if external
memory access is required then PORT P2 will act as an
address bus in conjunction with PORT P0 to access
external memory. PORT P2 acts as A8-A15
12
8051 I/O ports
Port 3 （pins 10-17）：P3（P3.0～P3.7）
PORT P3 acts as a normal IO port, but Port P3 has additional
functions such as, serial transmit and receive pins, 2 external
interrupt pins, 2 external counter inputs, read and write pins for
memory access.
Receive data
13
Other pins in MCU 8051
EA（pin 31）：external access
If we have to use multiple memories then the application of logic 1 to this pin
instructs the Microcontroller to read data from both memories: first internal
and then external.
PSEN（pin 29）：program store enable
This is an output pin and Systems to allow storage of program code in
external ROM..
ALE（pin 30）：address latch enable
When ALE=0, P0 provides data D0-D7.
When ALE=1, P0 provides address A0-A7.
This pin is used to distinguish between memory chips when
multiple memory chips are used.
14
Cont…
Vcc − Pin 40 provides supply to the Chip and it is +5 V.
Gnd − Pin 20 provides ground for the Reference.
XTAL1, XTAL2 (Pin no 18 & Pin no 19) − CPU executing an
instruction takes a certain number of clock cycles
These are referred as to as machine cycles
In original 8051, one machine cycle lasts 12 oscillator
periods
Oscillators are responsible for supplying the clock signals
in microcontrollers.
T0 and T1(timers):
A timer 16-bit register uses the frequency of the internal clock
signal, and generates delay.
to measure time and count external events.
15
Cont..
(RXD) :10th pin is RXD (serial data receive pin) which is for serial input.
Through this input signal microcontroller receives data for serial
communication.
(TXD) :11th pin is TXD (serial data transmit pin) which is serial output
pin
(WR’) :16th pin is for external memory write i.e. writing data to the
external memory.
(RD’) :17th pin is for external memory read i.e. reading data from
external memory.
16
R O M a n d R A M in 8051 MCU
The original 8051 microcontroller has 4K bytes on-chip ROM.
No member of 8051 family can have more than 64K bytes ROM:
There are 128 bytes of RAM in the 8051(Assigned addresses 00 to 7FH)
The 128 bytes are divided into three different groups as follows:
1. A total of 32 bytes from locations 00H to 1FH(0-31) are set aside for
register banks and the stack
2. A total of 16 bytes from locations 20H to 2FH (32-47) are set aside for
bit-addressable read/write memory
3. A total of 80 bytes from locations 30H to 7FH are used for read
and write storage, called scratch pad.
17
R A M of8051
18
Register Banks
19
Register Banks
The 32 bytes from address 00 to 1F hex are divided into 4
banks of registers in which each bank has 8 registers, R0-
R7.
Register bank 0 is the default when 8051 is powered up.
That is by default RAM locations 0, 1,2,3,4,5,6 and 7 are accessed
with names R0, R1, R2, R3, R4, R5, R6 and R7 when programing
the 8051.
We can switch to other banks by use of the PSW(program
status word) register.
Bits D4 and D3 of the PSW are used to select the desired
register bank.
20
Program Status Word (PSW)
Upon RESET, bank 0 is selected cause it is default
We can select any other banks using the bit-
addressability of the PSW.
21
Program Status Word (PSW)
The program status word (PSW) register, also referred to
as the flag register, is an 8 bit register.
Only 4 bits are used
CY (carry),AC (auxiliary carry), P (parity), and OV (overflow).
The PSW3 and PSW4 are designed as RS0 and RS1, and are used
to change the register banks.
MSB LSB
CY AC -- RS1 RS0 OV -- P
D7 D6 D5 D4 D3 D2 D1 D0
Program Status Word (PSW) Register
22
Program Status Word (PSW)
The carry flag (CY): there is a carry out of MSB or not.
Set whenever there is a carry out from the D7 bit
It is affected after an 8-bit addition or subtraction.
Auxiliary carry (AC)
indicates a carry from D3 to D4 during addition and subtraction
operations.
The overflow flag (OV)
set whenever the result of a signed number operation is too large,
causing the high-order bit to overflow into the sign bit.
23
Program Status Word (PSW)
The parity flag (P)
The parity flag reflects the number of 1s in the A (accumulator)
register only.
If the register A contains an odd number of 1s, then P = 1.
And P = 0 if A has an even number of 1s.
Exercise:
Show the status of CY ,AC and P flags after the addition of 9CH
and 64H in the following instruction. After Addition A=00H, C=1
MOV A, #9CH
ADD A, # 64H
24
Stack in 8051
The stack is a section of RAM used by the CPU to store
information temporarily.
The register used to access the stack is called the stack
pointer (SP) register.
The storing of a CPU register in the stack is called a PUSH
SP is pointing to the last used location of the stack
As we push data onto the stack, the SP is incremented by one
Loading the contents of the stack back into a CPU register is
called a POP
With every pop, the top byte of the stack is copied to the
register specified by the instruction and the stack pointer is
decremented one.
25
Stack in 8051
26
Stack in 8051
27
bit-addressable R A M
Of the 128-byte internal RAM of the 8051, only 16 bytes
from 20H to 2FH are bit-addressable.
The 8051 supports a special feature which allows access
to bit variables.
Being bit variables any one variable can have a value 0
or 1
This is where individual memory bits in Internal RAM
can be set or cleared.
A bit variable can be set with a command such as SETB
and cleared with a command such as CLR
28
bit-addressable R A M
Find out to which byte each of the following
bits belongs. Give the address of the RAM
a) SETB 42H
b) CLR 67H
c) CLR 0F
d) SETB 28B
e) CLR 12
f) CLR 05H
29
Cont….
30
Timers and Counters
Timers and counters are distinguished from one another
largely by their use, not by their logic.
Both are built from adder logic with registers to hold the
current value, with an increment input that adds one to the
current register value.
A timer has its count connected to a periodic clock signal to
measure time intervals.
A counter has its count input connected to an aperiodic signal in
order to count the number of occurrences of some external
event.
31
Timers in 8051
Original 8051 has 2 timers.
Timers increment on each system clock.
Timer registers (TH0,TL0,TH1,TL1) can be read or
written to.
Timer overflow can cause “interrupts” or set SFR bits
high.
16 bits 16 bits
TH0 : TL0 TH1 : TL1
Timer 0 Timer 1
32
Interrupts Handling
An interrupt is a signal to the processor emitted by
hardware or software indicating an event that needs
immediate attention
Whenever an interrupt occurs, the controller completes
the execution of the current instruction and starts the
execution of an Interrupt Service Routine (ISR) or
Interrupt Handler.
ISR tells the processor or controller what to do when the
interrupt occurs.
33
Interrupt Service Routine
For every interrupt, there must be an Interrupt service routine (ISR),
Interrupt handler.
For every interrupt, there is a fixed location in memory that
holds the address of its ISR.
The group of memory locations set aside to hold the addresses of
ISRs is called the interrupt vector table.
In polling method the microcontroller continuously monitor the
status of a given device, when the condition is met it performs the
service.
This polling method is not efficient because it has to monitor all
times.
34
Steps in executing an Interrupt
Once an interrupt is activated, microcontroller performs the following
steps.
1. It finishes the instruction it is executing and save the address of the
next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally.
3. It jumps to a fixed location in memory called the interrupt vector
table that holds the address of ISR.
4. The microcontroller gets the address of the ISR from the interrupt
vector table and jumps to it. It starts to execute the ISR until it
reaches last instruction of subroutine RETI (return from the
interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to
the place where it was interrupted. First it gets PC address from the
stack by popping the top two bytes of the stack into the PC
35
Interrupt Sources
Interrupts could be from hardware, software or other
sources.
Hardware interrupts are the most discussed types
originating from on-chip/on-board peripherals.
Apart of them, most architectures provides instructions
that can be used to generate an interrupt – typically to
enter kernel mode.
Also exceptions like page fault, instruction fetch errors
etc are handled as interrupts.
36
Hardware Interrupts
Hardware Interrupts: A hardware interrupt is anelectronic
alerting signal sent to the processor from an external
device, like a disk controller or an external peripheral.
For example, when we press a key on the keyboard, it triggers
hardware interrupt which causes the processor to read the
keystroke.
37
Software Interrupts
Software Interrupts: A software interrupt is causedeither
by an exceptional condition or a special instruction in the
instruction set which causes an interrupt when it is
executed by the processor.
For example, if the processor's arithmetic logic unit runs a
command to divide a number by zero, to cause a divide-by-zero
exception, thus causing the computer to abandon the calculation
or display an error message.
Software interrupt instructions work similar to subroutine calls.
38
Enabling and Disabling anInterrupt
Upon Reset, all the interrupts are disabled even if they are
activated.
The interrupts must be enabled using software in order for
the microcontroller to respond to those interrupts.
A special function register called IE (interrupt enable)
register is responsible for enabling and disabling the
interrupt.
IE is a bit-addressable register.
39
IE (Interrupt Enable) Register of8051
MSB LSB
40
Interrupt Priorities
What if two interrupt sources interrupt at the same
time?
Each interrupt source can also be individually
programmed to one of the two priority levels by setting
or clearing a bit in the SFR named IP (Interrupt Priority).
A low-priority interrupt can be interrupted by a high-
priority interrupt.
If two interrupt requests of different priority levels are
received simultaneously, the request of higher priority is
serviced.
41
Interrupt Priority in8051
If interrupt requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced.
When the 8051 is powered up, the priorities are assigned
according to the following.
42
Further Reading ….
Hardware Issues/Challenges
Micro Controllers families
How to use Assembly Language for
microcontroller simulation
Register Banks(stack in RAM)
Interrupt priorities
Block Diagram of MCU
Mobile Programming with Proteus 8
Professional
