Module-1

Moore’s Law:
 The invention of the transistor by William B. Shockley, Walter H. Brattain
and John Bardeen of Bell Telephone Laboratories was followed by the
development of the Integrated Circuit (IC).
 The very first IC emerged at the beginning of 1960 and since that time there
have already been four generations of ICs:
1) SSI (small scale integration)
2) MSI (medium scale integration)
3) LSI (large scale integration)
4) VLSI (very large scale integration).
5) ULSI (ultra large scale integration) which is characterized by complexities
in excess of 3 million devices on a single IC chip.
 Over the past several years, Silicon CMOS technology has become the
dominant fabrication process for relatively high performance and cost
effective VLSI circuits.
 The revolutionary nature of this development is indicated by the way in
which the number of transistors integrated in circuits on a single chip has
grown as indicated in Figure 1

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Speed Power Performance:
 In order to improve on throughput rate it will be necessary to improve the
technology, both in terms of scaling and processing, and through the
incorporation of other enhancements such as BiCMOS.
 The implications of this approach are that existing silicon technology could
effectively facilitate the tripling of rate.
 Beyond this, i.e., above 100 million instructions per second, one must look
to other technologies.
 In particular, the emerging Gallium Arsenide (GaAs) based technology will
be most significant in this area of ultra high speed logic/fast digital
processors.
 GaAs also has further potential as a result of its photo-electronic properties,
both as a receiver and as a transmitter of light.
 GaAs in combination with silicon will provide the designer with some very
exciting possibilities.

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nMOS fabrication:
STEP1:
 Processing is carried out on a thin wafer cut from a single crystal of silicon
of high purity into which the required p-impurities are introduced as the
crystal is grown.
 Such wafers are typically 75 to 150 mm in diameter and 0.4 mm thick and
are doped with, say, boron to impurity giving resistivity in the approximate
range 25 ohm cm to 2 ohm cm.

STEP2:
 A layer of silicon dioxide (Si02), typically 1µm thick, is grown all over the
surface of the wafer to protect the surface.

STEP3:
 The surface is now covered with a photoresist which is deposited onto the
wafer and spun to achieve an even distribution of the required thickness.

STEP4:
The photoresist layer is then exposed to ultraviolet light through a mask which
defines those regions into which diffusion is to take place together with transistor
channels. Assume, for example, that those areas exposed to ultraviolet radiation are
polymerized (hardened), but that the areas required for diffusion are shielded by
the mask and remain unaffected.

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STEP5:
These areas are subsequently readily etched away together with the underlying
silicon dioxide so that the wafer surface is exposed in the window defined by the
mask.

STEP6:
The remaining photoresist is removed and a thin layer of Si02 is grown over the
entire chip surface and then polysilicon is deposited on top of this to form the gate
structure.

STEP7:
Further photoresist coating and masking allows the polysilicon to be patterned and
then the thin oxide is removed to expose areas into which n-type impurities are to
be diffused to form the source and drain as shown.

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STEP8:
Thick oxide (Si02) is grown over all again and is then masked with photoresist and
etched to expose selected areas of the polysilicon gate and the drain and source
areas where connections (i.e. contact cuts) are to be made.

STEP9:
The whole chip then has metal (aluminum) deposited over its surface to a thickness
typically of 1 micro meter. This metal layer is then masked and etched to form the
required interconnection pattern.

CMOS FABRICATION
1. The p-well Process

The structure consists of an n-type substrate in which p-devices may be formed by

suitable masking and diffusion and, in order to accommodate n-type devices, a
deep p-well is diffused into the n-type substrate

 Mask 1 - defines the areas in which the deep p-well diffusions are to take
place.
 Mask 2 - defines the thinox regions, namely those areas where the thick
oxide is to be stripped and thin oxide grown to accommodate p- and n-
transistors and wires.

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  Mask 3 - used to pattern the polysilicon layer which is deposited after the
thin oxide.

 Mask 4 - A p-plus mask is now used to define all areas where p-diffusion is
to take place.

 Mask 5 - This is usually performed using the negative form of the p-plus
mask and defines those areas where n-type diffusion is to take place.

 Mask 6 - Contact cuts are now defined.

 Mask 7 - The metal layer pattern is defined by this mask.
 Mask 8 - An overall passivation (overglass) layer is now applied and Mask 8
is needed to define the openings for access to bonding pads.

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 2. The n-well Process

N-well CMOS circuits are also superior to p-well because of the lower substrate
bias effects on transistor threshold voltage and inherently lower parasitic
capacitances associated with source and drain regions.

Typical n-well fabrication steps are illustrated below:

An inverter circuit fabricated by the n-well process

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Comparison of bipolar and CMOS:
CMOS technology Bipolar technology
 Low static power dissipation  High power dissipation
 High input impedance  Low input impedance
 Scalable threshold voltage  Low voltage swing logic
 High noise margin  Low packing density
 High packing density  Low delay sensitivity to load
 High delay sensitivity to load  High output drive current
 Low output drive current  High gm
 Low gm  High ft, at low currents
 Bidirectional capability  Essentially unidirectional
 (drain_ and source are
interchangeable)
 A near ideal switching device

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DRAIN-TO-SOURCE CURRENT Ids versus VOLTAGE Vds
RELATIONSHIP:

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BASIC VLSI DESIGN
BASIC VLSI DESIGN
MOS TRANSISTOR TRANSCONDUCTANCE g m:

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BASIC VLSI DESIGN
 Module-2
Basic Electrical Properties of MOS and BiCMOS Circuits:
nMOS inverter:
 A basic requirement for producing a complete range of logic circuits is the
inverter. This is needed for restoring logic levels, for Nand and nor gates,
and for sequential and memory circuits of various forms.
 The basic inverter circuit requires a transistor with source connected to
ground and a load resistor of some sort connected from the drain to the
positive supply rail Vdd. The output is taken from the drain and the input
applied between gate and ground.

 For the depletion mode transistor, the gate is connected to the source so it is
always on.
 In this configuration the depletion mode device is called the pull-up (p.u.)
and the enhancement mode device the pull-down (p.d.) transistor.
 When Vin is logic 0, enhancement nmos is OFF. Hence current flows
through depletion nmos to the output voltage i.e.Vout=Vdd or Vout=logic 1.
 When Vin is logic 1, enhancement nmos is ON. Hence current flows from
Vdd to ground via enhancement and depletion nmos. Vout = 0 or logic 0.

Vin Vout
Logic 0 Logic 1

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  Derivation of nMOS Inverter transfer characteristic

 nMOS Inverter transfer characteristic

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PULL-UP TO PULL-DOWN RATIO FOR AN nMOS INVERTER
DRIVEN THROUGH ONE OR MORE PASS TRANSISTORS
 Now consider the arrangement of Figure below in which the input to inverter
2 comes from the output of inverter 1 but passes through one or more nMOS
transistors used as switches in series (called pass transistors).
 We are concerned that connection of pass transistors in series will degrade
the logic 1 level into inverter 2 so that the output will not be a proper logic 0
level.
 The critical condition is when point A is at 0 volts and B is thus at Vdd but
the voltage into inverter 2 at point C is now reduced from Vdd by the
threshold voltage of the series pass transistor.

 The input voltage to inverter 2 is

 We must now ensure that for this input voltage we get out the same voltage
as would be the case for inverter 1 driven with input = Vdd·
i.e. Vout1=Vout2

Similarly,

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ALTERMTIVE FORMS OF PULL UP:
1. Load resistance RL:
 This arrangement is not often used because of the large space requirements
of resistors produced in a silicon substrate.

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 2. nMOS depletion mode transistor pull-up:
 Switching of output from 1 to 0 begins when Vin exceeds Vt, of p.d. device.

3. nMOS enhancement mode pull-up:

 Vout can never reach VDD (logical 1) if VGG = VDD as is normally the case.

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 4. Complementary transistor pull-up (CMOS):
 No current flow either for logical 0 or for logical 1 input.
 Full logical 1 and 0 levels are presented at the output.

THE CMOS INVERTER

 We have seen that the current/voltage relationships for the MOS transistor
may be written as in the resistive region

 In saturation region

------- (1)
 In both cases the factor K is a technology-dependent parameter such that

 The factor W/L is, of course, contributed by the geometry and it is common
practice to write

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 -----------(2)
Substituting equation (2) in (1):

 where β may be applied to both nMOS and pMOS transistors as follows:

1. Region 1:
 Vin =logic 0, we have the p-transistor fully turned on while the n-transistor is
fully turned off.

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  Thus no current flows through the inverter and the output is directly
connected to VDD through the p-transistor.
 A good logic 1 output voltage is thus present at the output.
2. Region 2:
 The input voltage has increased to a level which just exceeds the threshold
voltage of the n-transistor.
 The n-transistor conducts and has a large voltage between source and drain;
so it is in saturation.
 The p-transistor is also conducting but with only a small voltage across it, it
operates in the unsaturated resistive region.
 A small current now flows through the inverter from VDD to Vss.
3. Region 3:
 Inverter exhibits gain and in which both transistors are in saturation.
 The current in each device must be the same since the transistors are in
series, so we may write
Idsp=-Idsn
Where

 To make this equal Vin=0.5VDD and = 2.5

4. Region 4:
 Region 4 is similar to region 2 but with the roles of the p- and n-transistors
reversed.
5. Region 5:
 In region 5, Vin = logic 1and the n-transistor is fully on while the p-transistor
is fully off.
 No current flows and a good logic 0 appears at the output.

BICMOS Inverters
 It consists of two bipolar transistors T1 and T2 with one nMOS transistor
T3, and one pMOS transistor T4, both being enhancement mode devices.
 With Vin= 0 volts (GND) T3 is off so that T1 will be non-conducting. But T4
is on and supplies current to the base of T2 which will conduct and act as a
current source to charge the load CL toward +5 volts(Vdd). The output of the
inverter will rise to +5 volts less the base to emitter voltage VBE of T2.
 With Vin = +5 volts (Vdd) T4 is off so that T2 will be non-conducting. But
T3 will now be on and will supply current to the base of T1 which will

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 conduct and act as a current sink to the load CL discharging it toward 0 volts
(GND). The output of the inverter will fall to 0 volts.

 An improved version of this circuit is given in Figure below, in which the

DC path through T3 and T1 is eliminated, but the output voltage swing is
now reduced, since the output cannot fall below the base to emitter voltage
V8E of T1.

 An improved inverter arrangement, using resistors, is shown in Figure

below. In this circuit resistors provide the improved swing of output voltage
when each bipolar transistor is off, and also provide discharge paths for base
current during turn-off.

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LATCH-UP IN CMOS CIRCUITS
 Latch-up is a condition in which the parasitic components give rise to the
establishment of low-resistance conducting paths between VDD and VSS
with disastrous results. Careful control during fabrication is necessary to
avoid this problem.
 There are, in effect, two transistors and two resistances which form a path
between VDD and VSS. If sufficient substrate current flows to generate
enough voltage across R5 to turn on transistor T1, this will then draw current
through Rp and, if the voltage developed is sufficient, T2 will also turn on,
establishing a self-sustaining low-resistance path between the supply rails.
 If the current gains of the two transistors are such that β1 x β2 > 1, latch-up
may occur.

 The switching characteristic of the arrangement is outlined in Figure above

 Remedies for the latch-up problem include:

1. An increase in substrate doping levels with a consequent drop in the value of
Rs
2. Reducing RP by control of fabrication parameters and by ensuring a low
contact resistance to Vss;
3. Other more elaborate measures such as the introduction of guard rings.

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SHEET RESISTANCE Rs
Consider a uniform slab of conducting material of resistivity p, of width W,
thickness t, and length between faces L. The arrangement is shown in Figure below

Consider the resistance RAB between two opposite faces.

Where A = cross-section area = t.W

Now, consider the case in which L = W, that is, a square of resistive material, then

Where Rs = ohm per square or sheet resistance

Thus the actual values associated with the layers in a MOS circuit depend on the
thickness of the layer and the resistivity of the material forming the layer.

BASIC VLSI DESIGN

STANDARD UNIT OF CAPACITANCE □Cg.

The unit is denoted □Cg and is defined the gate-to-channel capacitance of a MOS
transistor having W = L = feature size, that is, a 'standard' or 'feature size' square.

SOME AREA CAPACITANCE CALCULATIONS:

The approach will be demonstrated using λ-based geometry. The calculation of

capacitance values may now be undertaken by establishing the ratio between the
area of interest and the area of standard (feature size square) gate (2λ x 2λ for λ-
based rules) and multiplying this ratio by the appropriate relative C value from
Table below. The product will give the required capacitance in □Cg units.

Consider the area defined in Figure. First, we must calculate the area relative to
that of a standard gate.

BASIC VLSI DESIGN

Example 1:

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THE DELAY UNIT

If we consider the case of one standard (feature size square) gate area capacitance
being charged through one feature size square of n channel resistance (that is,
through Rs for an nMOS pass transistor channel).

However, in practice, circuit wiring and parasitic capacitances must be allowed for
so that the figure taken for t is often increased by a factor of two or three so that for
5 µm circuit
𝜏 = 0.2 to 0.3 nsec is a typical design figure used in assessing likely worst case
delays.

INVERTER DELAYS:

nMOS Inverter Delay:

If we consider a pair of cascaded inverters, then the delay over the pair will be
constant irrespective of the sense of the logic level transition of the input to the
first.
Assuming t = 0.3 nsec and making no extra allowances for wiring capacitance, we
have an overall delay of 𝜏 + 4𝜏 = 5𝜏. In general terms, the delay through a pair of
similar nMOS inverters is

Thus, the inverter pair delay for inverters having 4: 1 ratio is 5𝜏

BASIC VLSI DESIGN

CMOS Inverter Delay:

When considering CMOS inverters, the nMOS ratio rule no longer applies, but we
must allow for the natural asymmetry of the usually equal size pull-up p-transistors
and the n-type pull-down transistors.

overall delay=2𝜏 + 5𝜏 = 7𝜏

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Estimation of CMOS Inverter Delay
Rise-time estimation

In this analysis we assume that the p-device stays in saturation for the entire
charging period of the load capacitor CL.
The saturation current for the p-transistor is given by

This current charges CL and, since its magnitude is approximately constant, we

have

Substituting for Idsp and rearranging we have

We now assume that t = 𝜏r when Vout = + VDD so that

with 𝑉 = 0.2VDD then

𝟐𝑽𝑫𝑫 𝑪𝑳 𝟐𝑽𝑫𝑫 𝑪𝑳
𝝉𝒓 = =
𝜷𝒑 (𝑽𝑫𝑫 𝟎.𝟐𝑽𝑫𝑫 )𝟐 𝜷𝒑 (𝟎.𝟖𝑽𝑫𝑫 )𝟐

BASIC VLSI DESIGN

 Fall-time estimation
Similar reasoning can be applied to the discharge of CL through the n-transistor.

Making similar assumptions we may write for fall-time:

Super Buffers:

An inverting type is shown in Figure.

A positive going logic transition Vin at the input, it will be seen that the inverter
formed by T1 and T2 is turned on and, thus, the gate of T3 is pulled down toward 0
volt with a small delay. Thus, T3 is cut off while T4 (the gate of which is also
connected to Vin) is turned on and the output is pulled down quickly.

A negative going logic transition Vin at the input: when Vin drops to 0 volt, then
the gate of T3 is allowed to rise quickly to VDD· Thus, as T4 is also turned off by
Vin, T3 is made to conduct with Vin on its gate, that is, with twice the average
voltage that would apply if the gate was tied to the source as in the conventional
nMOS inverter.

BASIC VLSI DESIGN

The corresponding non-inverting nMOS super buffer circuit is given at Figure
below.

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 MODULE 3
STICK DIAGRAMS:

Stick diagrams may be used to convey layer information through the use of a color
code for example, in the case of nMOS design, green for n-diffusion, red for
polysilicon, blue for metal, yellow for implant, and black for contact areas.

Encodings for a simple metal nMOS process

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Encodings for a double metal CMOS p-well process

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nMOS Design Style:

Inverter:

NAND Gate

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NOR Gate:

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CMOS Design Style

Inverter:

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NAND GATE:

NOR GATE:

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F=(A+B)+C:

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Lambda-based Design Rules
All paths in all layers will be dimensioned in λ units and subsequently λ can be
allocated an appropriate value compatible with the feature size of the fabrication
process. This concept means that the actual mask layout design takes little account
of the value subsequently allocated to the feature size, but the design rules are such
that,· if correctly obeyed, the mask layouts will produce working circuits for a
range of values allocated to λ.

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BASIC VLSI DESIGN
 Module-4
SWITCH LOGIC

 Switch logic is based on the 'pass transistor' or on transmission gates.

 Switch logic may be formed from simple n- or p-pass transistors or from
transmission gates (complementary switches) comprising an n-pass and a p-
pass transistor in parallel.
 The reason for adopting the apparent complexity of the transmission gate,
rather than using a simple n-switch or p-switch in most CMOS applications,
is to eliminate the undesirable threshold voltage effects which give rise to
the loss of logic levels in pass transistors.

 When using nMOS switch logic, there is one restriction which must always
be observed no pass transistor gate input may be driven through one or more
pass transistors.
 Logic levels propagated through pass transistors are degraded by threshold
voltage effects.
 Since the signal out of pass transistor T1 does not reach a full logic 1, but
rather a voltage one transistor threshold below a true logic 1, this degraded
voltage would not permit the output of T2 to reach an acceptable logic 1
level.

 Transmission gates have good logic levels.

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  Pass Transistors:

And Operation:

OR operation:

a) CMOS

b) nMOS

Gate logic inverter

 Some of the most commonly used inverter circuit diagrams, the inverter
symbol, and the corresponding stick and symbolic diagrams is shown in the
figure below.
 In this configuration the depletion mode device is called the pull-up (p.u.)
and the enhancement mode device the pull-down (p.d.) transistor.

BASIC VLSI DESIGN

  When Vin is logic 0, enhancement nmos is OFF. Hence current flows
through depletion nmos to the output voltage i.e.Vout=Vdd or Vout=logic 1.
 When Vin is logic 1, enhancement nmos is ON. Hence current flows from
Vdd to ground via enhancement and depletion nmos. Vout = 0 or logic 0.

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For the given dimension of the inverter 8:1find the power dissipation

Given 𝐿 = 16λ, 𝑊 = 2λ, 𝐿 = 2λ, 𝑊 = 2λ, V=5v

𝑍 = = =8

𝑅 =𝑍 × 𝑅 = 8 × 10𝑘Ω = 80𝑘Ω

Similarly

𝑍 = = =1

𝑅 =𝑍 × 𝑅 = 1 × 10𝑘Ω = 10𝑘Ω

For the given dimension of the inverter 4: or 8:1 find the power dissipation

Given 𝐿 = 8λ, 𝑊 = 2λ, 𝐿 = 2λ, 𝑊 = 4λ, V=5v

𝑍 = = =4

𝑅 =𝑍 × 𝑅 = 4 × 10𝑘Ω = 40𝑘Ω

Similarly

𝑍 = = =

𝑅 =𝑍 × 𝑅 = × 10𝑘Ω = 5𝑘Ω

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NAND gates:

The critical factor here is that the output voltage Vout must be near enough to
ground to turn off any following inverter-like stages, that is

Applying Voltage divider rule

BASIC VLSI DESIGN

where Zp.d applies for any one pull-down transistor. The boundary condition then
is
𝑍 . = 4 ∗ 𝑛𝑍 .

𝑛𝑍𝑝.𝑑 𝑛𝑍𝑝.𝑑 1
= = = 0.2
𝑛𝑍𝑝.𝑑 + 4𝑛𝑍𝑝.𝑑 5𝑛𝑍𝑝.𝑑 5
.
nMOS Nand ratio= =
.

 The ratio between Zp.u. and the sum of all the pull-down Zp.d must be 4:1.
 This ratio must be adjusted appropriately if input signals are derived through
pass transistors.
 nMOS Nand gate area requirements are considerably greater than those of a
corresponding nMOS inverter, since not only must pull-down transistors be
added in series to provide the desired number of inputs, but, as inputs are
added, so must there be a corresponding adjustment of the length of the pull-
up transistor channel to maintain the required overall ratio .
 nMOS Nand gate delays are also increased in direct proportion to the
number of inputs added. If each pull-down transistor is kept to minimum
size , then each will present 1□Cg at its input, but if there are n such inputs,
then the length and resistance of the pull-up transistor must be increased by a
factor of n to keep the correct ratio.
 Thus, delays associated with the nMOS Nand are

NOR gates:

 Two-input Nor gate arrangements are given in Figure.

 This technologies, is preferred to the Nand gate when there is a choice.
 Since both 'legs' of the two-input nMOS Nor gate· provide a path to ground
from the pull-up transistor has the same ratio as would be the case for an
nMOS inverter.
 The area occupied by the nMOS Nor gate is reasonable since the pull-up
transistor dimensions are unaffected by the number of inputs accommodated.
 In consequence, the Nor gate is as fast as the corresponding inverter and is
the preferred inverter-based nMOS logic gate when a choice is possible.

BASIC VLSI DESIGN

Pseudo-nMOS logic:

 If we replace the depletion mode pull-up transistor of the standard nMOS

circuits with a p-transistor with gate connected to Vss, we have a structure
similar to the nMOS equivalent.
 This approach to logic design is illustrated by the three-input Nand gate in
Figure.
 The circuit arrangements look and behave much like nMOS circuits and
appropriate ratio rules must be applied.

BASIC VLSI DESIGN

  In order to determine the required ratio, we consider the arrangement of
Figure in which a pseudo-nMOS inverter is being driven by another similar
inverter, and we consider the conditions necessary to produce an output
voltage of Vinv for an identical input voltage:

Dynamic CMOS logic:

 The actual logic is implemented in the inherently faster nMOS logic, a p-

transistor is used for the precharging of the output line 'Z' so that the output
capacitance is charged to Vdd during the off period of the clock signal ɸ.
 During this same period the inputs are applied to the n-block and the state of
the logic is then evaluated during the on period of the clock when the bottom
n-transistor is turned on.

BASIC VLSI DESIGN

Problems in Dynamic CMOS:
 Charge sharing may be a problem unless the inputs are constrained' not to
change during the on period of the clock.
 Single phase dynamic logic structures cannot be cascaded since, owing to
circuit delays, an incorrect input to the next stage may be present when
evaluation begins, so that its output is inadvertently discharged and the
wrong output results
 One remedy is to employ a four-phase clock in which the actual signals used
are the derived clocks ɸ12,ɸ23,ɸ34,ɸ41.

A Parity Generator:

 A circuit is to be designed to indicate the parity of a binary number or word.

 Since the number of bits is undefined, we must find a general solution on a
cascadable bit-wise basis so that n can have any value. A suitably regular
structure is set out in Figure 6.15 and 6.16.
 From this, we may recognize a standard or basic one-bit cell from which an
n-bit parity generator may be formed. Such a cell is shown in Figure 6.17.
 A little reflection will readily reveal that the requirements are:

BASIC VLSI DESIGN

 A suitable arrangement for such a cell is given in stick diagram form

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Bus Arbitration Logic for n-line Bus:

 The functional requirements of this circuit are given by Figure and

associated truth table.

 If the highest priority line An is Hi (Logic 1 ), then output line 𝐴 will be Hi

and all other output lines Lo (Logic 0), irrespective of the state of the other
input lines A1 ----𝐴 .
 Similarly, 𝐴 will be Hi only when An-1 is Hi and An is Lo; again the state
of all input lines of lower priority (A1 - - - An-2) will have no effect and all
other output lines will be Lo.

BASIC VLSI DESIGN

 This requirement can be expressed algebraically as follows:

 This implementation seems the obvious one, but it does suffer from the fact
that as the input line under consideration moves down in significance so the
complexity of the logic grows.
 For example, we have shown only the top three lines in Figure, but it will be
seen that:
 An requires one diffusion path and no switches.
 An-1 requires two diffusion paths and two switches.
 An-2 requires three diffusion paths and four switches.

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  This is not a regular structure and is not well suited for VLSI
implementation. Therefore, we must take a cellular approach by setting out
the requirements in alternative fashion
 A regular structure having been arrived at, the requirements for each cell
may be expressed as follows:

 These requirements may be met by the circuit of Figure

 From which we could deduce

 The circuit realized in Figure below. This circuit is suitable for

implementation in nMOS or in CMOS technology.

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Multiplexers (Data Selectors)

 The requirements and general arrangement of a four-way multiplexer are set

out in Figure , from which we may write, where S1 and S0 are the selector
inputs

 A direct n-switch logic implementation using nMOS and CMOS which is

given as Figure in stick diagram form

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A General Logic Function Block

 An arrangement to generate any function of two variables (A, B) is readily

formed from any form of four-way multiplexer.
 The general approach is indicated in Figure.
 It will be seen that the required function is generated by driving the
multiplexer select inputs from the required two variables A and B and by
'programming' the inputs I0-I3 appropriately with Os and 1 s, as indicated in
the figure.
 Larger multiplexers may be similarly employed to generate any function of
up to four variables (16-way multiplexer).

BASIC VLSI DESIGN

A Four-line Gray Code to Binary Code Converter

 By inspecting (or mapping from) Table , it will be seen that the following
expressions relate the two codes:

 A suitable arrangement is set out in Figure below, and the only detailed
design required is that of a two input Exclusive-Or gate. Many arrangements
are possible to implement this operation

BASIC VLSI DESIGN

  Exclusive-Or gate made up of standard logic gates, as in Figure below

BASIC VLSI DESIGN

 MODULE 5

Clocked sequential circuits: Dynamic Register Element

 The basic dynamic register element is shown in Figure in mixed stick/circuit

notation and may be seen to consist of three transistors for nMOS and four
for CMOS per stored bit in complemented form.

 (Vin)t is clocked in by ɸ1 (or ɸ2) of the clock and charges the gate
capacitance Cg of the inverter to Vin.
 If subscript t is taken to represent the time during which ɸ1 (say) is at logic 1
and subscript t + 1 is taken to indicate the period during which ɸ1 is at logic
0, then the available output will be ( 𝑉𝚤𝑛 )t+1 which will be maintained by the
stored charge on the gate until Cg discharges or until the next ɸ1 signal
occurs.
 If uncomplemented storage is essential, the basic element is modified as
indicated in Figure below and will be seen to consist of six transistors for
nMOS and eight for CMOS.
 Data clocked in on ɸ1 is stored on Cg1 and the corresponding output appears
at the output of inverter 1.
 On ɸ2 this value is clocked into and stored by Cg2 and the output of inverter 2
then presents the 'true' form of the stored bit.

BASIC VLSI DESIGN

A Dynamic Shift Register

 A four-bit serial right shift nMOS register is illustrated in Figure below.

 Data bits are shifted in when ɸ1.LD is present, one bit being entered on each
ɸ1 signal (provided that LD is logic 1).
 Each bit is stored in Cg1 as it is entered, and then transferred complemented
into Cg2 during the next ɸ2.
 Thus, after a ɸ1 followed by ɸ2 signal, the stored bit is present at the output
of inverter 2.
 On the next ɸ1 the next input bit is stored in Cg1 and simultaneously the first
bit stored is passed on to inverter pair 3 and 4 by being stored in Cg3, and so
on.
 It will be seen that bits are thus clocked to the right along the shift register
on each ɸ1 followed by ɸ2 sequence.
 Once four bits are stored, the data is available in parallel form at the outputs
of inverters 2, 4, 6 and 8, and is also available in serial form from the output
of inverter 8 when ɸ1.
 RD is high as further clock sequences are received.

BASIC VLSI DESIGN

Bus lines

 There are three classes of bus-passive, active, and precharged.

1. Passive bus lines:

 A passive bus rail is a floating rail to which signals may be connected from
drivers through series switches, for example, pass transistors, to propagate
along the bus and from which signals may be taken, also through pass
transistors.

2. Active bus lines:

 A form of active bus is to treat the bus rail as a wired Nor connection which
has a common pull-up Rp.u. and n-type pull-down transistors or series n-type
transistor logic pull-downs where there are circuits which must be selected
to drive the bus.

BASIC VLSI DESIGN

 3. The Precharged Bus
 The precharged bus approach limits the effects of bus capacitance in that a
single pull-up transistor which is turned on only during ɸ 2 provides for the
bus to charge during the ɸ2 on period.

General considerations

1. Lower unit cost compared with other approaches to the same requirement.
2. Higher reliability High levels of system integration usually greatly reduce
interconnections-a weak spot in any system.
3. Lower power dissipation, lower weight, and lower volume compared with
most other approaches to a given system.
4. Better performance-particularly in terms of speed power product.
5. Enhanced repeatability. There are fewer processes to control if the whole
system or a very large part of it is realized on a single chip.
6. The possibility of reduced design/development periods (particularly for
more complex systems) if suitable design procedures and design aids are
available.

4-bit arithmetic processes

 Figure sets out the basic architecture of most, if not all, microprocessors

BASIC VLSI DESIGN

  The data path has been separated out in Figure below and it will be seen that
the structure comprises a unit which processes data applied at one port and
presents its output at a second port.
 Alternatively, the two data ports may be combined as a single bidirectional
port if storage facilities exist in the data path.

 Now we will decompose the data path into a block diagram showing the
main subunits.
 In doing this it is useful to anticipate a possible floor plan to show the
planned relative disposition of the subunits on the chip and thus on the mask
layouts.
 A block diagram is presented in Figure below

BASIC VLSI DESIGN

  A further decision must then be made about the nature of the bus
architecture linking the subunits.
 The choices in this case range from one-bus, two-bus or three-bus
architecture shown in Figure below.

 In pursuing this particular design exercise, it was decided to implement the

structure with two-bus architecture.
 In our planning we can now extend on our interconnections strategy by
planning for power rails and notionally making some basic allocation of
layers on which the various signal paths will be predominantly run.

BASIC VLSI DESIGN

  These additional features are illustrated in Figure below , together with a
tentative floor plan of the proposed design which includes some form of
interface (I/0) to the parent system data bus.

4-bit shifter

 Any general purpose n-bit shifter should be able to shift incoming data by up
to n - 1 place in a right-shift or left-shift direction.
 If we now further specify that all shifts should be on an 'end-around' basis,
so that any bit shifted out at one end of a data word will be shifted in at the
other end of the word, then the problem of right shift or left shift is greatly
eased.
 In fact, a moment's consideration will reveal, for a 4-bit word, that a 1-bit
shift right is equivalent to a 3-bit shift left and a 2-bit shift right is equivalent
to a 2-bit shift left, etc.
 Thus we can achieve a capability to shift left or right by zero, one, two, or
three places by designing a circuit which will shift right only (say) by zero,
one, two, or three places.

1. Crossbar switch:
 The arrangement is quite general and may be readily expanded to
accommodate n-bit inputs/outputs.
 In fact, this arrangement is overkill in that any input line can be connected to
any or all output lines-if all switches are closed, then all inputs are connected
to all outputs in one glorious short circuit.
 Furthermore, 16 control signals (sw00-sw15), one for each transistor switch,
must be provided to drive the crossbar switch, and such complexity is highly
undesirable.

BASIC VLSI DESIGN

 2. Barrel shifter:
 The interbus switches have their gate inputs connected in a staircase fashion
in groups of four.
 There are now four shift control inputs which must be mutually exclusive in
the active state.
 CMOS transmission gates may be used in place of the simple pass transistor
switches if appropriate.

BASIC VLSI DESIGN

  The structure of the barrel shifter is clearly one of high regularity and
generality and it may be readily represented in stick diagram form.

Regularity: Definition & Computation

 Regularity should be as high as possible to minimize the design effort

required for any system.
 The level of any particular design as far as this aspect is concerned may be
measured by quantifying regularity as follows:

 The denominator of this expression will obviously be greatly reduced if the

whole chip, or large parts of it, can be fabricated from a few standard cells,
each of which is relatively simple in structure.
 For the 4 x 4-bit barrel shifter just designed, the regularity factor is given by

BASIC VLSI DESIGN

  However, an 8 x 8-bit shifter, for example, would have a regularity factor of
64.

Practical aspects and testability: Some thoughts of performance:

 Two important parameters are speed and power dissipation.

 These factors are generally interrelated; power dissipation and area are also
interrelated in MOS technology.

1. Power dissipation:

 The simple case of an nMOS 8:1 inverter which may be set out with a
minimum feature size pull-down transistor giving a total resistance from
Vdd to GND of 90 kΩ.
 The maximum power dissipation for this particular design will thus be

 An alternative form of 8:1 inverter is to use a pull-down geometry 2λ long

and 6λ wide with a 6λ long, 2λ wide pull-up channel giving a Vdd to GND
resistance of 33 .3 kΩ and a consequent maximum power dissipation of

2. Speed:
 Take the simple case of one 8: 1 inverter driving another similar inverter.
 The longest delays will occur when the output of the first stage is changing
from logic 0 (Lo) to logic 1 (Hi), that is, the Δ transition of the output.
 The capacitances associated with the output and the input of the next stage
must charge through the pull-up resistance of the first stage as in Figure.
 It is also obvious that during the complementary ▼ transition the same
capacitances must be discharged through the pull-down transistor of the first
stage.

BASIC VLSI DESIGN

  For the minimum pull-down feature size nMOS 8:1 inverter

 For the alternative 8:1 inverter design

Summery Table.
Power Area Speed
2λ*2λ pull down Δ=40𝜏
0.278mW 36λ2
16λ*2λ pull up ▼=5𝜏
2λ*6λ pull down Δ=21𝜏
0.744mW 24λ2
6λ*2λ pull up ▼=0.66𝜏

Optimization: The CMOS Inverter

1. Area:
 The area of a basic CMOS inverter is proportional to the total area occupied
by the p- and n-devices.

 Minimum area can be achieved by choosing minimum dimensions for WP,

LP, Wn and Ln that is

BASIC VLSI DESIGN

 2. Switching power dissipation:
 Psd can be approximated by CL V2dd f where

 For fixed VDD and f, minimizing Psd requires minimizing CL which can be
achieved by minimizing the area A since CL is proportional to the gate areas
comprising A.

3. Asymmetry in rise and fall times:

 Can be equalized by using βn=βp This requires that
𝑊 𝑊
𝜇 =𝜇
𝐿 𝐿

𝑊 𝜇 𝑊
=
𝐿 𝜇 𝐿

 Assume Lp=Ln=2λ
𝜇
𝑊 = 𝑊
𝜇
Generally 𝜇 = 2 ∗ 𝜇
Hence
2𝜇
𝑊 = 𝑊
𝜇

𝑊
=2
𝑊
To compensate for the lower hole mobility µp, compared to electron mobility
µn
𝑊 = 2𝑊

BASIC VLSI DESIGN

CAD TOOLS FOR DESIGN AND SIMULATION

 The design of a chip of reasonable complexity can in time be completed 'by

hand' but it is both a hard and inefficient way of doing things.
 As far as the design of very large systems is concerned, it is essential to have
computer aids to design so that the design can be completed in a reasonable
time and, indeed, so that it can be completed at all.
 Tools are therefore essential to ensure first time (and every time) success in
silicon
1. Physical design layout and editing capabilities, either through textual or
graphical entry of information.
2. Structure generation/system composition capabilities, which may well be
part of the design layout software implementing Point 1;
3. Physical verification. The tools here should include design rule checking
(DRC), circuit extractors, ratio rule and other static checks, and a capability
to plot out and/or display for visual checking.
4. Behavioral verification. Simulation at various levels will be required to
check out the design before one embarks on the expense of turning out the
design in silicon.

 Simulators are available for logic (switch level) simulation and timing
simulation.
 Circuit simulation via such programs as SPICE is also possible, but may be
expensive in terms of computing time and therefore impractical for other
than small subsystems.
 Recent advances in simulators have made it possible to use the software as 'a
probe' to examine the simulated responses on various parts of the circuit to
input stimuli also provided via the simulator.

BASIC VLSI DESIGN