COURSE SYLLABUS

College Name: College of Engineering

Department Name: Department of Electrical & Computer Engineering
Course Name: Very Large Scale Integrated Circuits (VLSI)

COURSE INFORMATION

 Course Number/Section: ECEN 629

 Term:
 Semester Credit Hours: 3
 Times and Days:
 Class Location:

INSTRUCTOR CONTACT INFORMATION

 Instructor:
 Office Location:
 Office Phone:
 Email Address:

Faculty must notify students of the approximate time and method they can expect to receive an answer to all
communications (e.g., email, phone, course messages). Excluding holidays, the response should be provided within
48 hours.

If there’s a graduate teaching assistant assigned to work with this course, please include their names also.

STUDENT HOURS

These are times students may visit the professor without an appointment to request the assistance they need.
NOTE: Students are responsible for reading, understanding, and following the syllabus.

: AM / PM – : AM / PM

Monday Tuesday Wednesday Thursday Friday

COURSE PREREQUISITES

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Course Syllabus (rev 05-15-20 by the Extended Campus)
 Graduate standing

COURSE DESCRIPTION

This course introduces CMOS technology and devices for design and implementation of digital
integrated circuits. Propagation delay and power dissipation of static and dynamic combinational and
sequential logic circuits are studied. Method of Logical Effort is introduced for predicting path delays.
Layout design rules and verification tools are introduced. Design examples include Arithmetic Units
and Memory and Array

STUDENT LEARNING OBJECTIVES/OUTCOMES (SLO)

Learning outcomes should be specific, measurable, and focused on the content knowledge the students are
expected to master and not what the faculty will teach.

If the course is a General Education Course, the SLO should be listed and labeled as “General Education.”

SLO 1: Develop a firm background on CMOS technology and device modeling

SLO 2: Analyze and simulate circuit building blocks used to realize complex digital integrated
circuits
SLO 3: Classify Static and Dynamic Logic Circuits
SLO 4: Analyze delay using Logical Effort
SLO 5: Design and simulate CMOS Sequential Logic Circuits
SLO 6: Design and simulate Arithmetic Circuits
SLO 7: Analyze and Simulate Timing Issues
SLO 8: Classify Memory Circuits
SLO 9: Design and simulate CMOS Memory Circuits

REQUIRED TEXTBOOKS AND MATERIALS

Any course-level subscriptions and tools linked in Blackboard Learn learning management system (LMS) should
be listed here. The Blackboard LMS must have links to their student data privacy statement.

REQUIRED TEXTS:

Jan M. Rabaey, “Digital Integrated Circuits- A DESIGN PERSPECTIVE”, 2nd Ed., Prentice-Hall,
Inc., 2003, ISBN 9780130909961

REQUIRED MATERIALS:

SUGGESTED COURSE MATERIALS

SUGGESTED READINGS/TEXTS:

Kang & Leblebici, “CMOS Digital Integrated Circuits: Analysis and Design”, 3rd Ed., McGraw-Hill,
1999, ISBN 0-07-292507-8.

Weste & Eshraghian, “Principles of CMOS VLSI Design: A System Perspective”, 2nd Ed., 1994, ISBN
0-201-53376-6.

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Course Syllabus (rev 05-15-20 by the Extended Campus)
 Ivan Sutherland, Bob Sproull, and David Harris, “Logical Effort-Designing Fast CMOS Circuits”, Morgan
Kaufmann Publishers, 1999, ISBN 1-55860-557-6.
David Harris, “Skew-Tolerant Circuit Design”, Morgan Kaufmann Publishers, 2001, ISBN 1-55860-636-X

SUGGESTED MATERIALS:

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Course Syllabus (rev 05-15-20 by the Extended Campus)
GRADING POLICY

ASSIGNMENTS AND GRADING POLICY

94% and above A 76% - 74% C

93% - 90% A- 73% - 70% C-
89% - 87% B+ 69% - 67% D+
86% - 84% B 66% - 64% D
83% - 80% B- 63% - 0% F
79% - 77% C+

For GRADUATE COURSES: See 2019-2020 Graduate Catalog p.38 for graduate grading scale and
Non-Graded Courses

GRADING ALLOCATION

Course grades are based on a weighted grading scale of 100%. The breakdown for the course is
as follows: [Faculty, please adjust according to your course.]

Category # of Activities Percentage

Grade Weight
Homework 6 25%
Midterm Exam 2 25%
Final Exam 1 20%
Projects 3 20%
Discussion Board 8 10%
Total 25 100%

COURSE POLICIES

USE OF BLACKBOARD AS THE LEARNING MANAGEMENT SYSTEM

Blackboard is the primary online instructional and course communications platform. Students can
access the course syllabus, assignments, grades, and learner support resources. Students are
encouraged to protect their login credentials, complete a Blackboard orientation, and log in daily to
the course.

Note: Uploading assignments through Blackboard presents a challenge for Chromebook users in
locating the files for submission. If you use a Chromebook, please be sure you also have access to
a Mac computer or Windows computer so you can fully participate in your Blackboard class. For
more information about student computer recommendations, please visit
https://hub.ncat.edu/administration/its/computer-recommendations.php.

MAKE-UP EXAMS

See << Update Academic Year >>Undergraduate Bulletin:

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Course Syllabus (rev 05-15-20 by the Extended Campus)
 https://www.ncat.edu/provost/academic-affairs/bulletins/index.php

For GRADUATE STUDENTS: See 2019-20 Graduate Catalog p. 54

EXTRA CREDIT

LATE WORK

SPECIAL ASSIGNMENTS

For GRADUATE STUDENTS: FAILING TO MEET COURSE REQUIREMENTS (Graduate Catalog

p.40)

For GRADUATE STUDENTS: CLASS ATTENDANCE (see 2019-20 Graduate Catalog p. 53-54)

Students are expected to attend class and participate on a regular basis in order to successfully
achieve course learning outcomes and meet federal financial aid requirements (34 CFR 668.22).
Class attendance in online courses is defined as active participation in academically-related course
activities. Active participation may consist of course interactions with the content, classmates,
and/or the instructor. Examples of academically-related course activities include, but are not limited
to:

 Completing and submitting assignments, quizzes, exams, and other activities within Blackboard
or through Blackboard (3rd-party products).

 Participating in course-related synchronous online chats, discussions, or meeting platforms

such as Blackboard Collaborate in which participation is tracked.

CLASSROOM CITIZENSHIP

Courtesy, civility, and respect must be the hallmark of your interactions.

COMPLIANCE WITH THE AMERICANS WITH DISABILITIES ACT

North Carolina A&T State University is committed to following the requirements of the Americans
with Disabilities Act Amendments Act (ADAAA) and Section 504 of the Rehabilitation Act.
If you need an academic accommodation based on the impact of a disability, you must initiate the
request with the Office of Accessibility Resources (OARS) and provide documentation in
accordance with the Documentation Guidelines at N.C. A&T. Once documentation is received, it
will be reviewed. Once approved, you must attend a comprehensive meeting to receive appropriate
and reasonable accommodations. If you are a student registered with OARS, you must complete
the Accommodation Request Form to have accommodations sent to faculty.

OARS is located in Murphy Hall, Suite 01 and can be reached at 336-334-7765, or by email at
accessibilityresources@ncat.edu. Additional information and forms can be found on the internet at
https://www.ncat.edu/provost/academic-affairs/accessibility-resources/index.php.

Please note: Accommodations are not retroactive and begin once the Disability Verification Form
is provided to faculty.
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Course Syllabus (rev 05-15-20 by the Extended Campus)
 TITLE IX

North Carolina A&T State University is committed to providing a safe learning environment for all
students—free of all forms of discrimination and harassment. Sexual misconduct and relationship
violence in any form are inconsistent with the university’s mission and core values, violates
university policies, and may also violate federal and state law. Faculty members are considered
“Responsible Employees” and are required to report incidents of sexual misconduct and
relationship violence to the Title IX Coordinator. If you or someone you know has been impacted
by sexual harassment, sexual assault, dating or domestic violence, or stalking, please visit the Title
IX website to access information about university support and resources. If you would like to speak
with someone confidentially, please contact Counseling Services at 336-334-7727 or the Student
Health Center at 336-334-7880.

TECHNICAL SUPPORT

If you experience any problems with your A&T account, you may call Client Technology Services
(formerly Aggie Tech Support and Help Desk) at 336-334-7195, or visit
https://hub.ncat.edu/administration/its/dept/ats/index.php.

FIELD TRIP POLICIES / OFF-CAMPUS INSTRUCTION AND COURSE ACTIVITIES

If applicable:

Off-campus, out-of-state, foreign instruction, and activities are subject to state law and
university policies and procedures regarding travel and risk-related activities. Information
regarding these rules and regulations may be found at
https://www.ncat.edu/campus-life/student-affairs/index.php.

STUDENT HANDBOOK

https://www.ncat.edu/campus-life/student-affairs/departments/dean-of-students/student-
handbook.php

STUDENT TRAVEL PROCEDURES AND STUDENT TRAVEL ACTIVITY WAIVER

https://hub.ncat.edu/administration/student-affairs/staff-resources/studen_activity_travel_waiver.pdf

OTHER POLICIES (e.g., Copyright Guidelines, Confidentiality, etc.)

STUDENT HANDBOOK

https://www.ncat.edu/campus-life/student-affairs/departments/dean-of-students/student-
handbook.php

Graduate Catalog

SEXUAL MISCONDUCT POLICY

https://www.ncat.edu/legal/title-ix/sexual-harassment-and-misconduct-policies/index.php

FAMILY EDUCATIONAL RIGHTS AND PRIVACY ACT (FERPA)

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Course Syllabus (rev 05-15-20 by the Extended Campus)
 https://www.ncat.edu/registrar/ferpa.php

STUDENT COMPLAINT PROCEDURES

https://www.ncat.edu/current-students/student-complaint-form.php

STUDENT CONDUCT AND DISCIPLINE

North Carolina A&T State University has rules and regulations that govern student conduct and
discipline meant to ensure the orderly and efficient conduct of the educational enterprise. It is the
responsibility of each student to be knowledgeable about these rules and regulations.

Please consult the following about specific policies such as academic dishonesty, cell phones,
change of grade, disability services, disruptive behavior, general class attendance, grade appeal,
incomplete grades, make-up work, student grievance procedures, withdrawal, etc.:

 Undergraduate Bulletin
https://www.ncat.edu/provost/academic-affairs/bulletins/index.php

 Graduate Catalog
https://www.ncat.edu/tgc/graduate-catalog/index.php

 Student Handbook
https://www.ncat.edu/campus-life/student-affairs/departments/dean-of-students/student-
handbook.php

ACADEMIC DISHONESTY POLICY

Academic dishonesty includes but is not limited to the following:

1. Cheating or knowingly assisting another student in committing an act of cheating or

other academic dishonesty;
2. Plagiarism (unauthorized use of another’s words or ideas as one’s own), which includes
but is not limited to submitting exams, theses, reports, drawings, laboratory notes or
other materials as one’s own work when such work has been prepared by or copied
from another person;
3. Unauthorized possession of exams or reserved library materials; destroying or hiding
source, library or laboratory materials or experiments or any other similar actions;
4. Unauthorized changing of grades, or marking on an exam or in an instructor’s grade
book or such change of any grade record;
5. Aiding or abetting in the infraction of any of the provisions anticipated under the general
standards of student conduct;
6. Hacking into a computer and gaining access to a test or answer key prior to the test
being given. N.C. A&T reserves the right to search the emails and computers of any
student suspected of such computer hacking (if a police report of the suspected hacking
was submitted prior to the search); and
7. Assisting another student in violating any of the above rules.

A student who has committed an act of academic dishonesty has failed to meet a basic
requirement of satisfactory academic performance. Thus, academic dishonesty is not only a basis
for disciplinary action, but may also affect the evaluation of a student’s level of performance. Any
student who commits an act of academic dishonesty is subject to disciplinary action.

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Course Syllabus (rev 05-15-20 by the Extended Campus)
 In instances where a student has clearly been identified as having committed an act of academic
dishonesty, an instructor may take appropriate disciplinary action, including loss of credit for an
assignment, exam, or project; or awarding a grade of “F” for the course, subject to review and
endorsement by the chairperson and dean.

For GRADUATE STUDENTS: Reference for academic dishonesty – 2010-2020 Graduate Catalog, p.58-
59

For GRADUATE STUDENTS: STUDENT RELIGIOUS OBSERVANCE (see Graduate Catalog,

p.55)

ASSIGNMENTS AND ACADEMIC CALENDAR

Include topics, reading assignments, due dates, exam dates, withdrawal dates, pre-registration and
registration dates, all holidays, and convocations.*

THE WEEK SUBJECT UNIT LEARNING READING IN

OF OUTCOMES (ULO) TEXT, ACTIVITY, HOMEWORK,
MM/DD/YY EXAM
Unit 1: Introduction ULO1: Describe Digital IC 1. Read: Jan M. Rabaey, “Digital
to Digital IC Design Design Flow (SLO1) Integrated Circuits- A DESIGN
and CMOS PERSPECTIVE”, 2nd Ed.,
Technology ULO2: Describe properties Prentice-Hall, Inc., 2003
of Digital ICs (SLO1) 2. Complete: Discussion Board
#2 (Introduction) (ULO 5)
ULO3: Explain Moore’s
Law, cost of IC chips
(SLO1)

ULO4: Describe the CMOS

Technology Process
(SLO1)

ULO5: Develop
perspective into nanometer
CMOS Technology (SLO1)
Unit 2: CMOS ULO1: Calculate I-V 1. Read: Jan M. Rabaey, “Digital
Device Modeling characteristics of nMOS Integrated Circuits- A DESIGN
and pMOS transistors PERSPECTIVE”, 2nd Ed.,
(SLO1) Prentice-Hall, Inc., 2003
2. Complete: Discussion Board
ULO2: Calculate parasitic #3 (ULO1, ULO2, ULO3)
capacitances of nMOS and 3. Complete: Homework
pMOS transistors (SLO1) #1(ULO1, ULO2, ULO3,
ULO4, ULO5)
ULO3: Calculate on-
resistance, Ron, of nMOS
and pMOS transitors
(SLO1)
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Course Syllabus (rev 05-15-20 by the Extended Campus)
 THE WEEK SUBJECT UNIT LEARNING READING IN
OF OUTCOMES (ULO) TEXT, ACTIVITY, HOMEWORK,
MM/DD/YY EXAM

ULO4: Calculate Cequiv

for time-varying parasitic
capacitances (SLO1)

ULO5: Simulate I-V

characteristics and noise
performance of nMOS and
pMOS transistors (SLO1)
Unit 3: Interconnect ULO1: Explain parasitic 1. Read: Jan M. Rabaey, “Digital
Modeling I capacitances and Integrated Circuits- A DESIGN
resistances of wires PERSPECTIVE”, 2nd Ed.,
(SLO2) Prentice-Hall, Inc., 2003
2. Complete: Discussion Board
ULO2: R,L, and C lumped #4 (ULO1, ULO2, ULO5)
and distributed
representation of
Interconnects (SLO2)

ULO3: Analyze time delay

using Elmore Delay model
(SLO2)

ULO4: Explain Reliability

and electromigration
(SLO2)
ULO5: Describe IR drop
and transmission-line
effects (SLO2)
Unit 4: Interconnect ULO1: Describe the 1. Read: Jan M. Rabaey, “Digital
Modeling II Voltage Transfer Integrated Circuits- A DESIGN
Characteristic (VTC) of the PERSPECTIVE”, 2nd Ed.,
CMOS Inverter (SLO2) Prentice-Hall, Inc., 2003
2. Complete: Homework #2
ULO2: Derive expressions (ULO2, ULO3, ULO4, ULO5)
for VIL, VOL, and VM
(SLO2)

ULO3: Describe Dynamic

Behavior of the Inverter
(SLO3)

ULO4: Calculate
propagation delays, tPHL
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Course Syllabus (rev 05-15-20 by the Extended Campus)
 THE WEEK SUBJECT UNIT LEARNING READING IN
OF OUTCOMES (ULO) TEXT, ACTIVITY, HOMEWORK,
MM/DD/YY EXAM
and tpLH (SLO2)

ULO5: Analyze Power

Dissipation (SLO2)
Unit 5: ULO1: Describe Static and 1. Read: Jan M. Rabaey, “Digital
Combinational Dynamic Combinational Integrated Circuits- A DESIGN
Logic I Logic Circuits (SLO2) PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
ULO2: Size transistors in 2. Complete: Project #1 (ULO1,
the Pull-up and Pull-down ULO2, ULO3, ULO4)
circuits (SLO2)

ULO3: Calculate static and

dynamic behavior of Static
CMOS Gates (SLO3)

ULO4: Analyze Ratioed

Logic Gates (SLO3)
Unit 06: ULO1: Analyze Pass- 1. Read: Jan M. Rabaey, “Digital
Combinational Transistor Logic Gates Integrated Circuits- A DESIGN
Logic II (SLO3) PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
ULO2: Employ Logical 2. Complete: Homework #3
Effort to calculate optimum (ULO1, ULO2)
delay of a CMOS Complex 3. Complete: Midterm #1 (ULO’s
Circuits (SLO4) of Units 1,2, 3, 4, and 5)
Unit 07: ULO1: Describe Dynamic 1. Read: Jan M. Rabaey, “Digital
Combinational Logic Gates (SLO3) Integrated Circuits- A DESIGN
Logic III PERSPECTIVE”, 2nd Ed.,
ULO2: Analyze charge- Prentice-Hall, Inc., 2003
sharing (SLO3) 2. Complete: Discussion Board
#5 (ULO 1-3)
ULO3: Employ Domino
Logic to design complex
logic circuits (SLO4)
Unit 08: Arithmetic ULO1: Describe Binary 1. Read: Jan M. Rabaey, “Digital
Building Blocks Adders and Multipliers Integrated Circuits- A DESIGN
(SLO6) PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
ULO2: Design a Full Adder 2. Complete: Discussion Board
(SLO6) #6 (ULO1, ULO2, ULO3)
3. Complete: Homework #4
ULO3: Design a Shifter (ULO1, ULO2)
(SLO3)
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Course Syllabus (rev 05-15-20 by the Extended Campus)
 THE WEEK SUBJECT UNIT LEARNING READING IN
OF OUTCOMES (ULO) TEXT, ACTIVITY, HOMEWORK,
MM/DD/YY EXAM

ULO4: Simulate a 16-Bit

Adder (SLO6)
Unit 09: Sequential ULO1: State and describe 1. Read: Jan M. Rabaey, “Digital
Logic I principles of Sequential Integrated Circuits- A DESIGN
Logic Circuits (SLO5) PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
ULO2: Design Static 2. Complete: Project #2 (ULO1,
Latches and Registers ULO2, ULO3)
(SLO5)

ULO3: Describe the

principles of bistability
(SLO5)
Unit 10: Sequential ULO1: Design Dynamic 1. Read: Jan M. Rabaey, “Digital
Logic II Latches and Registes Integrated Circuits- A DESIGN
(SLO5) PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
ULO2: Explain the concept 2. Complete: Homework #5
of Pipelining (SLO5) (ULO1, ULO2, ULO3)

ULO3: Analyze
Nonbistable Circuits
(SLO5)
Unit 11: Timing ULO1: Describe Timing 1. Read: Jan M. Rabaey, “Digital
Issues I classification of Digital Integrated Circuits- A DESIGN
Systems (SLO7) PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
ULO2: Analyze Clock 2. Complete: Midterm #2 (ULO’s
Distribution Circuits of Units 6,7,8,9,10)
(SLO7)

ULO3: Describe Clock

Skew and Jitter (SLO7)
Unit 12: Timing ULO1: Analyze Self-Timed 1. Read: Jan M. Rabaey, “Digital
Issues II Circuits (SLO7) Integrated Circuits- A DESIGN
PERSPECTIVE”, 2nd Ed.,
ULO2: Describe Prentice-Hall, Inc., 2003
Synchronizers and Arbiters 2. Complete: Discussion Board
(SLO7) #7 (ULO1, ULO2, ULO3)
3. Complete: Project #3 (ULOs
ULO3: Understand Clock of Units 13 and 14)
Synthesis and PLL (SLO7)
Unit 13: CMOS ULO1: Describe ROM, 1. Read: Jan M. Rabaey, “Digital
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Course Syllabus (rev 05-15-20 by the Extended Campus)
 THE WEEK SUBJECT UNIT LEARNING READING IN
OF OUTCOMES (ULO) TEXT, ACTIVITY, HOMEWORK,
MM/DD/YY EXAM
Memory I RAM, DRAM, and Non- Integrated Circuits- A DESIGN
Volatile RAM (SLO8) PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
ULO2: Analyze ROM, 2. Complete: Homework #6
DRAM, SRAM (SLO8) (ULO1, ULO2, ULO3)

ULO3: Describe CAM

(SLO8)
Unit 14: CMOS ULO1: Analyze Memory 1. Read: Jan M. Rabaey, “Digital
Memory II Peripheral Circuitry (SLO9) Integrated Circuits- A DESIGN
PERSPECTIVE”, 2nd Ed.,
ULO2: Describe Memory Prentice-Hall, Inc., 2003
Reliability (SLO9) 2. Complete: Discussion Board
#8 (ULO1, ULO2, ULO3)
ULO3: Describe Flash
Memory Circuits (SLO9)
Unit 15: Final Exam 1. Read: Jan M. Rabaey, “Digital
Integrated Circuits- A DESIGN
PERSPECTIVE”, 2nd Ed.,
Prentice-Hall, Inc., 2003
2. Complete: Final Exam (ULO’s
of all Units)

* These descriptions and timelines are subject to change at the discretion of the instructor.

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Course Syllabus (rev 05-15-20 by the Extended Campus)