Sequential Circuits in Verilog
Q1: D-Latch
Verilog Code
// D-Latch
module D_Latch (input D, input En, output reg Q);
always @ (D or En) begin
if (En)
Q = D;
end
endmodule
Testbench
// Testbench for D-Latch
module tb_D_Latch;
reg D, En;
wire Q;
// Instantiate D_Latch
D_Latch dut (.D(D), .En(En), .Q(Q));
initial begin
$dumpfile("d_latch.vcd");
$dumpvars(0, tb_D_Latch);
D = 0; En = 0; #10;
D = 1; En = 0; #10;
D = 0; En = 1; #10;
D = 1; En = 1; #10;
$finish;
end
endmodule
Q2: SR-Latch
Verilog Code
// SR-Latch
module SR_Latch (input S, input R, output reg Q, output reg Qbar);
always @ (S or R) begin
if (S & ~R) begin
Q = 1;
Qbar = 0;
end else if (~S & R) begin
Q = 0;
Qbar = 1;
end else if (S & R) begin
Q = 1'bx;
Qbar = 1'bx;
end
end
endmodule
Testbench
// Testbench for SR-Latch
module tb_SR_Latch;
reg S, R;
wire Q, Qbar;
// Instantiate SR_Latch
SR_Latch dut (.S(S), .R(R), .Q(Q), .Qbar(Qbar));
initial begin
$dumpfile("sr_latch.vcd");
$dumpvars(0, tb_SR_Latch);
S = 0; R = 0; #10;
S = 1; R = 0; #10;
S = 0; R = 1; #10;
S = 1; R = 1; #10;
S = 0; R = 0; #10;
$finish;
end
endmodule
Q3: JK-Latch
Verilog Code
// JK-Latch
module JK_Latch (input J, input K, input En, output reg Q);
always @ (J or K or En) begin
if (En) begin
if (~J & K)
Q = 0;
else if (J & ~K)
Q = 1;
else if (J & K)
Q = ~Q;
end
end
endmodule
Testbench
// Testbench for JK-Latch
module tb_JK_Latch;
reg J, K, En;
wire Q;
// Instantiate JK_Latch
JK_Latch dut (.J(J), .K(K), .En(En), .Q(Q));
initial begin
$dumpfile("jk_latch.vcd");
$dumpvars(0, tb_JK_Latch);
J = 0; K = 0; En = 1; #10;
J = 1; K = 0; En = 1; #10;
J = 0; K = 1; En = 1; #10;
J = 1; K = 1; En = 1; #10;
J = 1; K = 1; En = 0; #10;
$finish;
end
endmodule
Q4: D-Flipflop with Asynchronous Active Low Reset
Verilog Code
// D Flip-Flop with asynchronous active low reset
module D_FF_Async_Reset (input D, input clk, input reset_n, output reg Q);
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
Q <= 0;
else
Q <= D;
end
endmodule
Testbench
// Testbench for D Flip-Flop with async reset
module tb_D_FF_Async_Reset;
reg D, clk, reset_n;
wire Q;
// Instantiate D_FF_Async_Reset
D_FF_Async_Reset dut (.D(D), .clk(clk), .reset_n(reset_n), .Q(Q));
always #5 clk = ~clk; // Generate clock signal
initial begin
$dumpfile("d_ff_async_reset.vcd");
$dumpvars(0, tb_D_FF_Async_Reset);
clk = 0; D = 0; reset_n = 0; #10;
reset_n = 1; D = 1; #10;
D = 0; #10;
D = 1; #10;
reset_n = 0; #10;
reset_n = 1; D = 0; #10;
$finish;
end
endmodule
(More circuits and testbenches will be added for the remaining questions.)
