Understanding Digital logic

Every manufacturer uses a different method to display their logic.

However, they all use the same
basic logic elements. We will review the basic logic principles in this
chapter then apply these
principles to protective relays.
1. understanding logic
Basic logic can be separated into the following logic functions: OR,
AND, NOT, NAND, NOR,
XOR, and XNOR. A single logic function is called an “operator” or
“gate.” A logic gate has
inputs and outputs that can be used in conjunction with other logic
gates (logic functions)
inside the relay. Logic is expressed in binary terms which means
that an input/output can be
in only one of two states, ON (1) (also called “Active” or “Enabled”)
or OFF (0). The number of
inputs for any gate is limited by the manufacturer’s interface, and
all examples are shown with
two inputs for simplicity’s sake.
A) oR
The OR function is the most common gate used in relaying
applications. An OR gate will be
ON (1) if ANY of its inputs are in the ON (1) state. If all inputs are
OFF (0), the output will
be OFF (0). The electrical equivalent of an OR gate is normally-open
contacts in parallel.
OR OR
1
OR
11
1
OR
10
1
OR
00
0
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
NORMALLY-OPEN
CONTACTS
IN PARALLEL
Figure 16-1: OR Gate Logic
Principles and Practice
474
B) AND
The AND function will be ON (1) if ALL its inputs are ON (1). If any
input is OFF (0), the
output will be OFF (0). The electrical equivalent of an AND gate is
normally-open contacts
in series.
AND
&
11
1
10
0
00
0
AND
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
NORMALLY-OPEN
CONTACTS
IN SERIES
Figure 16-2: AND Gate Logic
C) NoT
The NOT gate reverses the state of any input/output and is usually
represented as a circle
connected to an input or output. If the input to a NOT is OFF (0), its
output is ON (1) and
visa-versa. The electrical equivalent of a NOT gate uses a relay with
a normally-closed
contact.
01
10
R1
R1
NOT
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
RELAY WITH
NORMALLYCLOSED
CONTACTS
Figure 16-3: NOT Logic
Chapter 16: Understanding Digital Logic
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D) NoR
NOR gates are not as common as OR, AND, or NOT gates and
represent the opposite of an
OR gate. Its symbol includes an OR gate with a NOT connected to
the output. If any input
is ON (1), the output is OFF (0). NOR gates only turn ON (1) when all
inputs are OFF (0).
The electrical equivalent of a NOR gate is normally-closed contacts
in series.
NOR
NOR 0
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
NORMALLY-CLOSED
NOR CONTACTS IN SERIES
10
1 NOR
10
0 NOR
01
Figure 16-4: NOR Gate Logic
E) NAND
NAND gates are similar to NOR gates but they reverse the output of
an AND gate instead
of an OR gate. Therefore, the gate will be ON (1) if at least one input
is OFF (0). The
gate will be OFF (0) if all inputs are ON (1). The electrical equivalent
of a NAND gate is
normally-closed contacts in parallel.
NAND
11
0
10
00
NAND
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
1
1
NORMALLYCLOSED
CONTACTS
IN PARALLEL
Figure 16-5: NAND Gate Logic
Principles and Practice
476
F) xoR
The XOR gate is not available on most relay models and is
infrequently used. The XOR
gate is ON (1) if only one input is ON (1) and all other inputs are off.
It is the electrical
equivalent of an electrical-interlock like a forward/reverse motor
control circuit.
XOR
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
XOR
11
0
10
1
01
1
00
0
XOR
XOR
XOR
XOR
C1
C2
C2
C1
ELECTRICAL
INTERLOCK
Figure 16-6: XOR Gate Logic
G) xNoR
The XNOR gate is not available on most relay models and is
infrequently used. The XNOR
gate is ON (1) if all inputs are in the same state. All inputs must be
ON (1) or all inputs must
be OFF (0) for the gate to be ON (1). Its electrical equivalent is
normally-closed contacts
in parallel with normally-open contacts.
NORMALLYOPEN
IN
SERIES IN
PARALLEL
WITH
NORMALLYCLOSED
IN
SERIES
XNOR
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
XNOR
11
1
10
0
01
0
00
1
C1
C2
C2
C1
XNOR
XNOR
Figure 16-7: XNOR Gate Logic
Chapter 16: Understanding Digital Logic
477
H) Comparator
The comparator is not a common logic gate but is included here
because it is often found in
a relay’s internal logic schemes. A comparator compares an input to
a setpoint or reference
signal and turns ON (1) if the input is greater than the setpoint or
reference. The input is
typically an analog signal like a CT or PT and the comparator turns
the analog signal into
a digital signal to be used in the logic diagrams.
INPUT
SETPOINT
+-
INPUT > SETPOINT
SETPOINT 1
INPUT < SETPOINT
SETPOINT 0
COMPARATOR
DESCRIPTOR SYMBOL MATRIX
Figure 16-8: Comparator Logic
I) TIMER
Timers are not typically found in logic but are used extensively in
relays. Timers can be
on-delay and begin timing when its input is ON (1) or off-delay, and
begin timing after the
input has been removed. Time delays are defined by the user as a
relay setpoint or can
be pre-defined by the manufacturer. This logic device operates
exactly like an equivalent
electrical timer.
ON
OFF
1s
2s
0-1 1
AFTER 1s
1-0 0
AFTER 2s
ON DELAY
OFF DELAY
T1
ON-DELAY
(1.0 s)
T1
TIMER
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
0-1
1-0
T1
OFF-DELAY
(2 s)
Figure 16-9: Timer Logic
Principles and Practice
478
J) Summary of logic
AND
&
11
1
10
0
00
0
OR OR
1
OR
11
1
OR
10
1
OR
00
0
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
01
10
NORMALLY-OPEN
CONTACTS
IN PARALLEL
R1
R1
NORMALLYOPEN
IN
SERIES IN
PARALLEL
WITH
NORMALLYCLOSED
IN
SERIES
INPUT
SETPOINT
+-
INPUT > SETPOINT
SETPOINT
1
INPUT < SETPOINT
SETPOINT
0
ON
OFF
1s
2s
0-1 1
AFTER 1s
1-0 0
AFTER 2s
ON DELAY
OFF DELAY
AND
NOT
COMPARATOR
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
NORMALLY-OPEN
CONTACTS
IN SERIES
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
RELAY WITH
NORMALLYCLOSED
CONTACTS
DESCRIPTOR SYMBOL MATRIX
NOR
NOR 0
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
NORMALLY-CLOSED
NOR CONTACTS IN SERIES
10
1 NOR
10
0 NOR
01
NAND
11
0
10
00
NAND
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
1
1
NORMALLYCLOSED
CONTACTS
IN PARALLEL
XNOR
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
XNOR
11
1
10
0
01
0
00
1
C1
C2
C2
C1
XOR
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
XOR
11
0
10
1
01
1
00
0
XOR
XOR
XOR
XOR
C1
C2
C2
C1
ELECTRICAL
INTERLOCK
XNOR
XNOR
T1
ON-DELAY
(1.0 s)
T1
TIMER
DESCRIPTOR SYMBOL MATRIX ELECTRICAL EQUIVILANT
0-1
1-0
T1
OFF-DELAY
(2 s)
Figure 16-10: Summary of Logic Element Operation