SCAN

1. What is CTL?
CTL core test logic
All information the core provider needs to give for embedded core in SoC.
2. Explain scan insertion flow
Top Design-scan rule check and repair-testable design-scan configuration-scan
replacement-scan reordering-scan stiching-scan design-scan extraction-scan verification
3. How do you take care of clocks and resets during scan
Connected from top level
4. What are the D1 D2 D3 D5 D11 violations how will you fix??
D1: Checks for the possible disturbance of data values loaded or captured into scan cells.
D2: A violation occurs if there are multiple paths from the associated memory element
(MASTER or SLAVE) to the COPY and these paths can be sensitized at the same time
D3: The rule violation occurs if the master_observe procedure does not properly sensitize
the path between the SLAVE and MASTER.
D5: All memory elements (latches and flip-flops) must be scannable. The application
performs this check after identifying all scan memory elements. The rule violation occurs
for all memory elements not identified as part of a scan cell.
5. How will you decide on the capture pulse. example if the non-scan element is sitting
in between the scan flops
6. What is the issue faced during the scan & how will you fix them
DRC’s violations, need to debug those and need to add required
7. Which tool is used for scan insertion?
Tessent DFT Advisor, Cadence genus
8. What is a wrapper cell?
Wrapper cells are accessible from PI/PO either directly or combinational logic
9. What is core wrapping?
10. What is the difference between a dedicated wrapper and a shared wrapper
Shared wrapper---> inserted when we know about structure how pins to ports (combo
logic)are connected….there should not be any combo logic connected between input port to
pin and pin to output port.
dedicated wrapper---> finding combo logic is difficult so dedicated wrapper is used. If any
port is driving combo logic and it is connected without driving any output flop
11. 100 scan chain length how many tester cycle required to test?
Load+unload+capture=201 cycles
12. If shift clk working with 200MHz and at speed will work with 100 MHz or not?
It wont work
13. What is lockup latch? how to insert lockup latch cell??In which path will you insert
lockup latch?
To balance scan chains. When scan chains stitched together, there may be data slippage when
moving from one clk domain to another clk domain. So to reduce this, lockup cells are introduced
14. What are issues you have faced in scan insertion?
Synchronous circuitry
Asynchronous set & resets
Feedback loops
Gated clocks & clk dividers
Pulse geneartors
Incomplete designs
Make sure design is not overly constrained
All clks are properly initialized
15. What is the difference between a lockup latch and a terminal lockup latch?
Lockup latch provides half cycle delay
Terminal lockup latch  provides full cycle delay (automatically done by tool)
16. How do we do edge mixing and clock mixing?
Using lockup latch
17. When lockup latch is inserted
To eliminate skew
18. If there are 100000 flops and 2 external channels. what is the scan chain length.
Consider each channel connected 50 scan chains of each length of 1000 flops
19. How scan enable will work in chain testing?
Scan enable is 1 for chain testing
20. Scan DRC S1 and S2 and fixing
S1 - unstable non-scan cells when clocks off
S2 checks all clock inputs (not including sets and resets) of each non-scan
memory element to see whether they can capture data
22. How will you control the reset of a flop which is driven from other flop, where both
the flops are in scanchain?
We need to insert multiplexer in reset path of other flop
23. What is intest and extest in scan?
Extest mode ---> used to check interconnection between blocks
Intest mode ---> check logic between core logic
24. What is SCAN & Scan chain?
Scan is structured DFT technique used to increase testability of a design. Scan chain
consists of serially connected scan flops
25. What are the Trace violations you faced?
T3 & T5
26. Explain the Scan Validation Flow?
27. If there is 3 chains in your design having scan length of 250, 150, 50. How many clock
pulses are required. If 250 means, what about smaller chains? and some cross questions
on this
501 clock cycles are needed. In this case we need scan chain balancing
28. There is a 3-flop taking clock from same source but 3rd flop gating clock with some
skewed, what could be the reason, draw and explain.
29. During scan insertion what the things you have to need to take care.
30. Why we need spyglass? What are DRC’s fixed during spyglass?
31. What errors you got in scan? How did you sorted out?
Mostly DRC violations will come, we need to debug those need to define if any pins to be
initiated.
32. What is the advantage of spyglass?
33. Issues encountered in scan insertion?
C4 - Clock maybe affected by its captured data
D5 - Non-scan memory element
D6 - Non-transparent non-scan latches
S1 - unstable non-scan cells when clocks off
S3 - un-initialized non-clock PIs in clock cone
(Note)
C3 - clock may capture data affected by its captured data
S7 - Potentially scannable cell that is not in th clock path is driven by a constant value
34. Inputs & outputs for scan insertion?
Inputs  synthesized netlist, libraries, dofile
Outputs scan inserted netlist, scan reports & APG testproc, dofile
 36. What are the contents of SDC file?
An SDC file is a text file that contains timing constraints for a digital design
37. What is scan def file and where it is used?
Scan def file contains no of scan chains and how it connected
38. What was max chain length in your design?
We need to check in the block atpg log
39. Why do we have non scan flops in design?
It depends upon input constraints and logic specified to scan design
40. What is wrapper excluded ports and why?
JTAG, EDT & clock gaters
41. How to do TE hookup?
It should be connected to top level TDR or scan en
42. How were the clocks connected from top level and block level? Internal and external
clock in your architecture.
Through blocks
43. How do you decide which clock (fast or slow) has to propagate as PLL is free running
clock so do you directly connect it?
Fast clock
44. If there are 100 non scan flops are there, then how you will convert them scannable
flops & cross questions.
By scan insertion methodology
45. what is sequetial depth, how 2 capture pulses can covert the non scannable flops.
explain with example.
multiple clock cycles required to propagate fault through non scan cells to an observe
point
46. What is CTL? What is its usage?
All information the core provider needs to give for embedded core in soc
47. Have you done scan coverage analysis? –not valid
48. How are Scan chains stitched?
Based on clock domains
49.How are Clocks declared?
By add_clocks command
50.What is cutpoint?
Cutpoints are constraints added between chains
51. Difference between cutpoint and pin constraints?
Pin constraints are added through input level
52.Given Two flops, Asked to Stich in scan chain. There are two clock domain & 300 flops,
use 2 clock domain and asked me to stich 300 flops as scan chain?
53.How scan works?
we shift-in the values, initialize the primary inputs of the combinatorial logic, observe the
outputs, ONLY ONE CAPTURE pulse is given and shift-out the values.
54. How do you handle Scan/ATPG for multiple clock domains?
By inserting lockup latches if they have skew
55. Block A - 100000 flops in your design and 3 domains, explain DFT architecture for
this block
56. How are clocks handled in dedicated vs shared wrappers?
We need to maintain separated wrapper chain because it is driven by wrapper clock
Wrapper flop operation is different from normal scan flop
57. Explain wrappers functionality in intest vs extest?
Extest mode ---> used to check interconnection between blocks(i/p--s&c o/p--S)
Intest mode ---> check logic between core logic (i/p--s o/p--s&c)