HVDC Transmission Systems (3160921) VGEC Chandkheda

Vishwakarma Government Engineering College

Chandkheda
Department of Electrical Engineering

Academic Year: 2024-25

B. E. Semester 6

Manual for Laboratory work

HVDC Transmission Systems (3160921)

HVDC Transmission Systems (3160921) VGEC Chandkheda

INDEX
Sr. Page
Experiment
No. No

1 Components of HVDC Transmission system 3

2 6-Pulse HVDC Transmission System 18

3 12-Pulse HVDC Transmission System 23

4 Various FACTS Controllers models 30

5 Static VAR Compensator (SVC) in Power System 39

Thyristor-Controlled Series Capacitor (TCSC) in Power

6 45
System
Distribution Static Synchronous Compensator (DSTATCOM) in Power
7 52
System

8 Power Flow control in a five bus system using UPFC 61

9 Series Compensation of a Three-Phase Transmission Line 69

10 VSC-Based HVDC Link 73

2
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No.01

Components of HVDC Transmission System

AIM: To study about Components of HVDC Transmission System

The HVDC system basically uses DC for the power transmission and able to transmit the power between
the unsynchronized AC system. Hence, HVDC transmission system is divided into three fundamental
parts which are a converter station for AC to DC conversion (rectifier), transmission lines and another
converter station to convert back DC to AC (inverter). When design a HVDC transmission system, there
are several important components need to be considered. The main components are converter, harmonic
filters, reactive power source, smoothing reactor, electrodes, AC circuit breakers and DC lines. Figure 1
shows the schematic of HVDC transmission system to identify the main components.

Figure 1: Schematic of HVDC Transmission System.

1. Converters
The power electronic converter usually used to change the power parameters and
these parameters can be current, voltage or frequency. InHVDC transmission system, the
converter station is installed with thyristor based which convert AC to DC is called rectifier
while another converter station which convert DC to AC is called inverter. In additional, the
converterscontained valve bridges and transformers. The valve bridges are connected ina
3
HVDC Transmission Systems (3160921) VGEC Chandkheda

layout of 6 pulses or 12 pulses. The transformers are not grounded and hence the DC system
capable to set its reference to ground.

1.1 Smoothing Reactors

The smoothing reactor of HVDC is showed in Figure 2. HVDC smoothing reactor
can be designed as air core and oil-insulated unit as well. The connection between smoothing
reactor and converter is in series. The main functions of smoothing reactors are:

 To smooth the ripple currents in DC.

 To limit the fault currents in the DC line.

 To reduce the harmonic voltage and current in DC line.

 To avoid commutation failure in the inverter.

 To avoid current discontinuous for the loads.

Figure 2: HVDC Smoothing Reactor.

1.2 Harmonic Filters

4
HVDC Transmission Systems (3160921) VGEC Chandkheda

Harmonics are generated by HVDC converters in voltage and current. Generally, the AC
harmonics are occurred in the AC system, while the DC harmonics are occurred in the DC
lines. These harmonics can cause overheating on the capacitors and generators. Also,
interfere thetelecommunication systems. To minimize the harmonics, AC and DC filtersare
installed in HVDC system. The AC filters are based on RLC circuit which connects between
phase and ground. By using AC filters, the low impedances are supplied to harmonic
frequencies and resulting the AC harmonic currents passed through the ground. Both tuned
and damped filters can be used. Furthermore, the reactive power can be supplied by AC
harmonic filter to manipulate the converters efficiently. Connection between the neutral bus
and pole bus is DC filter. The DC filters are applied to divert the DC harmonics to ground
and avoid them getting into DC lines. Such a filter does not require reactive power as DC
line does not require DC power. Figure 2.6 shows the area of AC filter.

Figure 3: AC Harmonic Filter Area.

1.3 Reactive Power Source

At steady state condition, the reactive power required by converter is concerning half of
the active power transferred. The reactive power consumption may higher at transient
condition. Besides that, the additional supply also can be received from shunt capacitors.
1.4 Electrodes
Electrodes are the conductors used to make connection to the ground for neutral. The
functions of electrodes are reducing the current densities and surface voltage gradients.

1.5 AC Circuit Breakers

AC circuit breakers are usefulness to remove the faults in the transformer and prevent

5
HVDC Transmission Systems (3160921) VGEC Chandkheda

the DC links continuously function. But for DC fault, it can be removed by converter. The
AC circuit breakers are typically locatedat valve hall as shown in Figure 4.

Figure 4: AC Circuit Breakers.

1.6 Layout of HVDC Transmission System

Figure 5 shows the layout of HVDC transmission system. It consists of AC switchyard,

converter building and DC switchyard. The AC filters are located near the AC switchyard
and shunt capacitors are located beside the filters.

6
HVDC Transmission Systems (3160921) VGEC Chandkheda

Figure 5: Layout of HVDC Transmission System.

1.7 Types of HVDC Transmission System

In electric power sector, the HVDC transmission system can be designed in some
ways to support the price, flexibility and operational needs. The HVDC system can be
connected in different ways.

Back to Back HVDC System

The electric power transferred by HVDC system at the same place is

called back to back system. The structure of the system showed that two
converters are installed at the same place without using long DC line in the
power transmission system. Normally, the back to back HVDC system is
connected with two adjacent asynchronous AC system. These two AC system
interconnections are providing the frequency range in between 50 Hz and 60
Hz. Figure 6 shows the circuit diagram of back to back HVDC system.

7
HVDC Transmission Systems (3160921) VGEC Chandkheda

C C C

B
ridg

Figure 6: Circuit Diagram of Back to Back HVDC System.

1.8 Monopolar HVDC System

In Monopolar HVDC system, a single pole line is being used to separate the two
converter stations. By either ground or sea, the path of current is fully returned. Moreover,
this monopolar configuration can be used to connect the submarine cables for transmission
system. Figure 7 shows the circuit diagram of monopolar HVDC system.

Figure 7: Circuit Diagram of Monopolar HVDC System.

8
HVDC Transmission Systems (3160921) VGEC Chandkheda

1.9 Bipolar HVDC System

Two monopolar systems connected in parallel is known as bipolar HVDC system.

Bipolar system consists of two conductors which are positive and negative. Each system can
be operated separately as an independent system with the ground return. The currents
occurred in both poles are same, since one is positive and another is negative. Hence, the
ground current is zero or the ground current is within a difference of 1 percent. One of the
benefits is that the pole can still proceed for transmitting the power if a fault occurred on
another pole. Also, it is the most common use of configuration for HVDC transmission
system. Figure:8 shows the circuit diagram of bipolar HVDC system.

Figure 8: Circuit Diagram of Bipolar HVDC System.

1.10 Multi-terminal HVDC System

While, the system that involves three or more converter stations is known as multi-
terminal HVDC system. They are separated to different location and interconnected through
transmission cables or lines. This configuration has offered an effective way to transfer large
power and improvestability of the system. Figure 9 shows the circuit diagram of Multi-
terminal HVDC system.

9
HVDC Transmission Systems (3160921) VGEC Chandkheda

Figure 9: Circuit Diagram of Multi-terminal HVDC System

1.11 Types of Converter

Based on converter configuration, it consists of two different technologies used for
HVDC transmission system. They are Line Commutated Converter (LCC) and Voltage
Source Converter (VSC).

1.11.1 Line Commutated Converter (LCC)

In early research of the converter technology, the HVDC transmission system mainly
based on mercury valves. The major drawback of mercury-arc technology is ark-back fault
which damaged the rectifying property of the converter valve and consequently caused other
issues. Thus, a new thyristor valve technology has been found to overcome these problems.
Converter with mercury valve based or thyristor valve based is called line commutated
converter (LCC). LCC-HVDC converter generally formed by three phase and full wave
bridge circuit. Then, higher current and voltage thyristors is

10
HVDC Transmission Systems (3160921) VGEC Chandkheda

developed to eliminate the parallel connections and minimize the number of series
connections for thyristors at each valve (Toledo, P. F. D., 2003). Besides that, most of the
LCC-HVDC links are involved using submarine cables and there has no LCC-HVDC link
applied to converters on offshore substation. As shown in Figure 10, the LCC-HVDC
transmission system has the components like thyristor valves, AC filters, DC filters,
smoothing reactor,capacitor bank, converter transformer, DC cable and auxiliary power set.
The LCC-HVDC is a very successful technology and there are many expectations for LCC–
HVDC to grow better.

Figure 10: LCC – HVDC System

1.11.2 Voltage Source Converter (VSC)

Voltage-source converter (VSC) is a relatively new converter technology for HVDC
transmission system. After the development of Insulated Gate Bipolar Transistor (IGBT),
the VSC has been widely used for power transmission system. The world first VSC-HVDC
system is commissioned in Gotland island of Sweden in year 1999. Voltage-sourceconverter
is exploitation self-commutating switches which can be turned on or off easily (Toledo, P.
F. D., 2003). This showed that the reversed voltage can solely turns off the thyristor valve.
For HVDC applications, the converters have been categorized into three types which are two
level converter, three level converter and modular multilevel converter. The major features
of VSC are a four-quadrant operation capability, difficult design and higher power losses
compared to LCC. The circuit diagram of VSC – HVDC system is showed in Figure 11.

11
HVDC Transmission Systems (3160921) VGEC Chandkheda

Figure 11: VSC – HVDC System.

1.11.3Comparison of HVDC Converters

Table 1 shows a comparison of the LCC based and VSC based forHVDC transmission
system.

Table 1: Comparison of HVDC Converters.

LCC-based HVDC VSC-based HVDC

Power Up to 8000MW. Up to 1400MW.

Capability

Overload Good, continuous and short None.

Capability time.

AC System Strong existing network is Can operate into weak AC

Requirements required systems or no AC system.

Reactive Control by switching ac Control by the converter.

Power harmonic filters.

Harmonic Convertor generated Very low harmonic

Performance distortion reduced by ac distortion. No filters
and dc filters. required.

12
HVDC Transmission Systems (3160921) VGEC Chandkheda

Losses 0.8 % 1.0 %

Land Take Large site, dominated by 50 to 70% of LCC

the ac harmonic filters equivalent rating

Cable Mass impregnated (MI) Both MI and XLPE

Technology technology only. technologies are available.

13
HVDC Transmission Systems (3160921) VGEC Chandkheda

1.12 Comparison of AC and DC Transmissions

The electrical power needs to be transmitted either by AC or DC. Each system has their
own advantages and disadvantages. Hence, a comparative study is carried out to decide
which is the best system to transmit the electrical power over longer distance.

1.12.1 Advantages of HVDC Transmission System

1.12.2.1 DC transmits more power per conductor: An AC link and a DC link have different
capability to transmit the power. DC is required only two conductors as
compared to AC with three conductors as shown in Figure 2.15.

Figure 12: Three Conductors AC Tower versus Two Conductors DC

Tower.

1.12.2.2 Lower Space and Smaller Tower Size: The DC insulation level for a similar
power transmission is less than the corresponding AC level.

14
HVDC Transmission Systems (3160921) VGEC Chandkheda

Also, the DC line required only two conductors while three conductors are required for AC.
Hence, the electrical and mechanical design aspects brought the tower to become smaller.
Besides that, the DC transmission line lead to lower space requirement and the transmission
towers have been reduced from two to one transmission. Figure 2.16 shows the tower sizing
and land spacing for AC and DC transmission.

Figure 13: AC Transmission Tower versus DC Transmission Tower.

 Higher capacity available for cables: In review of the overhead line, the breakdown
cable is occurred by stimulate instead of external flashover. The main reason
behind is due to the absence of ionic motion. Moreover, the working stress of the
DC cable insulation is three times higher than AC (Behravesh, V. & Abbaspour, N.,
2012). Without continuous charge of current, the DC cable able to transmit higher
active power over the long distance.

 No skin effect: Under AC conditions, the current is not constantly

distributed over the conductor. From these conditions, it can be seen that

15
HVDC Transmission Systems (3160921) VGEC Chandkheda

the current density is larger in the outer region (skin effect) and end in
underutilization of the conductor cross-sectional. However, there are no skin
effect under the conditions of stable DC and result a constant current
supplied in the conductor that allows the conductor metal to have a better
use.

 Less corona and radio interference: The corona effects are lower when the
frequency increased for a specific conductor diameter and applied voltage.
Therefore, the radio interference with DC is lower. The cost of transmission
line is also reduced due to lesser use on conductors.

1.12.3 Disadvantages of HVDC Transmission System

1.12.3.1 Expensive converters: At each end of DC transmission link, an

expensive converter station is needed but AC transmission link only
needs transformer station.

1.12.3.2 Reactive power requirement: More reactive power is required for

converters during rectification and inversion. Each converter may use
up to half of the DC active power. (Behravesh, V. & Abbaspour, N.,
2012).

1.12.3.3 Generation of harmonics: Converters produce much harmonics for both

AC and DC sides. Thus, the filters are being used to minimize the
number of harmonics transmitted through the AC system. But for DC

16
HVDC Transmission Systems (3160921) VGEC Chandkheda

system, smoothing reactors are installed for same

purpose. Subsequently, these components cause the
system more expensive.

1.12.3.4 Difficulty of voltage transformation: In order to transmit higher

voltage, the DC transformers need to carry out the voltage
transformation on the AC system and avoid the DC system being
used alone.

1.12.3.5 Difficulty of high power generation: Because of some issues of

commutation with DC voltage, speed, machines and size are
restricted, the power generated by DC is relatively lower.

1.12.3.6 Absence of overload capacity: Converters have lower overload

capability in contrast to transformers.
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment no: 02
Six-pulse bridge configurations
AIM: To study about Six-pulse bridge configurations

In a bridge configuration, the number of pulses is twice the number of phases (p = 2m). It is
possible to obtain the same values for the rectified voltage and ripple factor using fewer phases, i.e.,
simpler transformers with fewer windings and better utilization factor (fewer oversized
transformers).
Starting from the basic 6-pulse structure shown in Fig. 1 it is possible to combine two bridges in
order to obtain 12 or more pulse rectifiers.
The PIV on the diodes in a bridge rectifier is half the PIV in an equivalent star rectifier: it is possible
to use components with a lower VRRM.

Fig. 1: Three-phase bridge rectifier

In Fig. 11 the secondary of the transformer is connected as a ‘Y’. Starting from a three-phase
mains distribution there are four possible combinations for the connections at the primary and the
secondary of the transformer: delta–delta, delta–Y, Y–delta and Y–Y (Fig. 12). They are not
equivalent. A delta primary requires three mains lines, without neutral, and avoids the so-called
excitation unbalance. With this connection, each winding is tied between two lines, the
nonsinusoidal exciting currents can be taken from the supply system so that there is a complete
ampere-turn balance and the excitation unbalance is avoided [10].

18
HVDC Transmission Systems (3160921) VGEC Chandkheda

Fig. 2: Three-phase transformer connections (P = primary, S = secondary)

The Y secondary has some advantages compared to a delta one with the same turn
ratio
windings is the same as in the load; there is an easily accessible common zero-point in case one
wants to get two voltages with opposite sign (each side of the bridge acts as a single-way rectifier
with m = 3).
The bridge structure is a double-way configuration; the secondary windings do not carry
any DC component and the currents are well balanced. The power ratings at primary and at
secondary are equal.
From the definitions presented in Section 2 and taking into account the symmetries given
by thepresence of p = 6 pulses in the period, we get

19
HVDC Transmission Systems (3160921) VGEC Chandkheda

The TUF is calculated from definition and is

TUF PDC
VSrms ISrms
0.955. (6)

Three-phase fully controlled bridge

Figure 3 is equivalent to Fig. 1: here thyristors have replaced diodes.

Fig. 3: Three-phase fully controlled bridge rectifier

20
HVDC Transmission Systems (3160921) VGEC Chandkheda

Similarly Fig. 16 shows the voltage waveforms with a delay angle = 45 degrees.

Fig. 4: Waveforms of a three-phase fully controlled bridge rectifier ( = 45 deg)

The delay angle or firing angle, indicated as , is defined as that angle in electrical radians
or electrical degrees comprised between the instant at which the thyristor would naturally switch
on if it were a diode and the instant at which the trigger pulse is applied and the thyristor starts to
conduct (assuming ideal devices with instantaneous turning on/off). In a bridge structure, two
switches are conducting at the same time, i.e., two trigger pulses must be applied simultaneously
to the couples of thyristors that must conduct.
In order to calculate the rectified voltage as a function of the delay angle , starting
fromdefinition (1) and considering the symmetries, one should consider the two cases:
Equation is valid when the condition of continuous conduction (i.e., the instantaneous voltage at
the DC terminals is at all times positive) is satisfied. For delay angles beyond 60 degrees the
instantaneous voltage at the DC terminals goes to zero (negative if the load has an inductive

Fig. 5: Waveforms of a three-phase fully controlled bridge rectifier at different values of 

21
HVDC Transmission Systems (3160921) VGEC Chandkheda

component, as will be seen later) for a while and the current does not flow continuously anymore.
Figure 17 shows the load voltage waveforms at four different values of .
Fig. 5: Waveforms of a three-phase fully controlled bridge rectifier at different values of 

All performance parameters defined in Section 2 can be recalculated as function of  and

there are different equations depending on the type of conduction.

22
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No-03
Title: Study of 12-Pulse HVDC Transmission System
AIM: Study of 12-Pulse HVDC Transmission System

Introduction

HVDC converters are usually built as 12-pulse circuits. This is a serial connection of two
fully controlled 6-pulse converter bridges and requires two 3-phase systems which are spaced apart
from each other by 30 electrical degrees. The phase difference effected to cancel out the 6-pulse
harmonics on the AC and DC side.

Twelve-pulse Bridge

With a phase change only every 60°, considerable harmonic distortion is produced at both
the DC and AC terminals when the six-pulse arrangement is used. An enhancement of the six-pulse
bridge arrangement uses 12 valves in a twelve-pulse bridge.[11] A twelve-pulse bridge is
effectively two six-pulse bridges connected in series on the DC side and arranged with a phase
displacement between their respective AC supplies so that some of the harmonic voltages and
currents are cancelled.
The phase displacement between the two AC supplies is usually 30° and is realised by using
converter transformers with two different secondary windings (or valve windings). Usually one of
the valve windings is star (wye)-connected and the other is delta-connected.[16] With twelve valves
connecting each of the two sets of three phases to the two DC rails, there is a phase change every
30°, and harmonics are considerably reduced. For this reason the twelve pulse system has become
standard on almost all line-commutated converter HVDC systems, although HVDC systems built
with mercury arc valves usually allowed for temporary operation with one of the two six-pulse
groups bypassed.

23
HVDC Transmission Systems (3160921) VGEC Chandkheda

Fig: 12 Pulse Bridge Configuration

24
HVDC Transmission Systems (3160921) VGEC Chandkheda

25
HVDC Transmission Systems (3160921) VGEC Chandkheda

26
HVDC Transmission Systems (3160921) VGEC Chandkheda

Model Description

A 1000 MW (500 kV, 2kA) DC interconnection is used to transmit power from a 500 kV,
5000 MVA, 60 Hz network to a 345 kV, 10 000 MVA, 50 Hz network.

The rectifier and the inverter are 12-pulse converters using two 6-pulse thyristor bridges
connected in series. The rectifier and the inverter are interconnected through a 300 km distributed
parameter line and two 0.5 H smoothing reactors. The transformer tap changers are not simulated
and fixed taps are assumed. Open the two transformer blocks in the Rectifier and Inverter
subsystems to see the factors applied on the primary voltage: 0.90 on rectifier side and 0.96 on
inverter side. Reactive power required by the converters is provided by a set of capacitor banks plus
11th, 13th and high pass filters for a total of 600 Mvar on each side. Two circuit breakers are used
to apply faults on the inverter AC side and rectifier DC side.

The rectifier and inverter control systems use the Discrete 12-pulse HVDC Control block
of the Extras/Discrete Control Blocks library. DC Protection functions are implemented in each
converter. At the rectifier the DC fault protection will detect and force the delay angle into the
inverter region so to extinguish the fault current. At the inverter the commutation failure prevention
control will detect AC faults and reduce the maximum delay angle limit in order to decrease the
risk of commutation failure. The Low AC voltage detection blocks will lock the DC fault protection
when a drop in the AC voltage is detected. The Master Control block initiates the starting and
stopping of the converters as well as the ramping up and down of the current references. The power
system and the control system are both discretized for a sample time Ts=50 us. Notice that the
"Model initialization" function of the model automatically sets Ts = 50e-6 in your Matlab
workspace. A description of the control systems is provided in the HVDC Transmission System
Case Study of the User's Manual.

Demonstration

The system is programmed to start and reach a steady state. Then steps are applied on the
reference current of the rectifier and on the inverter reference voltage in order to observe the
dynamic response of the regulators. Finally, a stop sequence is initiated to bring the DC power
down before blocking the converters. Start the simulation. Open the RECTIFIER and INVERTER
scopes (in the Data Acquisition subsystem) and observe the DC line voltage on trace
1 (1pu = 500 kV) and the DC line current (reference and measured values) on trace 2 (1pu =
2kA).

Start-up and Stop

27
HVDC Transmission Systems (3160921) VGEC Chandkheda

In the Master Control, the converters are deblocked and started by ramping the rectifier and
inverter reference current. At t = 0.02 s (i.e. when the converters at deblocked), the reference current
is ramped to reach the minimum value of 0.1 pu in 0.3 s (0.33 pu/s). At the end of this first ramp (t =
0.32 s) the DC line is charged at its nominal voltage and DC voltage reaches steady-state. At t= 0.4
s, the reference current is ramped from 0.1 pu to 1 pu (2kA) in 0.18 s (5 pu/s). At the end of this
starting sequence (t=0.58 s) , the DC current reaches steady state. The RECTIFIER then controls the
current and the INVERTER controls the voltage. In steady-state, the alpha firing angles (trace 3) are
16.5 degrees and 143 degrees respectively on the RECTIFIER and INVERTER sides. The exctinction
angle gamma (minimum value) is measured at the INVERTER and shown in trace 4. In steady-state,
the minimum value is between 22 and 24 degrees. The control mode of operation (an integer between
0 to 6) is shown in trace 4 (0= blocked; 1=Current control; 2=Voltage control; 3=Alpha minimum
limitation; 4=Alpha maximum limitation; 5=Forced or constant alpha; 6=Gamma control). At t = 1.4
s the Stop sequence is initiated by ramping down the current to 0.1 pu. At t = 1.6 s a Forced-alpha at
the Rectifier extinguishes the current and at the Inverter the Forced-alpha brings down the DC
voltage. At t =
1.7 s the pulses are blocked in both converters.

Step response of current and voltage regulators

Verify in the Master Control that the "Enable Ref. Current Step" switch is in the upper
position. This switch is used to apply a step on the reference voltage. Also verify that the reference
voltage step is enabled in the Inverter Control. At t=0.7 s, a -0.2 pu step is first applied on the
reference current (decrease from 1 pu to 0.8 pu ) and at t=0.8 s, the reference current is reset to its
1 pu original value.The current stabilizes in approximately 0.1 seconds. Steps are also applied on
the reference voltage of the inverter (-0.1 pu / +0.1 pu at t=1.0 s /
1.1s).

DC line fault at the rectifier

Deactivate the steps applied on the current reference and on the voltage reference in the
Master Control and in the inverter control respectively by setting the switches in lower position. In
the DC Fault block, change to 1 the 100 multiplication factor in the Switching times so that a fault
is now applied at t = 0.7 s. Reduce the Simulation stop time from 2 to 1.4 s. The DC Fault protection
(DCPROT) in the rectifier is activated by default. Open the FAULT scope to observe the DC fault
current. Restart the simulation.

28
HVDC Transmission Systems (3160921) VGEC Chandkheda

At fault application the DC current quickly increases to 2.3 pu and the DC voltage falls to zero
at the rectifier. This DC voltages drop is seen by the Voltage Dependent Current Order
Limiter (VDCOL) which reduces the reference current to 0.3 pu at the rectifier. A DC current still
continues to circulate in the fault. Then, at t = 0.77 s, the rectifier alpha firing angle is forced to 166
degrees by the DC protection because a DC voltage drop is detected (VdL< 0.5 pu for more than 70
ms). The rectifier now operates in inverter mode. The DC line voltage becomes negative and the
energy stored in the line is returned to the AC network, causing rapid extinction of the fault current
at its next zero-crossing. Then, alpha is released at t = 0.87 s and the normal DC voltage and current
recover in approximately 0.4 s

AC line-to-ground fault at the inverter

In the DC Fault block, change the multiplication factor of 1 in the Switching times to 100,
so that the DC fault is now eliminated. In the A-G Fault block, change to 1 the 100 multiplication
factor in the Switching times so that a 6 cycles line-to-ground fault is now applied at t = 0.7 s. The
Low AC voltage detection (LACVD) subsystem in the rectifier and inverter protections and the
Commutation Failure Prevention Control (CFPREV) in the inverter protection are activated by
default. Restart the simulation.

Notice the 120 Hz oscillations in the DC voltage and currents during the fault. When the
fault is cleared at t = 0.8 s, the VDCOL operates and reduces the reference current to 0.3 pu. The
system recovers in approximately 0.35 s after fault clearing. The LACVD detects the fault and locks
the DC Fault protection that should not detect a DC fault even if the DC line voltage dips. Look at
the CFPREV output (A_min_I) which decreases the maximum delay angle limit in order to increase
the commutation margin during and after the fault. Now deactivate the CFPREV protection by
deselecting the "ON State" in the CFPREV dilaog box. Restart the simulation and observe the
difference in recovery time of the DC transmission. Note that a commutation failure now occurs
during the recovery. A commutation failure is the result of a failure of the incoming valve to take
over the direct current before the commutation voltage reverses its polarity. The symptoms are a
zero DC voltage across the affected bridge causing an increase of the DC current at a rate
determined mainly by the DC circuit inductance.

29
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No-04
Various FACTS Controllers models

AIM: Study of various FACTS Controllers models

Introduction
The increasing Industrialization, urbanization of life style has lead to increasing dependency on
the electrical energy. This has resulted into rapid growth of PSs. This rapid growth has resulted into
few uncertainties. Power disruptions and individual power outages are one of the major problems
and affect the economy of any country. In contrast to the rapid changes in technologies and the
power required by these technologies, transmission systems are being pushed to operate closer to
their stability limits and at the same time reaching their thermal limits due to the fact that the
delivery of power have been increasing. The major problems faced by power industries in
establishing the match between supply and demand are:
 Transmission & Distribution; supply the electric demand without exceeding the thermal
limit.
 In large PS, stability problems causing power disruptions and blackouts leading to huge
losses.
These constraints affect the quality of power delivered. However, these constraints can be
suppressed by enhancing the PS control. One of the best methods for reducing these constraints is
FACTS devices. With the rapid development of power electronics, FACTS devices have been
proposed and implemented in PSs. FACTS devices can be utilized to control power flow and
enhance system stability. Particularly with the deregulation of the electricity market, there is an
increasing interest in using FACTS devices in the operation and control of PSs. A better utilization
of the existing PSs to increase their capacities and controllability by installing FACTS devices
becomes imperative. FACTS devices are cost effective alternatives to new transmission line
construction. Due to the present situation, there are two main aspects that should be considered in
using FACTS devices: The first aspect is the flexible power system operation according to the
power flow control capability of FACTS devices. The other aspect is the improvement of transient
and SSVS of PSs. FACTS devices are the right equipment to meet these challenges.

Definition of FACTS

According to IEEE, FACTS, which is the abbreviation of Flexible AC Transmission

Systems, is defined as follows: “Alternating current transmission systems incorporating power
electronics based and other static controllers to enhance controllability and APTC”.

30
HVDC Transmission Systems (3160921) VGEC Chandkheda

Since the ʺother static controllersʺ based FACTS devices are not widely used in current PSs,
the focused only on the power electronics based FACTS devices. The FACTS controllers are
classified as follows:

 Thyristor controlled based FACTS controllers such as TSC, TCR, FC‐TCR, SVC, TCSC, TC‐
PAR etc.
 VSI based FACTS controllers such as SSSC, STATCOM, UPFC, GUPFC, IPFC, GIPFC,
HPFC etc.

The main drawback of thyristor controlled based FACTS controllers is the resonance phenomena
occurs but VSI based FACTS controllers are free from this phenomena. So that the overall
performance of VSI based FACTS controllers are better than of that the thyristor controlled based
FACTS controllers.

Nomenclatures

HVDC High Voltage Direct Current PSS Power System Stabilizers

AP Active Power RP Reactive Power
VSC Voltage Source Converter VSI Voltage Source Inverter
VS Voltage Stability VI Voltage Instability
VC Voltage Collapse VP Voltage Profile
VR Voltage Regulation SSVS Steady State Voltage Stability
TS Transient Stability APTC Available Power Transfer Capacity
PQ Power Quality SSR Sub‐synchronous Resonance
OPF Optimal Power Flow NRFL Newton Raphson Load Flow
FL Fuzzy Logic NN Neural Network
GA Genetic Algorithm PSO Particle Swarm Optimization
POD Power Oscillation Damping DGs Distributed Generations
SS Steady State FCL Fault Current Limiting
WP Wind Power RESs Renewable Energy Sources
PMUs Phasor Measurement Units

31
HVDC Transmission Systems (3160921) VGEC Chandkheda

FACTS Categories and Their Functions

A. FACTS Categories:

In general, FACTS devices can be divided into four categories on basis of their connection diagram
in PSS mentioned in table 1:

1) Series Connected ‐FACTS Devices:

Series FACTS devices could be variable impedance, such as capacitor, reactor, etc., or
power electronics based variable source of main frequency, sub synchronous and harmonic
frequencies (or a combination) to serve the desired need. In principle, all series FACTS
devices inject voltage in series with the transmission line.

2) Shunt Connected ‐FACTS Devices:

Shunt FACTS devices may be variable impedance, variable source, or a combination of these.
They inject current into the system at the point of connection.

3) Combined Series‐series Connected ‐FACTS Device:

Combined series‐series FACTS device is a combination of separate series FACTS devices,
which are controlled in a coordinated manner.

4) Combined Series‐shunt Connected ‐FACTS Device:

Combined series‐shunt FACTS device is a combination of separate shunt and series
devices, which are controlled in a coordinated manner or one device with series and shunt
elements.
TABLE 1 BASIC TYPE OF FACTS CONTROLLERS
Sr.
Symbol Description
No.

01 General symbol for FACTS controller.

32
HVDC Transmission Systems (3160921) VGEC Chandkheda

 Known as series FACTS controller such

as TCSC.
 The controllers inject voltage in
02 quadrature with the line current
 The controllers supply /absorb variable
RP
 Known as shunt FACTS controller such
as SVC, STATCOM.
 The controllers inject capacitive or
03 inductive current in quadrature with the
line voltage
 The controllers supply/absorb variable
RP
 Known as combined
series‐series
FACTS controller such as IPFC
 It is a combination of separate series
04 controllers
 Provide independent series RP
compensation for each line
 Transfer AP among the lines via the dc
power link
 Known as combined series‐shunt
controller such as UPFC etc.
 It is a combination of separate series and
shunt controllers
05
 Provide series and shunt RP
compensation Transfer AP between
the series and shunt controllers via the dc
power link

B. Control Attributes for Various FACTS Controllers

The Control Attributes for Various FACTS Controllers are shown in Table 1.2.

33
HVDC Transmission Systems (3160921) VGEC Chandkheda

TABLE 2 CONTROL ATTRIBUTES FOR VARIOUS FACTS CONTROLLERS

No. FACTS Controller Control Attributes for Various FACTS Controllers
01 SVC, TCR, TCS, TRS Voltage control, VAR compensation, POD, VS, TS and DS
02 TCSC, TSSC Current control, POD, VS, TS and DS, FCL
03 TCSR, TSSR Current control, POD, VS, TS and DS, FCL
04 TC‐PST or TC‐PAR AP control, POD, VS, TS and DS
05 TCBR POD, TS and DS
06 TCVL Transient and dynamic voltage limit
07 TCVR RP control, voltage control, POD, VS, TS and DS
08 SSSC without storage Current control, POD, VS, TS and DS, FCL
09 SSSC with storage Current control, POD, VS, TS and DS
10 STATCOM without storage Voltage control, VAR compensation, POD, VS
STATCOM with storage, Voltage control, VAR compensation, POD, VS, TS and
11 BESS, SMES, large dc DS,
AGC
AP and RP control, voltage control, VAR compensation,
12 UPFC
POD, VS, TS and DS, FCL
13 IPFC RP control, voltage control, POD, VS, TS and DS

14 HPFC RP control, voltage control, POD, VS, TS and DS, FCL

Within the basic system security guidelines, the FACTS devices enable the transmission
system to obtain one or more of the following benefits:
• Control of power flow as ordered. This is the main function of FACTS devices. The use
of power flow control may be to follow a contract, meet the utilities’ own needs, ensure
optimum power flow, ride through emergency conditions, or a combination of them.
• Increase utilization of lowest cost generation. One of the principal reasons for
transmission interconnections is to utilize the lowest cost generation. When this cannot be
done, it follows that there is not enough cost‐effective transmission capacity. Cost‐

34
HVDC Transmission Systems (3160921) VGEC Chandkheda

effective enhancement of capacity will therefore allow increased use of lowest cost
generation.
• DS enhancement. This FACTS additional function includes the TS improvement, POD
and VS control.
• Increase the loading capability of lines to their thermal capabilities, including short term
and seasonal demands.
• Increased system reliability.
• Elimination or deferral of the need for new transmission lines.
• Added flexibility in siting new generation
• Provide secure tie‐line connections to neighbouring utilities and regions thereby
decreasing overall generation reserve requirements on both sides.
• Upgrade of transmission lines.
• Increased system security.
• Reduce RP flows, thus allowing the lines to carry more AP.
• Loop flow control.

TABLE 3 APPLICATIONS OF FACTS DEVICES

Conventional Equipment
Issues New Problem Corrective Action
Solution (FACTS)
Low voltage at Shunt capacitor, TCSC,
heavy load Supply RP
Series capacitor STATCOM
Switch EHV line
Remove RP
and/or shunt capacitor TCSC, TCR
supply
Voltage High voltage at
Limits light load Switch shunt
Absorb RP capacitor, shunt TCR, STATCOM
reactor, SVC

Absorb RP Add reactor TCR

35
HVDC Transmission Systems (3160921) VGEC Chandkheda

High voltage Protect equipment

Add arrestor TCVL
following outage
Switch, shunt
capacitor, reactor, STATCOM ,
Supply RP limit
Low voltage SVC, switch series TCSC
following outage capacitor
IPC, TCPAR,
Prevent over load Series reactor, PAR
TCSC
Low voltage and Supply RP and Combination of two or IPC, TCSC,
overload limit over load more equipment UPFC,
STATCOM
TCSC, TCPAR,
Add line/transformer
Line/transformer UPFC
Reduce overload
Thermal overload
Add series reactor TCR, IPC
Limits
Tripping of Limit circuit
- IPC,TCR, UPFC
parallel circuit loading
Add series reactor,
Limit short‐ fuses, new circuit
TCR, IPC, UPFC
circuit current
breaker
Excessive
Short circuit
breaker fault Change circuit Add new circuit
levels -
current breaker breaker
Rearrange
Split bus IPC
network

FACTS Controllers

The development of FACTS controllers has followed two distinctly different technical approaches,
both resulting in a comprehensive group of controllers able to address targeted transmission
problems. The first group employs reactive impedances or a tap-changing transformer with
thyristor switches as controlled elements; the second group uses selfcommutated static converters
as controlled voltage sources.

36
HVDC Transmission Systems (3160921) VGEC Chandkheda

A. Conventional Thyristor-based FACTS Controllers

37
HVDC Transmission Systems (3160921) VGEC Chandkheda

B. Switching Converter Based FACTS Controller

Conclusion: By studying this experiment, we understand the FACTS Controllers models and its
types.

38
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No-05
Static VAR Compensator (SVC) in Power System
AIM: Application Study of Static VAR Compensator (SVC) in Power System

Objective of SVC:
1. Increase power transfer in long lines.
2. Improve stability with fast acting voltage regulation.
3. Damp low frequency oscillations due to swing (rotor) modes.
4. Damp sub-synchronous frequency oscillations due to torsional modes.
5. Control dynamic overvoltages.

A SVC has no inertia compared to synchronous condensers and can be

extremely fast in response (2-3 cycles). This enables the fast control of reactive
power in the control range.

39
HVDC Transmission Systems (3160921) VGEC Chandkheda

40
HVDC Transmission Systems (3160921) VGEC Chandkheda

41
HVDC Transmission Systems (3160921) VGEC Chandkheda

Case

study: Steady-state and Dynamic Performance of the Static Var Compensator (SVC)

42
HVDC Transmission Systems (3160921) VGEC Chandkheda

Description

A static var compensator (SVC) is used to regulate voltage on a 500 kV, 3000 MVA system.
When system voltage is low the SVC generates reactive power (SVC capacitive). When system
voltage is high it absorbs reactive power (SVC inductive). The SVC is rated +200 Mvar capacitive
and 100 Mvar inductive. The Static Var Compensator block is a phasor model representing the
SVC static and dynamic characteristics at the system fundamental frequency.

To see the SVC control parameters, open the SVC dialog box and select "Display Control
parameters". The SVC is set in voltage regulation mode with a reference voltage Vref=1.0 pu. The
voltage droop is 0.03 pu/ 200MVA, so that the voltage varies from 0.97 pu to 1.015 pu when the
SVC current goes from fully capacitive to fully inductive. Double click now on the blue block to
display the SVC V-I characteristic.

The actual SVC positive-sequence voltage (V1) and susceptance (B1) are measured inside
the 'Signal Processing' subsystem, using the complex voltages Vabc and complex currents Iabc
returned by the Three-Phase V-I Measurement block.

1. Dynamic Response of the SVC

The Three-Phase Programmable Voltage Source is used to vary the system voltage and
observe the SVC performance. Initially the source is generating nominal voltage. Then, voltage is
successively decreased (0.97 pu at t = 0.1 s), increased (1.03 pu at t = 0.4 s) and finally returned to
nominal voltage (1 pu at t = 0.7 s).

Start the simulation and observe the SVC dynamic response to voltage steps on the Scope.
Trace 1 shows the actual positive-sequence susceptance B1 and control signal output B of the
voltage regulator. Trace 2 shows the actual system positive-sequence voltage V1 and output Vm of
the SVC measurement system.

The SVC response speed depends on the voltage regulator integral gain Ki (Proportional
gain Kp is set to zero), system strength (reactance Xn) and droop (reactance Xs). If the voltage
measurement time constant and average time delay Td due to valve firing are neglected, the system
can be approximated by a first order system having a closed loop time constant:

Tc= 1/(Ki*(Xn+Xs))

43
HVDC Transmission Systems (3160921) VGEC Chandkheda

With given system parameters (Ki = 300; Xn = 0.0667 pu/200 MVA; Xs = 0.03 pu/200
MVA), Tc = 0.0345 s. If you increase the regulator gain or decrease the system strength, the
measurement time constant and the valve firing delay Td will no longer be negligible and you will
observe an oscillatory response and eventually unstability.

2. Measurement of Steady-State V-I Characteristic

In order to measure the SVC steady-state V-I characteristic, you will now program a slow
variation of the source voltage. Open the Programmable Voltage Source menu and change the
"Type of Variation" parameter to "Modulation". The modulation parameters are set to apply a
sinusoidal variation of the positive-sequence voltage between 0.75 and 1.25 pu in 20 seconds. In
the Simulation->Configuration Parameters menu change the stop time to 20 s and restart simulation.
When simulation is completed, double click the blue block. The theoretical V-I characteristic is
displayed (in red) together with the measured characteristic (in blue).

Conclusion: By studying this experiment, we understand the Applications Study of Static VAR
Compensator (SVC) in Power System and learned how to plot graphs related to it.

44
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No-06
Thyristor-Controlled Series Capacitor (TCSC) in Power System

AIM: Application Study of Thyristor-Controlled Series Capacitor (TCSC) in Power System

45
HVDC Transmission Systems (3160921) VGEC Chandkheda

The major control functions in a TCSC are,

• Power Scheduling Control
• Power Swing Damping Control (PSDC)
• Transient Stability Control (TSC)

46
HVDC Transmission Systems (3160921) VGEC Chandkheda

• Sub-synchronous Damping Control (SSDC)

Modes of TCSC Operation

There are essentially three modes of TCSC operation

1. Bypassed-thyristor mode

In this bypassed mode, the thyristors are made to fully conduct with a conduction angle of
0
180 . Gate pulses are applied as soon as the voltage across the thyristors reaches zero and becomes
positive, resulting in a continuous sinusoidal of flow current through the thyristor valves. The TCSC
module behaves like a parallel capacitor–inductor combination. However, the net current through
the module is inductive, for the susceptance of the reactor is chosen to be greater than that of the
capacitor.
Also known as the TSR mode, the
bypassed thyristor mode is distinct from the
bypassed-breaker mode, in which the
circuit breaker provided across the series
capacitor is closed to
remove the capacitor or the
TCSC module in the event of TCSC faults
or transient over voltages across the TCSC.
Also known as the TSR mode, the bypassed thyristor mode is distinct from the
bypassedbreaker mode, in which the circuit breaker provided across the series capacitor is closed
to remove the capacitor or the TCSC module in the event of TCSC faults or transient over voltages
across the TCSC.
This mode is employed for control purposes and also for initiating certain protective
functions. Whenever a TCSC module is bypassed from the violation of the current limit, a finitetime
delay, Tdelay, must elapse before the module can be reinserted after the line current falls below the
specified limit.

47
HVDC Transmission Systems (3160921) VGEC Chandkheda

2. Blocked-thyristor mode

In this mode, also known as the waiting mode, the firing pulses to the thyristor valves are
blocked. If the thyristors are conducting and a blocking command is given, the thyristors turn off
as soon as the current through them reaches a zero crossing. The TCSC module is thus reduced to
a fixed-series capacitor, and the net TCSC
reactance is capacitive. In this mode, the
dc-offset voltages of the capacitors are
monitored and quickly discharged using a
dc-offset control without causing any
harm to the transmission-system
transformers.
3. Partially Conducting Thyristor
or Vernier Mode
This mode allows the TCSC to behave either as a continuously controllable capacitive reactance
or as a continuously controllable inductive reactance. It is achieved by varying the thyristor-pair
firing angle in an appropriate range. However, a smooth transition from the capacitive to inductive
mode is not permitted because of the resonant region between the two modes.

A variant of this mode is the capacitive-vernier-control mode, in which the thyristors are fired
when the capacitor voltage and capacitor current have opposite polarity. This condition causes a
TCR current that has a direction opposite that of the capacitor current, thereby resulting in a loop
current flow in the TCSC controller. The loop current increases the voltage across the FC,
effectively enhancing the equivalent-capacitive reactance and the seriescompensation level for the
same value of line current. To preclude resonance, the firing angle of the forward-facing
thyristor, as measured from the positive reaching a zero crossing of the capacitor voltage, is
constrained in the range αmin ≤ α ≤ 1800. This constraint provides a continuous vernier control of
the TCSC module reactance. The loop current increases as is decreased from 1800 to αmin. The
maximum TCSC reactance permissible with α = αmin is typically two-and-a-half to three times the
capacitor reactance at fundamental frequency.

48
HVDC Transmission Systems (3160921) VGEC Chandkheda

Another variant is the inductive-vernier mode, in which the TCSC can be operated by having a
high level of thyristor conduction. In this mode, the direction of the circulating current is reversed
and the controller presents net inductive impedance.

Case Study: Thyristor-Controlled Series Capacitor (TCSC) in Power System

Circuit Description

A TCSC is placed on a 500kV, long transmission line, to improve power transfer. Without
the TCSC the power transfer is around 110MW, as seen during the first 0.5s of the simulation when
the TCSC is bypassed. The TCSC consists of a fixed capacitor and a parallel Thyristor Controlled
Reactor (TCR) in each phase. The nominal compensation is 75%, i.e. using only the capacitors
(firing angle of 90deg). The natural oscillatory frequency of the TCSC is 163Hz, which is 2.7 times
the fundamental frequency. The test system is described in [1].

The TCSC can operate in capacitive or inductive mode, although the latter is rarely used in
practice. Since the resonance for this TCSC is around 58deg firing angle, the operation is prohibited
in firing angle range 49deg - 69deg. Note that the resonance for the overall system (when the line
impedance is included) is around 67deg. The capacitive mode is achieved with firing angles 69-
90deg. The impedance is lowest at 90deg, and therefore power transfer increases as the firing angle
is reduced. In capacitive mode the range for impedance values is approximately 120-136 Ohm. This
range corresponds to approximately 490-830MW power transfer range (100%-110%
compensation). Comparing with the power transfer of 110 MW with an uncompensated line, TCSC
enables significant improvement in power transfer level.

To change the operating mode (inductive/capacitive/manual) use the toggle switch in the
control block dialog. The inductive mode corresponds to the firing angles 0-49deg, and the lowest
impedance is at 0deg. In the inductive operating mode, the range of impedances is 1960 Ohm,

49
HVDC Transmission Systems (3160921) VGEC Chandkheda

which corresponds to 100-85 MW range of power transfer level. The inductive mode reduces power
transfer over the line. A constant firing angle can also be applied and the same limits will apply as
above.

TCSC Control

When TCSC operates in the constant impedance mode it uses voltage and current feedback
for calculating the TCSC impedance. The reference impedance indirectly determines the power
level, although an automatic power control mode could also be introduced.

A separate PI controller is used in each operating mode. The capacitive mode also employs
a phase lead compensator. Each controller further includes an adaptive control loop to improve
performance over a wide operating range. The controller gain scheduling compensates for the gain
changes in the system, caused by the variations in the impedance.
The firing circuit uses three single-phase PLL units for synchronisation with the line current.
Line current is used for synchronisation, rather than line voltage, since the TCSC voltage can vary
widely during the operation

Demonstration

Run the simulation and observe waveforms on the main variables scope block. The TCSC
is in the capacitive impedance control mode and the reference impedance is set to 128 Ohm. For
the first 0.5s, the TCSC is bypassed using the circuit breaker, and the power transfer is 110 MW.
At 0.5s TCSC begins to regulate the impedance to 128 Ohm and this increases power transfer to
610MW. Note that the TCSC starts with alpha at 90deg to enable lowest switching disturbance on
the line.

Dynamic Response

At 2.5s a 5% change in the reference impedance is applied. The response indicates that
TCSC enables tracking of the reference impedance and the settling time is around 500ms. At 3.3s
a 4% reduction in the source voltage is applied, followed by the return to 1p.u. at 3.8s. It is seen
that the TCSC controller compensates for these disturbances and the TCSC impedance stays
constant. The TCSC response time is 200ms-300ms.

50
HVDC Transmission Systems (3160921) VGEC Chandkheda

Conclusion: By studying this practical we understand the Applications of Thyristor-Controlled Series

Capacitor (TCSC) in Power System and learned how to plot graphs related to it.

51
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No-07
Distribution Static Synchronous Compensator (DSTATCOM) in
Power System

AIM: Application Study of Distribution Static Synchronous Compensator (DSTATCOM) in Power

System

52
HVDC Transmission Systems (3160921) VGEC Chandkheda

53
HVDC Transmission Systems (3160921) VGEC Chandkheda

54
HVDC Transmission Systems (3160921) VGEC Chandkheda

55
HVDC Transmission Systems (3160921) VGEC Chandkheda

56
HVDC Transmission Systems (3160921) VGEC Chandkheda

Case Study: Simulation Model of a Distribution STATCOM)

The model includes detailed representation of power electronic IGBT converters. In order to
achieve an acceptable accuracy with the 1680 Hz switching frequency used in this demo, the model
must be discretized at a relatively small time step (5 microseconds). This model is well suited for
observing harmonics and control system dynamic performance over relatively short periods of
times (typically hundreds of milliseconds to one second).

Model Description

A Distribution Static Synchronous Compensator (D-STATCOM) is used to regulate voltage

on a 25-kV distribution network. Two feeders (21 km and 2 km) transmit power to loads connected
at buses B2 and B3. A shunt capacitor is used for power factor correction at bus B2. The 600-V
load connected to bus B3 through a 25kV/600V transformer represents a plant absorbing
continuously changing currents, similar to an arc furnace, thus producing voltage flicker. The
variable load current magnitude is modulated at a frequency of 5 Hz so that its apparent power
varies approximately between 1 MVA and 5.2 MVA, while keeping a 0.9 lagging power factor.
This load variation will allow you to observe the ability of the D-STATCOM to mitigate voltage
flicker.

The D-STATCOM regulates bus B3 voltage by absorbing or generating reactive power.

This reactive power transfer is done through the leakage reactance of the coupling transformer by
generating a secondary voltage in phase with the primary voltage (network side). This voltage is
provided by a voltage-sourced PWM inverter. When the secondary voltage is lower than the bus
voltage, the D-STATCOM acts like an inductance absorbing reactive power. When the secondary
voltage is higher than the bus voltage, the D-STATCOM acts like a capacitor generating reactive
power.

The D-STATCOM consists of the following components:

• A 25kV/1.25kV coupling transformer which ensures coupling between the PWM inverter and
the network.
• A voltage-sourced PWM inverter consisting of two IGBT bridges. This twin inverter
configuration produces less harmonics than a single bridge, resulting in smaller filters and
improved dynamic response. In this case, the inverter modulation frequency is 28*60=1.68
kHz so that the first harmonics will be around 3.36 kHz.

57
HVDC Transmission Systems (3160921) VGEC Chandkheda

• LC damped filters connected at the inverter output. Resistances connected in series with
capacitors provide a quality factor of 40 at 60 Hz.
• A 10000-microfarad capacitor acting as a DC voltage source for the inverter
• A voltage regulator that controls voltage at bus B3
• A PWM pulse generator using a modulation frequency of 1.68 kHz Anti-aliasing filters
used for voltage and current acquisition.

The D-STATCOM controller consists of several functional blocks:

• A Phase Locked Loop (PLL). The PLL is synchronized to the fundamental of the transformer
primary voltages.
• Two measurement systems. Vmeas and Imeas blocks compute the d-axis and q-axis
components of the voltages and currents by executing an abc-dq transformation in the
synchronous reference determined by sin(wt) and cos(wt) provided by the PLL.
• An inner current regulation loop. This loop consists of two proportional-integral (PI)
controllers that control the d-axis and q-axis currents. The controllers outputs are the Vd and
Vq voltages that the PWM inverter has to generate. The Vd and Vq voltages are converted
into phase voltages Va, Vb, Vc which are used to synthesize the PWM voltages. The Iq
reference comes from the outer voltage regulation loop (in automatic mode) or from a
reference imposed by Qref (in manual mode). The Id reference comes from the DC-link
voltage regulator.
• An outer voltage regulation loop. In automatic mode (regulated voltage),
• A PI controller maintains the primary voltage equal to the reference value defined in the
control system dialog box. a DC voltage controller which keeps the DC link voltage constant
to its nominal value (Vdc=2.4 kV).

The electrical circuit is discretized using a sample time Ts=5 microseconds. The controller uses
a larger sample time (32*Ts= 160 microseconds).

58
HVDC Transmission Systems (3160921) VGEC Chandkheda

Demonstration

1. D-STATCOM dynamic response

During this test, the variable load will be kept constant and you will observe the dynamic
response of a D-STATCOM to step changes in source voltage. Check that the modulation of the
Variable Load is not in service (Modulation Timing [Ton Toff]= [0.15 1]*100 > Simulation Stop
time). The Programmable Voltage Source block is used to modulate the internal voltage of the 25-
kV equivalent. The voltage is first programmed at 1.077 pu in order to keep the D-STATCOM
initially floating (B3 voltage=1 pu and reference voltage Vref=1 pu). Three steps are programmed
at 0.2 s, 0.3 s, and 0.4 s to successively increase the source voltage by 6%, decrease it by 6% and
bring it back to its initial value (1.077 pu).

Start the simulation. Observe on Scope1 the phase A voltage and current waveforms of the D-
STATCOM as well as controller signals on Scope2. After a transient lasting approximately 0.15
sec., the steady state is reached. Initially, the source voltage is such that the D-STATCOM is
inactive. It does not absorb nor provide reactive power to the network. At t = 0.2 s, the source
voltage is increased by 6%. The D-STATCOM compensates for this voltage increase by absorbing
reactive power from the network (Q=+2.7 Mvar on trace 2 of Scope2). At t = 0.3 s, the source
voltage is decreased by 6% from the value corresponding to Q = 0. The D-STATCOM must
generate reactive power to maintain a 1 pu voltage (Q changes from +2.7 MVAR to -2.8 MVAR).
Note that when the D-STATCOM changes from inductive to capacitive operation, the modulation
index of the PWM inverter is increased from 0.56 to 0.9 (trace 4 of Scope2) which corresponds to
a proportional increase in inverter voltage. Reversing of reactive power is very fast, about one cycle,
as observed on D-STATCOM current (magenta signal on trace 1 of Scope1).

2. Mitigation of voltage flicker

During this test, voltage of the Programmable Voltage Source will be kept constant and you
will enable modulation of the Variable Load so that you can observe how the D-STATCOM can
mitigate voltage flicker. In the Programmable Voltage Source block menu, change the "Time
Variation of" parameter to "None". In the Variable Load block menu, set the Modulation Timing
parameter to [Ton Toff]= [0.15 1] (remove the 100 multiplication factor). Finally, in the
DSTATCOM Controller, change the "Mode of operation" parameter to "Q regulation” and make
sure that the reactive power reference value Qref (2nd line of parameters) is set to zero. In this
mode, the D-STATCOM is floating and performs no voltage correction.

59
HVDC Transmission Systems (3160921) VGEC Chandkheda

Run the simulation and observe on Scope3 variations of P and Q at bus B3 (1st trace) as well
as voltages at buses B1 and B3 (trace 2). Without D-STATCOM, B3 voltage varies between 0.96
pu and 1.04 pu (+/- 4% variation). Now, in the D-STATCOM Controller, change the "Mode of
operation" parameter back to "Voltage regulation" and restart simulation. Observe on Scope 3 that
voltage fluctuation at bus B3 is now reduced to +/- 0.7 %. The D-STATCOM compensates voltage
by injecting a reactive current modulated at 5 Hz (trace 3 of Scope3) and varying between 0.6 pu
capacitive when voltage is low and 0.6 pu inductive when voltage is high.

Conclusion: By studying this practical we understand the Applications of Distribution Static

Synchronous Compensator (DSTATCOM) in Power System and learned about its demonstrations.

60
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No- 08
Power Flow control in a five bus system using UPFC

AIM: Study and simulation of Power Flow control in a five bus system using UPFC

Introduction

A unified power flow controller (or UPFC) is an electrical device for providing fast-acting
reactive power compensation on high-voltage electricity transmission networks. It uses a pair of
three-phase controllable bridges to produce current that is injected into a transmission line using a
series transformer. The controller can control active and reactive power flows in a transmission
line.

The UPFC uses solid state devices, which provide functional flexibility, generally not
attainable by conventional thyristor controlled systems. The UPFC is a combination of a static
synchronous compensator (STATCOM) and a static synchronous series compensator (SSSC)
coupled via a common DC voltage link.

The main advantage of the UPFC is to control the active and reactive power flows in the
transmission line. If there are any disturbances or faults in the source side, the UPFC will not work.
The UPFC operates only under balanced sine wave source. The controllable parameters of the
UPFC are reactance in the line, phase angle and voltage. The UPFC concept was described in 1995
by L. Gyugyi of Westinghouse. The UPFC allows a secondary but important function such as
stability control to suppress power system oscillations improving the transient stability of power
system.

The UPFC is an advanced power system device capable of providing simultaneous control of
voltage magnitude, active and reactive power flows in an adaptive fashion. It has

• Extended functionality
• Capability to control voltage, line impedance and phase angle in the power system network
• Enhanced power transfer capability
• Ability to decrease generation cost
• Ability to improve security and stability
• Applicability for power flow control, loop flow control

61
HVDC Transmission Systems (3160921) VGEC Chandkheda

VOLTAGE OURCE CONVERTERS USED IN UPFC:

STATCOM:

A static synchronous generator operated as a shunt –connected

static var compensator whose capacitive or inductive output
current can be controlled independent of the ac system voltage.
For the voltage-sourced converter, its ac output voltage is
controlled such that it is just right for the required reactive current
flow for any ac bus voltage dc capacitor voltage is automatically
adjusted as require serving as a voltage source for the converter.
STATCOM also designed to act as an active filter to absorb system
harmonics. Figures shows the schematic diagram of STATCOM.

SSSC:
A Static synchronous series generator operated without an
exeternal electric energy source as a series compensator whose
output voltage is in quadrature with and controlled independently
of the line current for the purpose of increasing or decreasing
overall reactive voltage drop across the line and thereby
controlling the transmitted electric power. The SSSC may include
transiently rated energy storage or energy absorbing devices to
enhance the dynamic behavior of the power system by additional
temporary real power compensation to increase or decrease
momentarily the overall real voltage drop across the line.

Basic principle of UPFC:

From the conceptual viewpoint, the UPFC is a generalized synchronous voltage source
(SVS), represented at the fundamental (power system) frequency by voltage phasor Vpq with
controllable magnitude Vpq (0 S Vpq S Vpqmax) and angle p (0 -s p S21T), in series with the

62
HVDC Transmission Systems (3160921) VGEC Chandkheda

transmission line, as illustrated for the usual elementary two machine system (or for two
independent systems with a transmission link intertie) in Figure. In this functionally unrestricted
operation, which clearly includes voltage and angle regulation, the SVS generally exchanges both
reactive and real power with the transmission system. Since, as established previously, an SVS is
able to generate only the reactive power exchanged, the real power must be supplied to it, or
absorbed from it, by a suitable power supply or sink. In the UPFC arrangement the real power
exchanged is provided by one of the end buses (e.g., the sending-end bus), as indicated in Figure.

63
HVDC Transmission Systems (3160921) VGEC Chandkheda

In the presently used practical implementation, the UPFC consists of two voltagesourced
converters, as illustrated in Figure. Theseback-to-back converters, labeled "Converter 1" and
"Converter 2" in the figure, are operated from a common de link provided by a de storage capacitor.
As indicated before, this arrangement functions as an ideal ac-to-ac power converter in which the
real power can freely flow in either direction between the ac terminals of the two converters, and
each converter can independently generate (or absorb) reactive power at its own ac output terminal.
Converter 2 provides the main function of the UPFC by injecting a voltage Vpq with controllable
magnitude Vpq and phase angle p in series with the line via an insertion transformer. This injected
voltage acts essentially as a synchronous ac voltage source. The transmission line current flows
through this voltage source resulting in reactive and real power exchange between it and the ac
system. The reactive power exchanged at the ac terminal (Le., at the terminal of the series insertion
transformer) is generated internally by the converter. The real power exchanged at the ac terminal
is converted into de power which appears at the de link as a positive or negative real power demand.
The basic function of Converter 1 is to supply or absorb the real power demanded by
Converter 2 at the common de link to support the real power exchange resulting from the series
voltage injection. This de link power demand of Converter 2 is converted back to ac by Converter
1 and coupled to the transmission line bus via a shuntconnected transformer. In addition to the real
power need of Converter 2, Converter 1 can also generate or absorb controllable reactive power, if
it is desired, and thereby provide independent shunt reactive compensation for the line. It is
important to note that whereas there is a closed direct path for the real power negotiated by the
action of series voltage injection through Converters 1 and 2 back to the line, the corresponding
64
HVDC Transmission Systems (3160921) VGEC Chandkheda

reactive power exchanged is supplied or absorbed locally by Converter 2 and therefore does not
have to be transmitted by the line. Thus, Converter 1 can be operated at a unity power factor or be
controlled to have a reactive power exchange with the line independent of the reactive power
exchanged by Converter 2. Obviously, there can be no reactive power flow through the UPFC de
link.

Conventional Transmission Control Capabilities

Viewing the operation of the Unified Power Flow Controller from the standpoint of
traditional power transmission based on reactive shunt compensation, series compensation, and
phase angle regulation, the UPFC can fulfill all these functions and thereby meet multiple control
objectives by adding the injected voltage VP9' with appropriate amplitude and phase angle, to the
(sending-end) terminal voltage Vs. Using phasor representation, the basic UPFC power flow
control functions are illustrated in Figure.

Voltage regulation with continuously variable in-phase/anti-phase voltage injection, is

shown in Figure (a) for voltage increments Vpq = ±dV (p = 0). This is functionally similar to that
obtainable with a transformer tap changer having infinitely small steps.
Series reactive compensation is shown in Figure (b) where Vpq = Vq is injected in
quadrature with the line current I. Functionally this is similar to series capacitive and inductive line
compensation attained by the SSSC: the injected series compensating voltage can be kept constant,
if desired, independent of line current variation, or can be varied in proportion with the line current
to imitate the compensation obtained with a series capacitor or reactor.
Phase angle regulation (phase shift) is shown in Figure (c) where Vpq = V ' is injected
with an angular relationship with respect to V, that achieves the desired phase shift (advance or
retard) without any change in magnitude. Thus the UPFC can function as a perfect Phase Angle
Regulator which, can also supply the reactive power involved with the transmission angle control
by internal var generation.
Multifunction power flow control, executed by simultaneous terminal voltage regulation,
series capacitive line compensation, and phase shifting, is shown in Figure (d) where Vpq = V +
Vq + Y '. This functional capability is unique to the UPFC. No single conventional equipment has
similar multifunctional capability.

65
HVDC Transmission Systems (3160921) VGEC Chandkheda

Case Study: Unified Power Flow Controller (UPFC) Used to Relieve Power
Congestion on a 500/230 kV Grid

Circuit Description

A UPFC is used to control the power flow in a 500 kV /230 kV transmission system. The
system, connected in a loop configuration, consists essentially of five buses (B1 to B5)
interconnected through transmission lines (L1, L2, L3) and two 500 kV/230 kV transformer banks
Tr1 and Tr2. Two power plants located on the 230-kV system generate a total of 1500 MW which
is transmitted to a 500-kV 15000-MVA equivalent and to a 200-MW load connected at bus B3.
The plant models include a speed regulator, an excitation system as well as a power system
stabilizer (PSS). In normal operation, most of the 1200-MW generation capacity of power plant #2
is exported to the 500-kV equivalent through three 400-MVA transformers connected between
buses B4 and B5. For this demo we are considering a contingency case where only two transformers
out of three are available (Tr2= 2*400 MVA = 800 MVA).

66
HVDC Transmission Systems (3160921) VGEC Chandkheda

Using the load flow option of the powergui block, the model has been initialized with plants
#1 and #2 generating respectively 500 MW and 1000 MW and the UPFC out of service (Bypass
breaker closed). The resulting power flow obtained at buses B1 to B5 is indicated by red numbers
on the circuit diagram. The load flow shows that most of the power generated by plant #2 is
transmitted through the 800-MVA transformer bank (899 MW out of 1000 MW), the rest (101
MW), circulating in the loop. Transformer Tr2 is therefore overloaded by 99 MVA. The
demonstration illustrates how the UPFC can relieve this power congestion.

The UPFC located at the right end of line L2 is used to control the active and reactive powers
at the 500-kV bus B3, as well as the voltage at bus B_UPFC. It consists of a phasor model of two
100-MVA, IGBT-based, converters (one connected in shunt and one connected in series and both
interconnected through a DC bus on the DC side and to the AC power system, through coupling
reactors and transformers). Parameters of the UPFC power components are given in the dialog box.
The series converter can inject a maximum of 10% of nominal line-toground voltage (28.87 kV) in
series with line L2. The blue numbers on the diagram show the power flow with the UPFC in
service and controlling the B3 active and reactive powers respectively at 687 MW and -27 Mvar.

Demonstration

1. Power control with the UPFC

Open the UPFC dialog box and select "Display Control parameters (series converter)". The
control parameters of the series converter are displayed. Verify that "Mode of operation = Power
flow control". The UPFC reference active and reactive powers are set in the magenta blocks labeled
"Pref(pu)" and "Qref(pu)". Initially the Bypass breaker is closed and the resulting natural power
flow at bus B3 is 587 MW and -27 Mvar. The Pref block is programmed with an initial active power
of 5.87 pu corresponding to the natural flow. Then, at t=10s, Pref is increased by 1 pu (100 MW),
from 5.87 pu to 6.87 pu, while Qref is kept constant at -0.27 pu.

Run the simulation and look on the "UPFC" scope how P and Q measured at bus B3 follow
the reference values. At t=5 s, when the Bypass breaker is opened the natural power is diverted
from the Bypass breaker to the UPFC series branch without noticeable transient. At t=10 s, the
power increases at a rate of 1 pu/s. It takes one second for the power to increase to 687 MW. This
100 MW increase of active power at bus B3 is achieved by injecting a series voltage of 0.089 pu
with an angle of 94 degrees. This results in an approximate 100 MW decrease in the active power

67
HVDC Transmission Systems (3160921) VGEC Chandkheda

flowing through Tr2 (from 899 MW to 796 MW), which now carries an acceptable load. See the
variations of active powers at buses B1 to B5 on the "VPQ Lines" scope.

2. UPFC P-Q controllable region

Now, open the UPFC dialog box and select "Show Control parameters (series converter)".
Select "Mode of operation= Manual Voltage injection". In this control mode the voltage generated
by the series inverter is controlled by two external signals Vd, Vq multiplexed at the "Vdqref" input
and generated in the Vdqref magenta block. For the first five seconds the Bypass breaker stays
closed, so that the PQ trajectory stays at the (-27Mvar, 587 MW) point. Then when the breaker
opens, the magnitude of the injected series voltage is ramped, from 0.0094 to 0.1 pu. At 10 s, the
angle of the injected voltage starts varying at a rate of 45 deg./s.

Run the simulation and look on the "UPFC" scope the P and Q signals who vary according
to the changing phase of the injected voltage. At the end of the simulation, doubleclick on the blue
block located at the bottom right of the model. The trajectory of the UPFC reactive power as
function of its active power, measured at bus B3 will be displayed. The area located inside the
ellipse represents the UPFC controllable region.

Conclusion: By studying this practical, we understand the simulation of Power Flow control in a five
bus system using UPFC and learned about its implementation.

68
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No- 09
Series Compensation of a Three-Phase Transmission Line
AIM: Study of Series Compensation of a Three-Phase Transmission Line

Introduction

69
HVDC Transmission Systems (3160921) VGEC Chandkheda

70
HVDC Transmission Systems (3160921) VGEC Chandkheda

Case Study: Study of Series Compensation of a Three-Phase Transmission Line

Circuit Description

A three-phase, 60 Hz, 735 kV power system transmitting power from a power plant
consisting of six 350 MVA generators to an equivalent network through a 600 km transmission
line. The transmission line is split in two 300 km lines connected between buses B1,B2, and B3. In
order to increase the transmission capacity, each line is series compensated by capacitors
representing 40% of the line reactance. Both lines are also shunt compensated by a 330 Mvar shunt
reactance. The shunt and series compensation equipments are located at the B2 substation where a
300 MVA 735/230 kV transformer with a 25 kV tertiary winding feeds a 230 kV, 250 MW load.
The series compensation subsystems are identical for the two lines. For each line, each phase of the
series compensation module contains the series capacitor , a metal oxide varistor (MOV) protecting
the capacitor, and a parallel gap protecting the MOV. When the energy dissipated in the MOV
exceeds a threshold level of 30 MJ, the gap simulated by a circuit breaker is fired. CB1 and CB2
are the two line circuit breakers .

The generators are simulated with a Simplified Synchronous Machine block. Universal
transformer blocks (two-windings and three-windings) are used to model the two transformers.
Saturation is implemented on the transformer connected at bus B2. Voltages and currents are
measured in B1, B2, and B3 blocks. These blocks are Three-phase V-I Measurement blocks where
voltage and current signals are sent to the Data Acquisition block through Goto blocks.

Fault and Line Switching

We study the transient performance of this circuit when a line-to-ground and threephase-to-
ground faults are applied on line 1. The fault and the two line circuit breakers CB1 and CB2 are
simulated with blocks from the three-phase library. Open the dialog boxes of CB1 and CB2. See
how the initial breaker status and switching times are specified. A line-to-ground fault is applied
on phase A at t = 1cycle. The two circuit breakers which are initially closed are then open at t = 5
cycles, simulating a fault detection and opening time of 4 cycles. The fault is eliminated at t = 6
cycles, one cycle after line opening.

71
HVDC Transmission Systems (3160921) VGEC Chandkheda

Demonstration

Notice that this system contains the Powergui block. In addition, when you start the system
the 'power_3phseriescomp' model, the sampling time Ts = 50e-6 is automatically set in your
workspace. The system is therefore be discretized using a 50 microseconds sample time.

Line-to-Ground Fault

Double click the Data Acquisition block and open the three scopes. Start the simulation.
As the system has already been initialized (1500 MW generation at the 13.8 kV bus) with the Lod
Flow utility of the Powergui, the simulation starts in steady state. At t = 1 cycle a line-toground
fault is applied and the fault current reaches 10 kA . During the fault, the MOV conducts at every
half cycle and the energy dissipated in the MOV builds up to 13 MJ.

At t = 5 cycles the line protection relays (not simulated) open breakers CB1 and CB2 and
the energy stays constant at 13 MJ. As the maximum energy does not exceed the 30 MJ threshold
level, the gap is not fired. After breaker opening the fault current drops to a small value and the line
and series capacitance start to discharge through the fault and the shunt reactance. The fault current
extinguishes at the first zero crossing after the opening order given to the fault breaker (t = 6 cycles).
Then, the series capacitor stops discharging and its voltage oscillates around 220 kV.

Three-Phase-to-Ground Fault

Change the fault type to a three-phase-to-ground fault by checking Phases A, B, and C in

the Fault Breaker block. Restart the simulation. Notice that during the fault the energy dissipated
in the MOV builds up faster that in the case of a line-to-ground fault. The energy reaches the 30
MJ threshold level after 3 cycles, one cycle before opening of the line breakers. As a result, the gap
is fired and the capacitor voltage quickly discharges to zero through the damping circuit.

Conclusion: By studying this experiment we understand about the Series Compensation of a Three-
Phase Transmission Line and learned about its demonstration.

72
HVDC Transmission Systems (3160921) VGEC Chandkheda

Experiment No.: 10
VSC-Based HVDC Link
AIM: To study about VSC-Based HVDC Link

Introduction
The increasing rating and improved performance of self-commutated semiconductor devices have
made possible High Voltage DC (HVDC) transmission based on Voltage-Sourced Converter (VSC).
Two technologies offered by the manufacturers are the HVDC Light and the HVDC.
The example described in this section illustrates modeling of a forced-commutated Voltage-Sourced
Converter high-voltage direct current (VSC-HVDC) transmission link. The objectives of this
example are to demonstrate the use of Simscape™ Electrical™ Specialized Power Systems blocks in
the simulation of a HVDC transmission link based on three-level Neutral Point Clamped (NPC) VSC
converters with single-phase carrier based Sinusoidal Pulse Width Modulation (SPWM) switching.
Perturbations are applied to examine the system dynamic performance.
Description of the HVDC Link:
The principal characteristic of VSC-HVDC transmission is its ability to independently control the
reactive and real power flow at each of the AC systems to which it is connected, at the Point of
Common Coupling (PCC). In contrast to line-commutated HVDC transmission, the polarity of the
DC link voltage remains the same with the DC current being reversed to change the direction of
power flow.
The HVDC link described in this example is available in the power_hvdc_vsc model. You can run the
command by entering the following in the MATLAB® Command Window: power_hvdc_vsc. Load this
model and save it in your working directory as case5 to allow further modifications to the original
system. This model represents a 200 MVA, +/- 100 kV VSC-HVDC transmission link.
The 230 kV, 2000 MVA AC systems (AC system1 and AC system2 subsystems) are modeled by
damped L-R equivalents with an angle of 80 degrees at fundamental frequency (50 Hz) and at the
third harmonic. The VSC converters are three-level bridge blocks using IGBT/diodes. The relative
ease with which the IGBT can be controlled and its suitability for high-frequency switching, has made
this device the better choice over GTO and thyristors. Open the Station 1 and Station 2 subsystems
to see how they are built.
A converter transformer (Wye grounded /Delta) is used to permit the optimal voltage transformation.
The present winding arrangement blocks tripplen harmonics produced by the converter. The
transformer tap changer or saturation are not simulated. The tap position is rather at a fixed position
determined by a multiplication factor applied to the primary nominal voltage of the converter

73
 HVDC Transmission Systems (3160921) VGEC Chandkheda

transformers The multiplication factors are chosen to have a modulation index around 0.85
(transformer ratios of 0.915 on the rectifier side and 1.015 on the inverter side). The converter reactor
and the transformer leakage reactance permit the VSC output voltage to shift in phase and amplitude
with respect to the AC system, and allows control of converter active and reactive power output.
To meet AC system harmonic specifications, AC filters form an essential part of the scheme. They
can be connected as shunt elements on the AC system side or the converter side of the converter
transformer. Since there are only high frequency harmonics, shunt filtering is therefore relatively
small compared to the converter rating. It is sufficient with a high pass-filter and no tuned filters are
needed. The later arrangement is used in our model and a converter reactor, an air cored device,
separates the fundamental frequency (filter bus) from the raw PWM waveform (converter bus). The
AC harmonics generation [4] mainly depends on the:
 Type of modulation (e.g. single-phase or three-phase carrier based, space vector, etc.)
 Frequency index p = carrier frequency / modulator frequency (e.g. p = 1350/50 = 27)
 Modulation index m = fundamental output voltage of the converter / pole to pole DC voltage
The principal harmonic voltages are generated at and around multiples of p. The shunt AC filters are
27th and 54th high pass totaling 40 Mvar. To illustrate the AC filter action, we did an FFT analysis
in steady state of the converter phase A voltage and the filter bus phase A voltage, using the Powergui
block. The results are shown in Phase A Voltage and FFT Analysis: (a) Converter Bus (b) Filter Bus.
Phase A Voltage and FFT Analysis: (a) Converter Bus (b) Filter Bus

74
HVDC Transmission Systems (3160921) VGEC Chandkheda

The reservoir DC capacitors are connected to the VSC terminals. They have an influence on the
system dynamics and the voltage ripple on the DC side. The size of the capacitor is defined by the
time constant τ corresponding to the time it takes to charge the capacitor to the base voltage (100 kV)
if it is charged with the base current (1 kA). This yields
τ = C · Zbase = 70e-6 · 100 = 7 ms
with Zbase = 100kV/1 kA
The DC side filters blocking high-frequency are tuned to the 3rd harmonic, i.e., the main harmonic
present in the positive and negative pole voltages. It is shown that a reactive converter current
generate a relatively large third harmonic in both the positive and negative pole voltages [3] but not
in the total DC voltage. The DC harmonics can also be zero-sequence harmonics (odd multiples of
3) transferred to the DC side (e.g., through the grounded AC filters). A smoothing reactor is connected
in series at each pole terminal.
To keep the DC side balanced, the level of the difference between the pole voltages has to be
controlled and kept to zero (see the DC Voltage Balance Control block in the VSC Controller block).
The rectifier and the inverter are interconnected through a 75 km cable (2 pi sections). The use of
underground cable is typical for VSC-HVDC links. A circuit breaker is used to apply a three-phase
to ground fault on the inverter AC side. A Three-Phase Programmable Voltage Source block is used
in station 1 system to apply voltage sags.
VSC Control System
Overview of the Control System of a VSC Converter and Interface to the Main Circuit shows an
overview diagram of the VSC control system and its interface with the main circuit.
Overview of the Control System of a VSC Converter and Interface to the Main Circuit

75
 HVDC Transmission Systems (3160921) VGEC Chandkheda

The converter 1 and converter 2 controller designs are identical. The two controllers are independent
with no communication between them. Each converter has two degrees of freedom. In our case, these
are used to control:
 P and Q in station 1 (rectifier)
 Udc and Q in station 2 (inverter).
The control of the AC voltage would be also possible as an alternative to Q. This requires an extra
regulator which is not implemented in our model.
Open the VSC Controller subsystem to see the details.
The sample time of the controller model (Ts_Control) is 74.06 µs, which is ten times the simulation
sample time. The later is chosen to be one hundredth of the PWM carrier period (i.e., 0.01/1350 s)
giving an acceptable simulation precision. The power elements, the anti-aliasing filters and the PWM
Generator block use the fundamental sample time (Ts_Power) of 7.406 µs. The unsynchronized
PWM mode of operation is chosen for our model.

76
HVDC Transmission Systems (3160921) VGEC Chandkheda

The normalized sampled voltages and currents (in pu) are provided to the controller.
The Clark Transformations block transforms the three-phase quantities to space vector components
α and β (real and imaginary part). The signal measurements (U and I) on the primary side are rotated
by ±pi/6 according to the transformer connection (YD11 or YD1) to have the same reference frame
with the signal measured on the secondary side of the transformer (see block CLARK YD).
The dq transformations block computes the direct axis “d” and the quadratic axis “q” quantities (two
axis rotating reference frame) from the α and β quantities.
The Signal Calculations block calculates and filters quantities used by the controller (e.g., active and
reactive power, modulation index, DC current and voltage, etc.).
Phase Locked Loop(PLL)
The Phase Locked Loop block measures the system frequency and provides the phase synchronous
angle Θ (more precisely [sin(Θ), cos(Θ)]) for the dq Transformations block. In steady state, sin(Θ) is
in phase with the fundamental (positive sequence) of the α component and phase A of the PCC voltage
(Uabc).
Outer Active and Reactive Power and voltage loop\
The active and reactive power and voltage loop contains the outer loop regulators that calculates the
reference value of the converter current vector (Iref_dq) which is the input to the inner current loop.
The control modes are: in the “d” axis, either the active power flow at the PCC or the pole-to-pole
DC voltage; in the “q” axis, the reactive power flow at the PCC. Note that, it would be also possible
to add an AC voltage control mode at the PCC in the “q” axis. The main functions of the Active and
reactive power and voltage loop are described below.
The Reactive Power Control regulator block combines a PI control with a feedforward control to
increase the speed response. To avoid integrator wind-up the following actions are taken: the error is
reset to zero, when the measured PCC voltage is less than a constant value (i.e., during an AC
perturbation); when the regulator output is limited, the limitation error is fed back with the right sign,
to the integrator input. The AC Voltage control override block, based on two PI regulators, will
override the reactive power regulator to maintain the PCC AC voltage within a secure range,
especially in steady-state.
The Active Power Control block is similar to the Reactive Power Control block. The extra Ramping
block ramps the power order towards the desired value with an adjusted rate when the control is de-
blocked. The ramped value is reset to zero when the converter is blocked. The DC Voltage control
override block, based on two PI regulators, will override the active power regulator to maintain the
DC voltage within a secure range, especially during a perturbation in the AC system of the station
controlling the DC voltage.

77
HVDC Transmission Systems (3160921) VGEC Chandkheda

The DC Voltage Control regulator block uses a PI regulator. The block is enabled when the Active
Power Control block is disabled. The block output is a reference value, for the “d” component of
converter current vector, for the Current Reference Limitation block.
The Current Reference Calculation block transforms the active and reactive power references,
calculated by the P and Q controllers, to current references according to the measured (space vector)
voltage at the filter bus. The current reference is estimated by dividing the power reference by the
voltage (up to a minimum preset voltage value).
The current reference vector is limited to a maximum acceptable value (i.e., equipment dependent)
by the Current Reference Limitation block. In power control mode, equal scaling is applied to the
active and reactive power reference when a limit is imposed. In DC voltage control mode, higher
priority is given to the active power when a limit is imposed for an efficient control of the voltage.
Inner Current Loop
The main functions of Inner Current Loop block are described below.
The AC Current Control block tracks the current reference vector (“d” and “q” components) with a
feed forward scheme to achieve a fast control of the current at load changes and disturbances (e.g.,
so short-circuit faults do not exceed the references) [3] [5] [6]. In essence, it consist of knowing the
U_dq vector voltages and computing what the converter voltages have to be, by adding the voltage
drops due to the currents across the impedance between the U and the PWM-VSC voltages. The state
equations representing the dynamics of the VSC currents are used (an approximation is made by
neglecting the AC filters). The “d” and “q” components are decoupled to obtain two independent
first-order plant models. A proportional integral (PI) feedback of the converter current is used to
reduce the error to zero in steady state. The output of the AC Current Control block is the unlimited
reference voltage vector Vref_dq_tmp.
The Reference Voltage Conditioning block takes into account the actual DC voltage and the
theoretical maximum peak value of the fundamental bridge phase voltage in relation to the DC
voltage to generate the new optimized reference voltage vector. In our model (i.e., a three-level NPC
with carrier based PWM), the ratio between the maximum fundamental peak phase voltage and the
DC total voltage (i.e., for a modulation index of 1) is (G2)/(G3) = 0.816. By choosing a nominal line
voltage of 100 kV at the transformer secondary bus and a nominal total DC voltage of 200 kV the
nominal modulation index would be 0.816. In theory, the converter should be able to generate up to
1/0.816 or 1.23 pu when the modulation index is equal to 1. This voltage margin is important for
generating significant capacitive converter current (i.e., a reactive power flow to the AC system).
The Reference Voltage Limitation block limits the reference voltage vector amplitude to 1.0, since
over modulation is not desired.

78
HVDC Transmission Systems (3160921) VGEC Chandkheda

The Inverse dq and Inverse Clark transformation blocks are required to generate the three-phase
voltage references to the PWM.
DC Voltage Balance Control
The DC Voltage Balance Control can be enabled or disabled. The difference between the DC side
voltages (positive and negative) are controlled to keep the DC side of the three level bridge balanced
(i.e., equal pole voltages) in steady-state. Small deviations between the pole voltages may occur at
changes of active/reactive converter current or due to nonlinearity on lack of precision in the
execution of the pulse width modulated bridge voltage. Furthermore, deviations between the pole
voltages may be due to inherent unbalance in the circuit components impedance.
The DC midpoint current Id0 determines the difference Ud0 between the upper and lower DC voltages
(DC Voltages and Currents of the Three-Level Bridge) .
DC Voltages and Currents of the Three-Level Bridge

Id0=−(Id1+Id2)=−C⋅ (Ud1−Ud2)=−C⋅ (Ud0)

ddt ddt

By changing the conduction time of the switches in a pole it is possible to change the average of the
DC midpoint current Id0 and thereby control the difference voltage Ud0. For example, a positive
difference (Ud0 ≥ 0) can be decreased to zero if the amplitude of the reference voltage which generates
a positive midpoint current is increased at the same time as the amplitude of the reference voltage
which generates a negative DC midpoint current is decreased. This is done by the addition of an offset
component to the sinusoidal reference voltage. Consequently, the bridge voltage becomes distorted,
and to limit the distortion effect, the control has to be slow. Finally, for better performance this
function should be activated in the station controlling the DC voltage.
Dynamic Performance:
In the next sections, the dynamic performance of the transmission system is verified by simulating
and observing the

79
HVDC Transmission Systems (3160921) VGEC Chandkheda

Dynamic response to step changes applied to the principal regulator references, like active/reactive
power and DC voltage
Recovery from minor and severe perturbations in the AC system
For a comprehensive explanation of the procedure followed obtaining these results and more, refer
to the Model Information block.
System Startup – Steady-State and Step Response
Startup and P & Q Step Responses in Station 1

The main waveforms from the scopes are reproduced below.

Startup and Udc Step Response in Station 2

80
HVDC Transmission Systems (3160921) VGEC Chandkheda

Station 2 converter controlling DC voltage is first deblocked at t=0.1 s. Then, station 1 controlling
active power converter is deblocked at t=0.3 s and power is ramped up slowly to 1 pu. Steady state
is reached at approximately t=1.3 s with DC voltage and power at 1.0 pu (200 kV, 200 MW). Both
converters control the reactive power flow to a null value in station 1 and to 20 Mvar (-0.1 pu) into
station 2 system.
After steady state has been reached, a -0.1 pu step is applied to the reference active power in converter
1 (t=1.5 s) and later a -0.1 pu step is applied to the reference reactive power (t=2.0 s). In station 2, a
-0.05 pu step is applied to the DC voltage reference. The dynamic response of the regulators are
observed. Stabilizing time is approximately 0.3 s.The control design attempts to decouple the active
and reactive power responses. Note how the regulators are more or less mutually affected.
AC side perturbations
From the steady-state condition, a minor and a severe perturbation are executed at station 1 and 2
systems respectively. A three-phase voltage sag is first applied at station 1 bus. Then, following the
system recovery, a three-phase to ground fault is applied at station 2 bus. The system recovery from
the perturbations should be prompt and stable. The main waveforms from the scopes are reproduced
in the two figures below.
Voltage Step on AC System 1

81
HVDC Transmission Systems (3160921) VGEC Chandkheda

The AC voltage step (-0.1 pu) is applied at t=1.5 s during 0.14 s (7 cycles) at station 1. The results
show that the active and reactive power deviation from the pre-disturbance is less than 0.09 pu and
0.2 pu respectively. The recovery time is less than 0.3 s and the steady state is reached before next
perturbation initiation.
The fault is applied at t=2.1 s during 0.12 s (6 cycles) at station 2.
Three-Phase to Ground Fault at Station 2 Bus

82
HVDC Transmission Systems (3160921) VGEC Chandkheda

Note that during the three-phase fault the transmitted DC power is almost halted and the DC voltage
tends to increase (1.2 pu) since the DC side capacitance is being excessively charged. A special
function (DC Voltage Control Override) in the Active Power Control (in station 1) attempts to limit
the DC voltage within a fixed range. The system recovers well after the fault, within 0.5 s. Note the
damped oscillations (around 10 Hz) in the reactive power.

Conclusion: By studying this experiment we understand about the VSC-Based HVDC Link and
performed it, we get the final output in graph form and we got the value of it in terms if Udc and p.u.

83