Machine Instruction

Introduction
 It determines the Operation of the Processor

 Collection of different instructions that the processor can

execute is processor’s instruction set
Elements
 Operation Code (OpCode) -Type of Operation performed
◦ Defined by abbreviations called mnemonics

 Source Operand – One or More inputs

 Result Operand – Output

 Next Instruction Reference

Pentium Data Types
 8 bit Byte

 16 bit word

 32 bit double word

 64 bit quad word

 Addressing is by 8 bit unit

 A 32 bit double word is read at addresses divisible by 4

Specific Data Types
 General - arbitrary binary contents
 Integer - single binary value
 Ordinal - unsigned integer
 Unpacked BCD - One digit per byte
 Packed BCD - 2 BCD digits per byte
 Near Pointer - 32 bit offset within segment
 Bit field
 Byte String
 Floating Point
Numeric Data Formats
PowerPC Data Types
 8 (byte), 16 (halfword), 32 (word) and 64 (doubleword) length data types
 Some instructions need operand aligned on 32 bit boundary
 Can be big- or little-endian
 Fixed point processor recognises:
◦ Unsigned byte, unsigned halfword, signed halfword, unsigned word, signed word,
unsigned doubleword, byte string (<128 bytes)

 Floating point
◦ IEEE 754
◦ Single or double precision
Operand -Source
 Main or Virtual Memory

 Processor Register

 Immediate

 I/O Device
 Instruction Representation
OpCode Operand Reference Operand Reference
(4 bits) (6 bits) (6 bits)
Instruction Types
 Assume X = X + Y
◦ Load the register with value X
◦ Add the contents of register to the value Y
◦ Store the contents in the address of X
 Data Processing – Arithmetic and Logical Instruction
 Data Storage - Movement of data into or out of register and or
memory location
 Data Movement – I / O instruction
 Control – Test and Branching instruction
Number of Addresses
 Zero Address – e.g. Break, End

 One Address – Using accumulator as another operand by

default

 Two Address – One as Input and another as Output by default

 Three Address – Two operands as input and one operand as

output

 Trade off between No. of addresses and No. of Instruction

 INSTRUCTION SET
A set of instructions is said to be complete if the computer includes a
sufficient number of instructions in each of the following categories:

 Arithmetic, logical and shift instructions

 A set of instructions for moving information to and from memory and

processor registers.

 Instructions which controls the program together with instructions that

check status conditions.

 Input and Output instructions

Instruction Set Design
 Operation repertoire

 Data Types

 Instruction Format

 Registers

 Addressing
Types of Operands
 Addresses
 Numbers
◦ Binary Integer or fixed point
◦ Binary Floating Point
◦ Decimal

 Characters
◦ ASCII, EBCDIC in IBM mainframe

 Logical Data
Types of Operations
 Data Transfer

 Arithmetic

 Logical

 Conversion

 I/O

 System Control

 Transfer of Control
Data Transfer – Processor Activities
 Data transfer from one memory location to another

 Determine Memory Location

 Perform Physical to actual memory translation

 Check Cache

 Initiate Memory read / write

Data Transfer
 Move

 Store

 Load

 Exchange

 Clear

 Set

 Push

 Pop
Arithmetic – Processor Activities
 Data Transfer before and/or after

 Perform function in ALU

 Set conditional codes and flags

Arithmetic
 Add

 Subtract

 Multiply

 Divide

 Absolute

 Negate

 Increment

 Decrement
Arithmetic – Single Operand
 Absolute

 Negate

 Increment

 Decrement
Logical
 And

 Or

 Not

 Ex-OR

 Test

 Compare

 Set Control Variables

 Shift – Arithmetic Shift, Rotate

 Rotate
Conversion
 Type Conversion – Convert

 Translate instruction – Translate

◦ TR R1 (L), R2
Input / Output & System Control
 Issue Command to I/O Module

 If memory mapped I/O, determine memory mapped address

 Input (read)

 Output (write)

 Start I/O

 Test I / O

 Required Privileged execution space

Transfer of Control
 Update Program Counter

 For subroutine call / return, manage parameter passing and linkage

 Branch
◦ Conditional or Unconditional

 Skip
◦ Skip if Zero (ISZ)

 Procedure Call
◦ Reentrant Procedure, one type is Recursive Procedure Call
Transfer of Control
Transfer of Control
Use of Stack
Stack Frame Growth -Sample Procedures P and Q
System Control
 Commands executed under privileged mode

 Processor in a special privileged state of operation

 Reserved mostly by operating system

 E.g. Access to process control blocks during multiprogramming

LITTLE, BIG, BI-ENDIAN
Byte Order (A portion of chips?)
 What order do we read numbers that occupy more than one byte

 e.g. (numbers in hex to make it easy to read)

 12345678 can be stored in 4x8bit locations as follows

Byte Order (example)
 Address Value (1) Value(2)

 184 12 78

 185 34 56

 186 56 34

 186 78 12

 i.e. read top down or bottom up?

Byte Order Names
 The problem is called Endian

 The system on the left has the least significant byte in the lowest
address is called big-endian

 The system on the right has the least significant byte in the
highest address is called little-endian
Example of C Data Structure
Alternative View of Memory Map
Standard…What Standard?
 Pentium (80x86), VAX are little-endian

 IBM 370, Moterola 680x0 (Mac), and most RISC are big-endian

 Internet is big-endian
ADDRESSING MODE
Addressing Mode
Mode in which operands are addressed
 Immediate
 Direct
 Indirect
 Register
 Register Indirect
 Displacement
 Stack
Immediate Addressing
 Operand is part of instruction

 Operand = address field

 e.g. ADD 5

◦ Add 5 to contents of accumulator

◦ 5 is operand

 No memory reference to fetch data

 Fast

 Limited range
Immediate Addressing Diagram
Instruction

Opcode Operand
Addressing modes - Immediate
Direct Addressing
 Address field contains address of operand

 Effective address (EA) = address field (A)

 e.g. ADD A

◦ Add contents of cell A to accumulator

◦ Look in memory at address A for operand

 Single memory reference to access data

 No additional calculations to work out effective address

 Limited address space

 Direct Addressing Diagram
Instruction

Opcode Address A
Memory

Operand
Addressing modes - Direct
Indirect Addressing
 Memory cell pointed to by address field contains the address of
(pointer to) the operand

 EA = (A)

◦ Look in A, find address (A) and look there for operand

 e.g. ADD (A)

◦ Add contents of cell pointed to by contents of A to accumulator

Indirect Addressing
 Large address space

 2n where n = word length

 May be nested, multilevel, cascaded

◦ e.g. EA = (((A)))

 Multiple memory accesses to find operand

 Hence slower
 Indirect Addressing Diagram
Instruction

Opcode Address A
Memory

Pointer to operand

Operand
Addressing modes - Indirect
Register Addressing
 Similar to direct addressing

 Operand is held in register named in address filed

 EA = R

 Limited number of registers

 Very small address field needed

◦ Shorter instructions

◦ Faster instruction fetch

Register Addressing
 No memory access

 Very fast execution

 Very limited address space

 Multiple registers helps performance

◦ Requires good assembly programming or compiler writing

◦ N.B. C programming

 register int a;
 Register Addressing Diagram
Instruction

Opcode Register Address R

Registers

Operand
Addressing modes - Register Direct
Register Indirect Addressing
 Similar to indirect addressing

 EA = (R)

 Operand is in memory cell pointed to by contents of register R

 Large address space (2n)

 One fewer memory access than indirect addressing

Register Indirect Addressing Diagram
Instruction

Opcode Register Address R

Memory

Registers

Pointer to Operand Operand

Addressing modes - Register Indirect

@R
Displacement Addressing
 Combines capability of direct and register indirect addressing

 EA = A + (R)

 Address field hold two values

◦ A = base value

◦ R = register that holds displacement

◦ or vice versa
 Displacement Addressing Diagram
Instruction

Opcode Register R Address A

Memory

Registers

Pointer to Operand + Operand

Relative Addressing
 A version of displacement addressing

 R = Program counter, PC – implicitly referred

 EA = A + (PC)

 i.e. get operand from A cells from current location pointed to by

PC

 c.f locality of reference & cache usage

Addressing modes - Relative
Base-Register Addressing
 A holds displacement

 R holds pointer to base address

 R may be explicit or implicit

 e.g. segment registers in 80x86

Indexed Addressing
 A = base (main memory address)

 R = displacement

 EA = A + R

 Good for accessing arrays

◦ EA = A + R

◦ R++

 AutoIndexing
Combinations
Postindex

 EA = (A) + (R)

Preindex

 EA = (A+(R))
Addressing modes - Indexed
Stack Addressing
 Last in First Out

 Operand is (implicitly) on top of stack

 e.g.

◦ ADD Pop top two items from stack and add

Addressing modes - Implicit
Summary
X86 Addressing Mode
x86 Addressing Mode Calculation
x86 Addressing Modes
 Virtual or effective address is offset into segment
◦ Starting address plus offset gives linear address
◦ This goes through page translation if paging enabled
 12 addressing modes available
◦ Immediate
◦ Register operand
◦ Displacement
◦ Base
◦ Base with displacement
◦ Scaled index with displacement
◦ Base with index and displacement
◦ Base scaled index with displacement
◦ Relative
ARM Addressing Modes - Load/Store
 Only instructions that reference memory
 Indirectly through base register plus offset
 Offset
◦ Offset added to or subtracted from base register contents to form
the memory address
 Preindex
◦ Memory address is formed as for offset addressing
◦ Memory address also written back to base register
◦ So base register value incremented or decremented by offset value
ARM Addressing Modes - Load/Store
 Postindex

◦ Memory address is base register value

◦ Offset added or subtracted

Result written back to base register

 Base register acts as index register for preindex and postindex addressing

 Offset either immediate value in instruction or another register

 If scaled register addressing available

◦ Offset register value scaled by shift operator

◦ Instruction specifies shift size

ARM Indexing Method
ARM Data Processing Instruction Addressing
& Branch Instructions
 Data Processing
◦ Register addressing
 Value in register operands may be scaled using a shift operator
◦ Or mixture of register and immediate addressing
 Branch
◦ Immediate
◦ Instruction contains 24 bit value
◦ Shifted 2 bits left
 On word boundary
 Effective range +/-32MB from PC.
ARM Load/Store Multiple Addressing
 Load/store subset of general-purpose registers
 16-bit instruction field specifies list of registers
 Sequential range of memory addresses
 Increment after, increment before, decrement after, and decrement
before
 Base register specifies main memory address
 Incrementing or decrementing starts before or after first memory
access
ARM Load/Store Multiple Addressing Diagram
Instruction Format
Instruction Formats
 Layout of bits in an instruction

 Includes opcode

 Includes (implicit or explicit) operand(s)

 Usually more than one instruction format in an instruction set

Instruction Length
 Affected by and affects:
◦ Memory size
◦ Memory organization
◦ Bus structure
◦ CPU complexity
◦ CPU speed

 Trade off between powerful instruction repertoire and saving

space
Allocation of Bits
 Number of addressing modes

 Number of operands

 Register versus memory

 Number of register sets

 Address range

 Address granularity
Instruction Set Architecture
 Instruction set
 Register set
 Memory access information
ISA Attributes
 Completeness
 Orthogonality
 Register set design
ISA Requirements
 Backward compatibility
 Data types/sizes
 Interrupts
 Conditional instructions
A Relatively Simple ISA - Registers
 Accumulator AC
 General purpose register R
 Flag Z
The 8085 ISA - Instruction Set
 Data movement instructions
The 8085 ISA - Instruction Set
 Data operation instructions
The 8085 ISA - Instruction Set
 Program control instructions
The 8085 ISA - Instruction Formats
Example 8085 Program

n
1  2  ...  n, or i
i 1

1. i = n, sum = 0
2. sum = sum + i, i = i - 1
3. IF i  0 THEN GOTO 2
4. total = sum
Example 8085 Program Code
Example 8085 Program Trace
 Comparison

Property 8085 Microprocessor 8086 Microprocessor

Data Bus Size 8-Bit 16-Bit

Address Bus Size 16-bit 20-bit

Clock Speed 3MHz Varies in range 5.8 – 10 MHz

Duty Cycle for clock 50% 33%

It has 9 flags (Overflow, Direction,

It has 5 flags (Sign, Zero, Auxiliary Carry,
Flags Interrupt. Trap, Sign, Zero, Auxiliary
Parity, Carry)
Carry, Parity, Carry)
 Comparison

Property 8085 Microprocessor 8086 Microprocessor

Pipelining Support Does not support Supports

Memory Segmentation Does not support Supports

supports

Number of transistors Nearly 6500 Nearly 29000

Processor type Accumulator based General Purpose register based

Presence of Minimum Not present Present

and Maximum mode
 Comparison

Property 8085 Microprocessor 8086 Microprocessor

Number of processors Only one processor is used More than one processor is used.
Additional processor (external) can
also be employed

Memory Size 64KB 1MB

Instruction No multiplication and division Multiplication and Division

instruction operations are present

Instruction Queue Does not support Supports

Support
PDP-8 Instruction Format
PDP-10 Instruction Format
PDP-11 Instruction Format
VAX Instruction Examples
x86 Instruction Format
 ARM Instruction Formats

 S = For data processing instructions, updates condition codes

 S = For load/store multiple instructions, execution restricted to supervisor mode
 P, U, W = distinguish between different types of addressing_mode
 B = Unsigned byte (B==1) or word (B==0) access
 L = For load/store instructions, Load (L==1) or Store (L==0)
 L = For branch instructions, is return address stored in link register
ARM Immediate Constants
Thumb Instruction Set
 Re-encoded subset of ARM instruction set
 Increases performance in 16-bit or less data bus
 Unconditional (4 bits saved)
 Always update conditional flags
◦ Update flag not used (1 bit saved)
 Subset of instructions
◦ 2 bit opcode, 3 bit type field (1 bit saved)
◦ Reduced operand specifications (9 bits saved)
Expanding Thumb ADD Instruction to ARM Equivalent Fig 11.12
Assembler
 Machines store and understand binary instructions
 E.g. N= I + J + K initialize I=2, J=3, K=4
 Program starts in location 101
 Data starting 201
 Code:
 Load contents of 201 into AC
 Add contents of 202 to AC
 Add contents of 203 to AC
 Store contents of AC to 204
 Tedious and error prone
Improvements
 Use hexadecimal rather than binary
◦ Code as series of lines
 Hex address and memory address
◦ Need to translate automatically using program
 Add symbolic names or mnemonics for instructions
 Three fields per line
◦ Location address
◦ Three letter opcode
◦ If memory reference: address
 Need more complex translation program
 Program in:
Address
Binary Contents
Hexadecimal
Address Contents

101 0010 0010 101 2201 101 2201

102 0001 0010 102 1202 102 1202

103 0001 0010 103 1203 103 1203

104 0011 0010 104 3204 104 3204

201 0000 0000 201 0002 201 0002

202 0000 0000 202 0003 202 0003

203 0000 0000 203 0004 203 0004

204 0000 0000 204 0000 204 0000

Symbolic Addresses
 First field (address) now symbolic
 Memory references in third field now symbolic
 Now have assembly language and need an assembler to
translate
 Assembler used for some systems programming
◦ Compliers
◦ I/O routines
Symbolic Program
Address Instruction
101 LDA 201
102 ADD 202
103 ADD 203
104 STA 204

201 DAT 2
202 DAT 3
203 DAT 4
204 DAT 0
Assembler Program
Label Operation Operand
FORMUL LDA I
ADD J

ADD K

STA N

I DATA 2
J DATA 3
K DATA 4
N DATA 0