ELE301/302: Electronics III

Spring 2025
Lecture 4: Differential Amplifiers

Dr.Ahmed Abdeltawb
Electronics and Communications Engineering
Misr University for Science & Technology (MUST)
Announcements
• HW
• HW3 due today

• Reading
• Razavi Chapter 10

2
Exam 1
• In class on Feb 24
• 9:35 – 11:00 (10 extra minutes)
• Closed book w/ one standard note sheet
• 8.5”x11” front & back
• Bring your calculator
• Covers through Lecture 3
• Sample Exam1s posted on website
3
Agenda
• General considerations
• Bipolar differential pair
• MOS differential pair
• Cascode differential amplifiers
• Common-mode rejection
• Differential pair with active load

4
 Audio Amplifier Example

➢ An audio amplifier is constructed above that takes on a

rectified AC voltage as its supply and amplifies an audio
signal from a microphone.
CH 10 Differential Amplifiers 5
 “Humming” Noise in Audio Amplifier Example
Undesired power supply
noise component
Desired output signal

Vout = VCC + vr − IC RC + Avvin

Vin,DC + vin

VCC + vr

➢ However, VCC contains a ripple from rectification that leaks

to the output and is perceived as a “humming” noise by the
user.
CH 10 Differential Amplifiers 6
 Supply Ripple Rejection

vr

vX = Av vin + vr
vY = vr
vX − vY = Av vin

➢ Since both node X and Y contain the ripple, vr, their

difference will be free of ripple.

CH 10 Differential Amplifiers 7
 Ripple-Free Differential Output

vr

➢ Since the signal is taken as a difference between two

nodes, an amplifier that senses differential signals is
needed.
➢ How can we construct this differential amplifier?
CH 10 Differential Amplifiers 8
 Common Inputs to Differential Amplifier

v X = Av vin + vr
vY = Av vin + vr
v X − vY = 0

➢ Signals cannot be applied in phase to the inputs of a

differential amplifier, since the outputs will also be in phase,
producing zero differential output.
CH 10 Differential Amplifiers 9
 Differential Inputs to Differential Amplifier

vX = Av vin + vr
vY = − Av vin + vr
vX − vY = 2 Av vin

➢ When the inputs are applied differentially, the outputs are

180° out of phase; enhancing each other when sensed
differentially.
➢ Provides twice the output swing of the original amplifier
CH 10 Differential Amplifiers 10
 Differential Signals

➢ A pair of differential signals can be generated, among other

ways, by a transformer.
➢ Differential signals have the property that they share the
same average value to ground and are equal in magnitude
but opposite in phase.
CH 10 Differential Amplifiers 11
 Single-ended vs. Differential Signals

• Single-Ended Signals
• Measured with
respect to the Vout = Vo sin t + VCM
common ground
• Reside on one “line”
or node
• Differential Signals
• Measured between two nodes
• Reside on two differential “lines” or nodes

V1 = Vo sin t + VCM

V2 = −Vo sin t + VCM

V1 − V2 = 2Vo sin t

CH 10 Differential Amplifiers 12
Single-Ended & Differential Signals
• A single-ended signal is measured with respect to a fixed
potential (ground)
• A differential signal is measured between two equal and
opposite signals which swing around a fixed potential
(common-mode level)
• You can decompose differential signals into a differential
mode (difference) and a common-mode (average)
Single-Ended Signal Differential Signal

Vout+ + Vout−
VDM = V+
out −V −
out VCM =
2 13
Single-Ended & Differential Amplifiers
• Differential signaling
advantages Max Output Swing
• Common-mode noise VDD − (VGS − VTn )
rejection
• Higher (ideally double)
potential output swing
• Simpler biasing
• Improved linearity
• Main disadvantage is area,
which is roughly double
• Although, to get the same
performance in single-ended Max Output Swing
designs, we often have to
increase the area 2(VDD − (VGS − VTn ))
dramatically
14
Common-Mode Level Sensitivity
• A design which uses two single-ended amplifiers to realize a
differential amplifier is very sensitive to the common-mode
input level
• The transistors’ bias current and transconductance can vary
dramatically with the common-mode input
• Impacts small-signal gain
• Changes the output common-mode, which impacts the maximum
output swing

15
Agenda
• General considerations
• Bipolar differential pair
• MOS differential pair
• Cascode differential amplifiers
• Common-mode rejection
• Differential pair with active load

16
 Differential Pair

➢ With the addition of a tail current, the circuits above operate

as an elegant, yet robust differential pair.

CH 10 Differential Amplifiers 17
 Common-Mode Response

Assuming  = 1 for simplicity

VBE1 = VBE 2
IEE IEE I EE
2 2 IC1 = I C 2 =
2
I EE
VX = VY = VCC − RC
2

CH 10 Differential Amplifiers 18
 Common-Mode Rejection

➢ Due to the fixed tail current source, the

input common-mode value can vary
without changing the output common-
mode value.

Lower limit of VCM also occurs

due to the requirement of a
minimum “compliance” voltage
• Assuming VBC=0 for saturation (VCE~0.7V) across a real current source
• Often we allow for VBC=0.4V or VCE~0.3V and still consider “active” mode
operation, although this is formally “soft saturation”
• In any problems, I’ll make it clear what assumptions to use
CH 10 Differential Amplifiers 19
 Differential Response I – Big Differential Input

Cutoff
IEE
~ 1.3V
I C1 = I EE
IC 2 = 0
VX = VCC − RC IEE
VY = VCC
CH 10 Differential Amplifiers 20
 Differential Response II – Big Differential Input

Cutoff

IEE
I C 2 = I EE
~ 1.3V

IC1 = 0
VY = VCC − RC IEE
VX = VCC
CH 10 Differential Amplifiers 21
 Differential Pair Characteristics

IEE
Output Common Mode = VCC − RC
2
Transistor Currents Output Voltages

➢ None-zero differential input produces variations in output

currents and voltages, whereas common-mode input produces
no variations.
CH 10 Differential Amplifiers 22
 Small-Signal Analysis

IEE
I C1 = + I
2
IEE
IC2 = − I
2

➢ Since the input to Q1 and Q2 rises and falls by the same

amount, and their bases are tied together, the rise in IC1 has
the same magnitude as the fall in IC2.
CH 10 Differential Amplifiers 23
 Virtual Ground

VP = 0
IC1 = gm (V − VP ) IC1 = g m V
IC 2 = −g m (V + VP )
IC 2 = −g m V
Because IC1 = −IC 2

➢ For small changes at inputs, the gm’s are the same, and the
respective increase and decrease of IC1 and IC2 are the
same, node P must stay constant to accommodate these
changes. Therefore, node P can be viewed as AC ground.
CH 10 Differential Amplifiers 24
 Small-Signal Differential Gain

IC1 = gmV
IC 2 = −gmV
VX = −gmVRC
VY = gmVRC

V X − VY − 2g m VRC
Av = = = −g m RC
Vdiff 2V

➢ Since the output changes by -2gmVRC and input by 2V,

the small signal gain is –gmRC, similar to that of the CE
stage. However, to obtain same gain as the CE stage,
power dissipation is doubled.
CH 10 Differential Amplifiers 25
 Large Signal Analysis

• Objective: Find expressions for IC1 and IC2 as a function of the differential
input Vin1-Vin2
• This can then be used to find the differential output voltage
VBE
1. Using IC = I S e VT

I 
VBE1 = VT ln C1 
 IS 
 IC 2 
VBE 2 = VT ln 
 IS 
2. Writing a KVL around the input network
Vin1 − VBE1 = VP = Vin2 − VBE 2
Vin1 −Vin2 = VBE1 − VBE 2
I  I 
= VT ln C1  − VT ln C 2 
 IS   IS 
I 
= VT ln C1 
 IC 2 
CH 10 Differential Amplifiers 26
 Large Signal Analysis

3. Writing a KCL at node P

IC1 + IC 2 = IEE
4. Combining previous KVL equation with the KCL
Vin1 − Vin2
I C 2 exp + I C 2 = I EE
VT
IEE
IC 2 =
V −V
1+ exp in1 in2
VT
5. From circuit symmetry
Vin1 − Vin2
I EE exp
IEE VT
IC1 = =
V − Vin1 V −V
1+ exp in2 1 + exp in1 in2
VT VT

CH 10 Differential Amplifiers 27
 Input/Output Characteristics

Vin1 −Vin 2
I EEexp
VT
I C1 =
Vin1 −Vin 2
1+ exp
VT
I EE
IC2 =
Vin1 −Vin 2
1+ exp
VT

Vout1 −Vout 2 =
Vin1 −Vin 2
− RC I EE tanh
2VT
• If Vin1-Vin2 ≥ 4VT = 104mV, the majority of the current is steered through Q1
CH 10 Differential Amplifiers 28
 Linear/Nonlinear Regions

➢ The left column operates in linear region, whereas the right

column operates in nonlinear region.
CH 10 Differential Amplifiers 29
 Small-Signal Model

• We can use the virtual GND concept discussed in Slide 23 to simplify this
CH 10 Differential Amplifiers 30
Virtual GND Proof

1. KVL around the input networks

vin1 − v 1 = vP = vin2 − v 2
2. KCL at node P
v1 v
+ g m1v 1 +  2 + g m2 v 2 = 0
r1 r 2
For small signals r1 = r 2 and gm1 = gm2
v1 = −v 2
For differential operation vin1 = −vin2 , and using the above KVL
2vin1 = 2v 1
which implies that
vP = vin1 − v1 = 0
31
 Half Circuits

vout1 vout 2

vout1 = −g m RC vin1
vout 2 = −g m RC vin2

vout1 − vout 2
= −g m RC
vin1 − vin 2
➢ Since VP is grounded, we can treat the differential pair as two CE
“half circuits”, with half the output swing on either side
➢ If the circuit is symmetrical, we can just analyze the half-circuit
with a virtual ground to get the gain equation
CH 10 Differential Amplifiers 32
 Example: Differential Gain

w/ finite ro

vout 1 − vout 2
= − g m rO
v in1 − v in 2

CH 10 Differential Amplifiers 33
 Extension of Virtual Ground

Symmetry Axis

VX = 0

➢ It can be shown that if R1 = R2, and points A and B go up

and down by the same amount respectively, VX does not
move.
CH 10 Differential Amplifiers 34
 Half Circuit Example I

R1 = R2

Av = −g m1 (rO1 || rO3 || R1 )
CH 10 Differential Amplifiers 35
 Half Circuit Example II

Av = −g m1 (rO1 || rO3 || R1 )
CH 10 Differential Amplifiers 36
 Half Circuit Example III

assuming  = 1 for simplicity

RC
Av = −
1
RE +
gm
CH 10 Differential Amplifiers 37
 Half Circuit Example IV

assuming  = 1 for simplicity

RC
Av = −
RE 1
+
CH 10 Differential Amplifiers
2 gm 38
BJT Differential Pair Input Resistance

• In order to obtain the differential input resistance, apply a

test differential voltage vX and find the developed current iX
v1 v
= iX = −  2
r1 r 2
vX = v 1 − v 2 = 2r iX
v
Differential Rin = X = 2r
iX
39
Agenda
• General considerations
• Bipolar differential pair
• MOS differential pair
• Cascode differential amplifiers
• Common-mode rejection
• Differential pair with active load

40
 MOS Differential Pair’s Common-Mode Response

ISS ISS
I SS
2 2 VX = VY = VDD − RD
2

➢ Similar to its bipolar counterpart, MOS differential pair

produces zero differential output as VCM changes.

CH 10 Differential Amplifiers 41
 Equilibrium Overdrive Voltage

n Cox W
Using Saturation I D = (VGS − VTH )2
2 L

ISS ISS
I SS
2 2 (VGS −VTH )equil = W
nCox
L

➢ The equilibrium overdrive voltage is defined as the overdrive

voltage seen by M1 and M2 when both carry an ISS/2 current
➢ Larger tail current or smaller W/L results in a larger equilibrium
overdrive voltage
CH 10 Differential Amplifiers 42
 Minimum Common-mode Output Voltage

I SS
VDD − RD  VCM −VTH
2

➢ In order to maintain M1 and M2 in saturation, the common-

mode output voltage cannot fall below the value above.
➢ This value usually limits voltage gain.
CH 10 Differential Amplifiers 43
 Differential Response

CH 10 Differential Amplifiers 44
 Small-Signal Response

V P = 0
Av = − g m RD

➢ Similar to its bipolar counterpart, the MOS differential pair

exhibits the same virtual ground node and small signal
gain.
CH 10 Differential Amplifiers 45
 Power and Gain Tradeoff

➢ In order to obtain the source gain as a CS stage, a MOS

differential pair must dissipate twice the amount of current
(assuming the same MOSFET overdrive voltage). This power
and gain tradeoff is also echoed in its bipolar counterpart.
CH 10 Differential Amplifiers 46
 MOS Differential Pair’s Large-Signal Response

1. Writing a KVL around the input network

Vin1 −VGS1 = Vin2 − VGS 2
2. Writing a KCL at the tail node
ID1 + I D2 = ISS
nCox W
(VGS −VTH )2
2ID
Using I D = and VGS = VTH +
2 L W
nCox
L

Vin1 −Vin2 = VGS1 − VGS 2 =

2
W
( I D1 − I D2 )
nCox
L
Squaring both sides

(Vin1 −Vin2 )2 = 2
(I + I − 2
W D1 D2
I D1I D2 )=
2
W
(ISS − 2 I D1I D2 )
nCox nCox
L L
CH 10 Differential Amplifiers 47
 MOS Differential Pair’s Large-Signal Response

After some algebraic manipulations (see Razavi10.3.2), can show that

ISS Vin1 − Vin2
I D1 = + nCox W 4I SS − nCox W (Vin1 −Vin2 )2 
2 4 L  L 
ISS Vin2 −Vin1 4I −  C W (V − V )2 
I D2 = + nCox W  SS n ox in1 
2 4 L L in2 

*Note, this equation

n Cox W
(Vin1 − Vin2 ) − (Vin1 − Vin2 )2
4ISS is only valid for a
I D1 − I D2 =
2 L W certain maximum
nCox
L input differential
voltage Vin1 – Vin2
CH 10 Differential Amplifiers 48
 Maximum Differential Input Voltage

n Cox W
(Vin1 − Vin2 ) − (Vin1 − Vin2 )2
4ISS
ID1 − I D2 =
2 L W
nCox
L
The above equation is only valid when both M1 and M 2 are on.
This stops when VGS 2 = VTH and VGS1 supports a full ISS value.
2ISS
VGS1 = VTH +
W
nCox
L

Vin1 −Vin2 max = 2(VGS − VTH )equil =

2ISS
W
nCox
L
➢ There exists a finite differential input voltage that completely
steers the tail current from one transistor to the other. This
value is known as the maximum differential input voltage.
CH 10 Differential Amplifiers 49
 Contrast Between MOS and Bipolar Differential Pairs

MOS Bipolar

nCox W  V −V 
(Vin1 − Vin2 ) − (Vin1 − Vin2 )2
4ISS
Vout1 − Vout 2 = −R D Vout1 − Vout 2 = −RC I EE tanh in1 in2 
2 L W  2VT 
nCox
L

➢ In a MOS differential pair, there exists a finite differential

input voltage to completely switch the current from one
transistor to the other, whereas, in a bipolar pair that
voltage is infinite.

CH 10 Differential Amplifiers 50
 The effects of Doubling the Tail Current

➢ Since ISS is doubled and W/L is unchanged, the equilibrium

overdrive voltage for each transistor must increase by 2
to accommodate this change, thus Vin,max increases by 2
as well. Moreover, since ISS is doubled, the differential
output swing will double.
➢ Small signal gain also increases by 2
➢ Linear input range increases, assuming RD value is small
enough to keep transistors in saturation
CH 10 Differential Amplifiers 51
 The effects of Doubling W/L

➢ Since W/L is doubled and the tail current remains

unchanged, the equilibrium overdrive voltage will be
lowered by 2 to accommodate this change, thus Vin,max
will be lowered by 2 as well. Moreover, the differential
output swing will remain unchanged since neither ISS nor RD
has changed
➢ Small signal gain increases by 2
➢ Linear input range decreases
CH 10 Differential Amplifiers 52
 Small-Signal Analysis of MOS Differential Pair

n Cox W
− (Vin1 − Vin2 )2
4ISS
I D1 − I D2 = (Vin1 − Vin2 ) W
2 L nCox
L
n Cox W W I 
(Vin1 − Vin2 ) 2 SS  (Vin1 − Vin2 ) = g m (Vin1 − Vin2 )
4ISS
 = nCox
2 L W L  2 
nCox
L

➢ When the input differential signal is small compared to

4ISS/nCox(W/L), the output differential current is linearly
proportional to it, and small-signal model can be applied.

CH 10 Differential Amplifiers 53
 Virtual Ground and Half Circuit

RD RD
vout1 vout 2

𝑣௢௨௧ଵ ൌ ൌ 𝑔௢𝑅௢𝑣௢௢ଵ ௢
𝑣௢௨௧ଶ ൌ ൌ 𝑔௢𝑅௢𝑣௢௢ଶ
௩ ௢ ௢

➢ Applying the same analysis as the bipolar case, we will

arrive at the same conclusion that node P will not move for
small input signals and the concept of half circuit can be
used to calculate the gain.
CH 10 Differential Amplifiers 54
Small-Signal Impedance:
Simple Current Source (Finite ro)

1
rout =
go

55
Small-Signal Impedance:
“Diode” Load (Finite ro)

1 1 1
rout = ro = 
gm g m + go g m

56
Small-Signal Impedance:
Looking Into Source (Finite ro and gmb)

io = (gm + g mb )vo + = (gm + g mb + g o )vo

vo
ro
1 1 1 1
rout = = ro 
gm + gmb + go gm gmb gm
57
Small-Signal Impedance:
Looking Into Source w/ RD (Finite ro and gmb)

1  RD 
rout = 1+ 
g m + g mb + g o  ro 

58
 MOS Differential Pair Half Circuit Example I

1 1
rout = ro 
gm gm

 0
 1  g
Av = −g m1 || rO3 || rO1   − m1
 g m3  g m3
CH 10 Differential Amplifiers 59
 MOS Differential Pair Half Circuit Example II

=0
g m1
Av = −
g m3
CH 10 Differential Amplifiers 60
 MOS Differential Pair Half Circuit Example III

=0
RDD 2
Av = −
RSS 2 +1 g m
CH 10 Differential Amplifiers 61
Agenda
• General considerations
• Bipolar differential pair
• MOS differential pair
• Cascode differential amplifiers
• Common-mode rejection
• Differential pair with active load

62
Maximum Differential Amplifier Gain

w/ finite ro

• With ideal current source

loads, the differential gain is
limited by the intrinsic
transistor gain (gmro)
vout 1 − vout 2
= − g m rO • How to increase the gain
v in1 − v in 2 further?
• Use a topology which boosts
the output resistance
63
Bipolar Cascode Topology

vx = io (r3 ro1)
Writing a KCL at the output node
vo − vx
− io + g m3 (− vx )+ =0
o

ro3
io (r3 ro1 )
− io − g m3io (r 3 ro1 )−
v
=− o m3 x o3
o
ro3 ro3 x

= ro3 + r 3 ro1 + g m3 ro3 (r 3 ro1 ) g m3 ro3 (r 3 ro1 )

vo
Rout =
io
o1 3
The dominant term is the bottom effective resistance
boosted by the gain of the top transistor (gm3ro3) 64
 Bipolar Cascode Differential Pair

Cascode Output Resistance

Rout = ro3 + ro1 r 3 + gm3ro3 (ro1 r 3 )
 gm3ro3 (ro1 r 3 )

• Gain is roughly
squared relative
to the simple

Av = − g m1 ro3 + ro1 r 3 + g m 3 ro3 (ro1 r 3 )

differential pair
• Trade-off is

 − g m1 g m 3 ro3 (ro1 r 3 )
reduced output
voltage swing
range
SlightCH
approximation here. More when we study Cascodes in detail.
10 Differential Amplifiers 65
 Bipolar Telescopic Cascode

Av = −gm1(ro3 + ro1 r 3 + gm3ro3 (ro1 r 3 )(ro5 + ro7 r 5 + gm5ro5 (ro7 r 5 )

 −gm1(gm3ro3 (ro1 r 3 )(gm5ro5 (ro7 r 5 )
CH 10 Differential Amplifiers 66
 Example: Bipolar Telescopic Parasitic Resistance

 r R1   R1 r R1 
Rop = rO 5 1 + g m5  O 7 || r 5 ||  + rO 7 || r 5 ||  g m5 rO 5  O 7 || r 5 || 
  2  2  2 
Av = − gm1gm3rO 3 (rO1 || r 3 )|| Rop
CH 10 Differential Amplifiers 67
MOS Cascode Topology

vx = ioro1
Writing a KCL at the output node
vo − v x
− io + g m3 (− vx )+ =0
o

ro3
ir v
− io − gm3ioro1 − o o1 = − o m3 x o3
o
ro3 ro3 x

vo
Rout = = ro3 + ro1 + g m3 ro3 ro1  g m3 ro3 ro1
io
o1
The dominant term is the bottom effective resistance
boosted by the gain of the top transistor (gm3ro3) 68
 MOS Cascode Differential Pair

Cascode
Output
Resistance
Rout = ro3 + ro1 + gm3ro3ro1
 gm3ro3ro1

• Gain is roughly squared

Av = − gm1ro3 + ro1 + g m 3ro3ro1  relative to the simple
differential pair
 − g m1 g m 3ro3ro1 • Trade-off is reduced output
voltage swing range
CH 10 Differential Amplifiers 69
 MOS Telescopic Cascode

Av  −g m1 (gm3rO3rO1 ) || (g m5 rO5 rO7 )

CH 10 Differential Amplifiers 70
 Example: MOS Telescopic Parasitic Resistance

Rop = ro5 R1 + ro7 + g m 5 (ro5 R1 )ro7  g m 5 (ro5 R1 )ro7

Av  − gm1gm 3ro3ro1 g m 5 (ro5 R1 )ro7 
CH 10 Differential Amplifiers 71
Agenda
• General considerations
• Bipolar differential pair
• MOS differential pair
• Cascode differential amplifiers
• Common-mode rejection
• Differential pair with active load

72
 Effect of Finite Tail Impedance

RC
2

Assuming =1
Vout ,CM RC / 2
=−
Vin,CM REE +1/ 2g m
➢ If the tail current source is not ideal, then when a input CM
voltage is applied, the currents in Q1 and Q2 and hence
output CM voltage will change.
CH 10 Differential Amplifiers 73
 Input CM Noise with Ideal Tail Current

CH 10 Differential Amplifiers 74
 Input CM Noise with Non-ideal Tail Current

• Common-mode noise is now transferred to the single-ended outputs

• However, output differential signal is still ideally unaffected by common-
mode noise
CH 10 Differential Amplifiers 75
 Comparison

➢ As it can be seen, the differential output voltages for both

cases are the same. So for small input CM noise, the
differential pair is not affected.
CH 10 Differential Amplifiers 76
 CM to DM Conversion, ACM-DM

Assuming high ro in the diff. pair transistors

ID1 = I D2 = I D and VGS1 = VGS2 = VGS
A net current of 2I D will flow through RSS
VCM = VGS + 2IDRSS
 1 
VCM = I D  + 2RSS 
 gm 
VCM
I D =
1
+ 2R SS
gm
Vout = Vout1 − Vout 2 = I D R D − I D (RD + RD ) = −IDRD
VCM
Vout = − RD
1
+ 2R SS
➢ If finite tail impedance and gm
asymmetry are both present, Vout R D
then the differential output =
VCM 1
+ 2RSS
signal will contain a portion of gm
input common-mode signal.
CH 10 Differential Amplifiers 77
 Example: ACM-DM

Vout RC
ACM −DM = =
VCM 1
+ 2Rout3
gm1
RC
=
+ 2ro3 + R1 r 3 + g m3 ro3 (R1 r 3 )
1
gm1

CH 10 Differential Amplifiers 78
 CMRR

RC + RC

ADM
CMRR =
ACM −DM
gm RC RC + 2g m RC REE
= =
  RC
 
 RC 
 1 
g + 2R EE 
 m 

➢ CMRR defines the ratio of wanted amplified differential

input signal to unwanted converted input common-mode
noise that appears at the output.
CH 10 Differential Amplifiers 79
Agenda
• General considerations
• Bipolar differential pair
• MOS differential pair
• Cascode differential amplifiers
• Common-mode rejection
• Differential pair with active load

80
 Differential to Single-ended Conversion

Simple OpAmp

➢ Many circuits require a differential to single-ended

conversion, however, the above topology is not very good.
CH 10 Differential Amplifiers 81
 Supply Noise Corruption

➢ The most critical drawback of this topology is supply noise

corruption, since no common-mode cancellation
mechanism exists. Also, we lose half of the signal.
CH 10 Differential Amplifiers 82
 Gain Reduction

vin1 = +vin
vin2 = −vin
vout = −g m (− vin )RC
+ vin =
vout g R v g R
= m C in = m C
vin1 − vin2 2vin 2
− vin =

➢ The most critical drawback of this topology is supply noise

corruption, since no common-mode cancellation
mechanism exists. Also, we lose half of the signal.
CH 10 Differential Amplifiers 83
 Better Alternative

Current Mirror or
“Active” Load

➢ This circuit topology performs differential to single-ended

conversion with no loss of gain.
CH 10 Differential Amplifiers 84
 Active Load

IEE
~ + I
2

➢ With current mirror used as the load, the signal current

produced by the Q1 can be replicated onto Q4.
➢ This type of load is different from the conventional “static
load” and is known as an “active load”.

CH 10 Differential Amplifiers 85
 Differential Pair with Active Load

IEE Vout = 2IRL

+ I 2I
2

➢ The input differential pair decreases the current drawn from

RL by I and the active load pushes an extra I into RL by
current mirror action; these effects enhance each other.
CH 10 Differential Amplifiers 86
 Active Load vs. Static Load

Active Load Static Load

 2I  I  I

➢ The load on the left responds to the input signal and

enhances the single-ended output, whereas the load on the
right does not.
CH 10 Differential Amplifiers 87
 MOS Differential Pair with Active Load

Vout = 2IRL

ISS ISS
+ I + I
2 2 2I

ISS
− I
2

➢ Similar to its bipolar counterpart, MOS differential pair can

also use active load to enhance its single-ended output.

CH 10 Differential Amplifiers 88
 Asymmetric Differential Pair

➢ Because of the vastly different resistance magnitude at the

drains of M1 and M2, the voltage swings at these two nodes
are different and therefore node P cannot be viewed as a
virtual ground.
CH 10 Differential Amplifiers 89
 Thevenin Equivalent of the Input Pair

To Find RThev

vThev = −g mN roN (vin1 − vin 2 )

RThev = 2roN
CH 10 Differential Amplifiers 90
 Simplified Differential Pair with Active Load

vA can be viewed as a divided version of vE

1
ro3
gm3
vA =
1
(vout + vThev )
ro3 + RThev
g m3
Writing a KCL at the output node
vout vout + vThev
g m4 v A + + =0
ro4 1
ro3 + RThev
g m3
 1 
 ro3 
 g m3 1  vout
 g m4 + (vout + vThev )+ =0
1 1 r
 ro3 + RThev ro3 + RThev  o4
 g m3 gm3 
since1 gm3  ro3 and 1 gm3  RThev and gm3 = gm4 = gmP and ro3 = ro4 = roP
2
(vout + vThev )+ vout =0
vout RThev roP

= gmN (rON || rOP ) vout

= g mN (roN roP )

vin1 − vin 2 vin1 − vin2

CH 10 Differential Amplifiers 91
Next Time
• Cascode Stages & Current Mirrors
• Razavi Chapter 9

92